A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces

Differential signaling is effective in suppressing common-mode noise in parallel links as well as in high-speed serial links. However, differential signaling is not cost effective for DRAM interfaces because the I/O-pin count is a significant portion of the chip cost. Since differential signaling requires 2n pins and channels to transmit n bits of data, the data rate must be doubled compared to single-ended signaling to accomplish the same per-pin data rate. However, ISI due to channel-bandwidth limits and technology limits degrade the performance [1]. Although single-ended signaling achieves a higher data rate per pin, two major problems limit increases of the data rate: reference ambiguity and power-supply fluctuation [2]. Several works are reported to solve the problems of single-ended signaling [3–7]. However, the skew between encoder outputs in [3] and receiver outputs in [4,5] degrades the performance of transceivers and the signaling in [6,7] keeps the reference signal. We describe pseudo-differential signaling schemes for DRAM interfaces that minimize the skew between data and suppress common-mode noise. The chip is implemented in a 0.13µm process and occupies 2.7×2.3mm2 and the active area is 1.0×0.3mm2.