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In this work, graphene nanodots have been fabricated and characterized as it has the potential for nanodevices application. Here we show non-volatile memory devices based on the capacitor structure by using graphene nanodots as the charge storage nodes. The graphene nanodots on silicon dioxide tunneling barrier were fabricated by etching the graphene with gold nanoparticles as self-aligned mask. Furthermore, different blocking oxide layer were also adopted to optimize the memory characteristics, including retention and operation speed. The memory of graphene nanodots with high-k blocking oxide layer shows higher flat-band voltage shift at low programming voltage, and excellent charge loss less than 12% after 104 sec, potentially provides a promising route for non-volatile memory application.

In this work, two-dimensional MoS2 has been performed for nonvolatile memory application as charge storage layer. The capacitance-voltage (C-V) hysteresis and programming characteristics of MoS2-NVMs with blocking oxide layer of various thicknesses have been further investigated. The MoS2-NVMs with 9-nm-thck blocking oxide layer exhibits a large hysteresis in the C-V sweeping and the fastest speed in programming characteristics. In addition, both electrons and holes can store in MoS2 monolayer, contributing to a promising application in future high-performance NVMs.

The influence of current compliance (I CC ) on resistive switching (RS) of silver programmable metallization cells (Ag-PMCs) with stacked SiO x /SiO 2 solid electrolytes has been investigated by carrier transportation and capacitance-voltage measurements. The low I CC of 10 μA leads to the superior multilevel RS characteristics because of a locally discontinuous conductive filament within the stacked solid electrolytes. Possible RS mechanisms of Ag-PMCs with different I CC are proposed according to the electrical analyses. Thus, the stacked-solid-electrolyte Ag-PMCs are considered as the promising candidate for future high-density nonvolatile memory application.

Ultra-fast (μsec) and disturb-free multilevel flash memory was demonstrated by a novel gold and gadolinium oxide bi-nanocrystals (BNCs). Through nanocrystal band engineering design and using a new operation scheme, the BNCs memory exhibits an ultra-fast program and erase speed for 3.5μsec and 5μsec respectively, which is three orders faster than the conventional one. A disturb-free behavior is achieved for operating under -14 to 9 V. The threshold voltage memory window (2.78 V for 4 bits) closure is only 7.3% under 108 cycling and with only 10% charge loss for 104 sec retention. The activation energy of charge loss and trapped charge centroid were extracted to identify the nanocrystal band engineering and carrier injection mechanism.

Different post-metallization annealing gas ambient has been performed in the gadolinium oxide resistive switching memories to enhance the fabrication yield. The superior memory properties such as the low set and reset voltages (−1.4 V and 2.1 V) and high resistance ratio (∼104) are successfully achieved. With no degradation of the memory characteristics, the fabrication yield of the oxygen post-metallization annealed gadolinium oxide resistive switching memories can be increased to over 60% due to the sufficient mobile oxygen ions supplied in the gadolinium oxide layers.

In this paper, we demonstrate gadolinium oxide RRAM with nitrogen plasma immersion ion implantation (PIII) treatment technique at first time. For nitrogen plasma treatment, the nitrogen ions were incorporated with gadolinium oxide. We controlled the implantation voltage that the nitrogen ions exist near the surface of gadolinium oxide and it was forming a GdxOyNz layer. This can reduce the leakage current to reach a low current and power consumption operation. In addition, the retention and endurance characteristics were also improved.

In-Ga-Zn-O (IGZO) was widely applied in the substrate of TFT to replace a-Si in recent year. In this study, IGZO layer with thickness of 70 nm is first proposed as a pH sensing membrane directly on P-type Si substrate acting as an extended gate of conventional extended-gate field-effect Transistor (EGFET). Material criteria of extended gate electrode are low resistance and high capacitance. Therefore, Ar/O2 ratio was modified in the rf sputtering with IGZO target. Post deposition anneal was also performed to check the sheet resistance and pH sensing performance. EGFETs were measured in standard pH buffer solution by using B1500A and constant voltage constant current (CVCC) circuit. Similar IDS-VGS curves including transconductance (Gm) and substrate swing (S.S.) are obtained in various sputtering conditions of IGZO compared to commercial NMOSFET in CD4007. pH application range is only between pH 2 to pH 10. IGZO-EGFET prepared by Ar/O2 ambience of 24/1 in sputtering can have a sensitivity of 59.5 mV/pH. Lower sensitivity and linearity can be observed in the samples with RTA treament at higher temp and in O2 ambience. N2 anneal at 500°C can be used to improve pH sensing performance for IGZO-EGFET prepared by Ar/O2 ambience of 20/5 in sputtering. Nano-IGZO layer is verified to be the sensing membrane in EGFET to have a high sensitivity of 59.5 mV/pH for the first time. More studies on enlargement pH application range and minimization of non-ideal effect still need to be investigated.

The gadolinium oxide nanocrystal (Gd2O3-NCs) memory has been demonstrated with large memory window and good reliabilities. It has been proven that the charges are stored in the crystallized Gd2O3-NCs which are surrounded by trapping-free amorphous phase of Gd2O3 film. The calculated deep trapping energy level is about 1.7eV below the conduction of the Gd2O3-NCs, and the energy band diagram of the Gd2O3-NCs memory has been proposed. In this study, we optimize the thickness of Gd2O3 thin film to investigate the effect on the charge storage mechanism. The thickness of Gd2O3 thin film and blocking oxide could simultaneously dominate the operation speed and charge loss phenomenon. Thus, the most suitable film thicknesses for the Gd2O3-NCs memory were proposed for future mass production nonvolatile memory application.

As a potential candidate for future nonvolatile memory (NVM) application, the discrete charge storage nodes formed as the nanocrystal (NC) structure has been caught much attention. Among the NC materials, high-k metal oxide is the unique one due to the mixed chemical reactions during high temperature forming process. The over-view of gadolinium oxide nanocrystal (Gd 2 O 3 -NC) memory is revealed in this paper. Gd 2 O 3 -NC was formed by one step rapid thermal annealing treated on the amorphous Gd 2 O 3 film prepared by sputter system. The optical tests were conducted to exam the bandgap value of the Gd 2 O 3 -NC and the x-ray tests were conducted to exam the valence band offset. The charge trapping phenomenon can be characterized by the retention tests for various temperatures. Forming gas annealing was treated on the Gd 2 O 3 -NC to passivate the deep traps. A band engineered method by CF 4 plasma treatment was also conducted to improve the memory characteristics.

In this paper, we have studied the I d variation in linear and saturation region by considering the strain-induced effect and the carrier transport of strained CMOS devices. It was found that the origin of linear I d variation comes from the mobility scattering; while in saturation region, the I d variation is dominated by the injection velocity. The higher the injection velocity is, the smaller the saturation I d variation becomes. These results provide us a guideline for achieving good variability control of strain-based CMOS technologies.

Recently, nanocrystal (NC) memory such as gadolinium oxide NC (Gd 2 O 3 -NC) memory performed by the band-gap offset of a crystallized Gd 2 O 3 -NC dots surrounded by the amorphous Gd 2 O 3 dielectrics has been proposed [1–2]. The crystallization temperature was optimized and the excellent memory properties were obtained [2]. In addition, to improve the programming/erasing (P/E) and retention characteristics of future nonvolatile memory, the BE-SONOS with SiO 2 /SiN/ SiO 2 (ONO) tunneling layer has been proposed due to the suitable band engineering and large physical thickness [3]. In this paper, the novel Gd 2 O 3 -NC memory with HfO 2 charge trapping layer was investigated and multi-tunneling layer (Al 2 O 3 /IL-SiO 2 ) was applied to further improve the performance. The charge storage characteristic was related to the charge trapping phenomenon of HfO 2 layer.

Electrolyte-insulator-semiconductor (EIS) devices with programmable Sm 2 O 3 /Si 3 N 4 /SiO 2 and HfO 2 /gadolinium oxide nanocrystals (Gd 2 O 3 -NCs)/SiO 2 structures are demonstrated for pH detection. The proposed programmable EIS sensors with multiple sensing membranes exhibit a high pH sensitivity (larger than the ideal Nernst response, 59.16 mV/pH at 25 °C) owing to the hydrogen ions attraction by electrons trapped within the embedded trapping layers (Si 3 N 4 and Gd 2 O 3 -NCs) after programming. When compared with the conventional EIS devices, the programmable EIS sensors with programming provide the possibility for the small pH fluctuation detection and can be used in future pH sensor applications owing to its high pH sensing response.

In this article, the development of a potassium ion sensor based on the fluorinated-HfO 2 using fluorine (F19+) ion implantation on Electrolyte-Insulator-Semiconductor (EIS) structure is proposed. To concentrate the F atom within a shallow region on HfO 2 sensing membrane surface, relatively low implant power and big tilt angle are chosen. With suitable F19+ implant dosage, the pK sensitivity can be effectively improved from 18.19 to 112 mV/pK, and relatively low drift coefficient of 2.62 mV/h is also achieved in 10 mM potassium electrolyte. To investigate the surface roughness and the fluorine depth profile of the implanted-HfO 2 films, physics analysis including AFM and XPS are both performed.

In this work, discussing the detection of NH 4 + ion based on LAPS with functionalized 2 nm-thick ALD-HfO 2 film using RTA and CF 4 plasma is demonstrated. The annealing treatment at 500, 700, and 900°C were performed on ALD-HfO 2 film and the plasma treatment for 1, 3, and 5 min were performed on ALD-HfO 2 film with 900°C annealing. In the results, the response for NH 4 + ion detection was decreased with increasing annealing temperature and increased with increasing plasma time. The optimum sensitivity of 37.28mV/pNH 4 was achieved with 900°C annealing and 5 min CF 4 plasma.

Improvement of Fermi-level pinning (FLP) and relaxation of negative-bias-temperature-instability (NBTI) for CMOS without interfacial layers was achieved by fluorine incorporation into HfO 2 . The driving current capability was increased up to 48% and 45% for n-MOSFET and p-MOSFET, respectively. It's caused by the oxygen vacancy was blocked by the fluorine incorporated interface and resulted in the suppression of the interfacial oxide growth to achieved thinner effective oxide thickness (EOT). The improvement included the Fermi-level pinning shift from ∼0.1eV to ∼0.02eV for samples without and with fluorination, respectively. V th shifts under NBTI stressing were relaxed from positive 350mv to negative 270mv for control and fluorinated samples, respectively. It is due to the Si-F bondings broken under NBTI stressing which the released-fluorine re-incorporate to passivate the HfO 2 bulk.

Fluorine distribution engineering in HfO 2 to get higher performance (HP EOT=1.2nm) and low stand-by power (LSTP EOT=1.8nm) CMOS device with 48% driving current enhancement for HP, 73% leakage reduction for LSTP were demonstrated. Better uniformity (50% VtU and 9% IdU reduction) and excellent reliability, P/NBTI, of n-/p-MOSFET were achieved A new physical model of fluorine re-incorporation was proposed to explain the turnaround of NBTI and the much improvement of NBTI for HP and LP device.

In this paper, we demonstrate TaN/fluorinated HfO2 CMOS devices, focusing on symmetry and asymmetry fluorine incorporation at top or bottom HfO2 interfaces. 16% permittivity enhancement, 65% and 91% mobility increases for electron and hole, respectively, under high electric field was achieved. Reliability of n- and p-MOSFET was improved 3 orders and 8% for GIDL and hot carrier immunity, respectively. A physical model of shallow and deep trapping level affected by fluorine was proposed to explain the NBTI and PBTI improvements.

High-performance wrapped-select-gate (WSG) SONOS (silicon-oxide-nitride-silicon) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism with different ONO thickness in WSG-SONOS memory was well investigated. The different programming efficiency of the WSG-SONOS memory with different ONO thickness can be explained by the lateral electrical field extracted from the simulation. Furthermore, multi-level storage is easily obtained and well Vth distribution is also presented. High program/erase speed (10 us/5 ms) and low programming current (3.5 u/A) are performed to achieve the multi-level operation with excellent gate and drain disturbance, second-bit effect, data retention and endurance.

High-performance CESL strained nMOSFET with HfO2 gate dielectrics has been successfully demonstrated in this work. It is found that, the transconductance (gm) and driving current (Ion) of the nMOSFETs increase 70% and 90%, respectively, of the increase of devices with a 300 nm capping nitride layer. A superior HfO2/Si interface for CESL-devices is observed, demonstrated by an obvious interface state density reduction (6.56times1011 to 9.85times1010 cm-2). Further, a roughly 50% and 60% increase of gm and Ion, respectively, can be achieved for the 300 nm SiN-capped HfO2 nMOSFET without considering charge trapping under pulsed-IV measurement.

In this paper, we have investigated the properties and carrier transportation of ultra-thin cerium dioxide films with rapid thermal annealing. Improved characteristics such as low leakage current, high breakdown voltage and large time-dependent-dielectric-breakdown (TDDB) are obtained owing to the more stoichiometric quality of the CeO/sub 2/ films after high temperature annealing. Moreover, temperature dependence of gate leakage current under substrate injection is studied, and the carrier conduction mechanisms, including the Frenkel-Poole (F-P) conduction and the Fowler-Nordheim (F-N) tunneling are also proposed, from which we have deduced the energy band diagram of Al/CeO/sub 2//n-Si structure for the first time.