81 results on '"JAOUEN, H."'
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2. New compact model for performance and process variability assessment in 14nm FDSOI CMOS technology
3. Experimental and theoretical investigation of the ‘apparent’ mobility degradation in Bulk and UTBB-FDSOI devices: A focus on the near-spacer-region resistance
4. The importance of the spacer region to explain short channels mobility collapse in 28nm Bulk and FDSOI technologies
5. A new approach for modeling drain current process variability applied to FDSOI technology
6. Effective field and universal mobility in high-k metal gate UTBB-FDSOI devices
7. Mobility in high-K metal gate UTBB-FDSOI devices: From NEGF to TCAD perspectives
8. Limits and improvements of TCAD piezoresistive models in FDSOI transistors
9. TCAD modeling challenges for 14nm FullyDepleted SOI technology performance assessment.
10. Modeling study of the SiGe/Si heterostructure in FDSOI pMOSFETs
11. Electron-phonon scattering in Si and Ge: From bulk to nanodevices
12. Mechanical issues induced by Electrical Wafer Sort: Correlations from actual tests, nanoindentation and 3D dynamic modeling
13. Characterization & modeling of gate-induced-drain-leakage with complete overlap and fringing model
14. On the accuracy of current TCAD hot carrier injection models for the simulation of degradation phenomena in nanoscale devices
15. Thermal effects modeling of multi-fingered MOSFETs based on new specific test structures
16. New self heating structures for thermal coupling modeling on multi-fingered SOI power devices
17. Transport masses in strained silicon MOSFETs with different channel orientations
18. Chip-package interactions: Some combined package effects on copper/low-k interconnect delaminations
19. Experimental and theoretical analysis of hole transport in uniaxially strained pMOSFETs
20. Electromigration induced failure mechanism: Multiphysics model and correlation with experiments
21. On the validity of the effective mass approximation and the luttinger k.p model in confined and strained 2D-holes-systems
22. Random telegraph signal noise SPICE modeling for circuit simulators
23. Low-Field Mobility in Strained Silicon with `Full Band' Monte Carlo Simulation using k.p and EPM Bandstructure
24. Monte Carlo simulation of ultimate DGMOS based on a Pearson Effective Potential formalism
25. Analysis and modeling of substrate impedance network in RF CMOS
26. A New Quasi Ballistic Model for Strained MOSFET.
27. Characterization and modelling of gate current injection in embedded non-volatile flash memory.
28. Characterization and Physical Modeling of Endurance in Embedded Non-Volatile Memory Technology.
29. Small signal analysis of electrically-stressed oxides with Poisson-Schroedinger based multiphonon capture model.
30. Mechanical issues induced by Electrical Wafer Sort: Correlations from actual tests, nanoindentation and 3D dynamic modeling.
31. Characterization & modeling of gate-induced-drain-leakage with complete overlap and fringing model.
32. Simulation of surface engineering for ultra shallow junction formation of PMOS for the 90nm CMOS technology node and beyond
33. Monitoring variability of channel doping profile in the 45nm node MOSFET through reverse engineering of electrical back-bias effect.
34. Monte Carlo-Based Analytical Models for Electron and Hole Electrical Parameters in Strained SiGeC Alloys.
35. Chip-package interactions: Some investigations on copper/Low-k interconnect delaminations.
36. Electrical characterization and compact modeling of MOSFET body effect.
37. Improved Test Structure for Thermnal Resistance Scaling Study in Power Devices.
38. A constitutive single crystal model for the silicon mechanical behavior: applications to the stress induced by silicided lines and STI in MOS technologies.
39. LDMOS modeling for analog and RF circuit design.
40. Strained Si/SiGe MOSFET capacitance modeling based on band structure analysis.
41. Impact of the CDM tester ground plane capacitance on the DUT stress level.
42. TCAD modelling of PLAD implantations and application to sub-65nm technological nodes [plasma doping].
43. FEM-based method to determine mechanical stress evolution during process flow in microelectronics. Application to stress-voiding.
44. Finite element analysis of stress evolution in Si based front and back ends micro structures.
45. Comparison between S-parameter measurements and 2D electromagnetic simulations for microstrip transmission lines on BiCMOS process.
46. Modeling arsenic activation and diffusion during furnace and rapid thermal annealing.
47. STORM: A European Platform for Sub-Micron Technology Simulation and Optimisation.
48. Sensitivity of PNP Doping Profiles to Annealing Conditions - Role of Dynamic Clustering Phenomena.
49. Dopant Activation and Defect Annihilation of Heavily Doped Arsenic Implanted Silicon Layers.
50. Programming efficiency and drain disturb trade-off in embedded Non Volatile Memories.
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