103 results on '"Sudhakar, M."'
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2. On reset based functional broadside tests.
3. Reducing the storage requirements of a test sequence by using a background vector.
4. Functional and partially-functional skewed-load tests.
5. State persistence.
6. Definition and application of approximate necessary assignments.
7. Partitioned n-detection test generation.
8. A scalable method for the generation of small test sets.
9. Improving compressed test pattern generation for multiple scan chain failure diagnosis.
10. Selection of a fault model for fault diagnosis based on unique responses.
11. A same/different fault dictionary.
12. A bridging fault model where undetectable faults imply logic redundancy.
13. On Tests to Detect Via Opens in Digital CMOS Circuits.
14. Test vector chains for increased targeted and untargeted fault coverage.
15. Circuit lines for guiding the generation of random test sequences for synchronous sequential circuits.
16. On test generation by input cube avoidance.
17. A delay fault model for at-speed fault simulation and test generation.
18. A test pattern ordering algorithm for diagnosis with truncated fail data.
19. The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits.
20. Defect Aware Test Patterns.
21. Worst-Case and Average-Case Analysis of n-Detection Test Sets.
22. On test generation for transition faults with minimized peak power dissipation.
23. On test data compression and n-detection test sets.
24. A scan BIST generation method using a markov source and partial bit-fixing.
25. Conflict driven techniques for improving deterministic test pattern generation.
26. On undetectable faults in partial scan circuits.
27. On output response compression in the presence of unknown output values.
28. Fast identification of robust dependent path delay faults
29. REDI.
30. ITEM.
31. On diagnosis of pattern-dependent delay faults.
32. Functional test generation for full scan circuits.
33. Built-in generation of weighted test sequences for synchronous sequential circuits.
34. Built-in test sequence generation for synchronous sequential circuits based on loading and expansion of test subsequences.
35. Proptest.
36. An approach for improving the levels of compaction achieved by vector omission.
37. Techniques for improving the efficiency of sequential circuit test generation.
38. Fault simulation under the multiple observation time approach using backward implications.
39. On static compaction of test sequences for synchronous sequential circuits.
40. Built-in test generation for synchronous sequential circuits.
41. Functional test generation for delay faults in combinational circuits.
42. On diagnosis and correction of design errors.
43. Test generation for path delay faults based on learning.
44. On path selection in combinational logic circuits.
45. NEST.
46. Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits.
47. INCREDYBLE-TG.
48. On testing delay faults in macro-based combinational circuits.
49. COMPACTEST-II.
50. An efficient non-enumerative method to estimate path delay fault coverage.
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