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For the first time, we report a short channel high performance, gate-all-around strained Si 0.4 Ge 0.6 nanosheet PMOSFET with aggressively scaled dimensions. We demonstrate realization of s-Si 0.4 Ge 0.6 nanosheet with 5nm thickness and device with L G =25nm featuring record high I ON =508 µA/µm at I OFF =100nA/µm and V DS = -0.5V. This result is obtained with the combination of (a) novel Si-cap-free gate oxide solution featuring thin EOT=9.1A, low D IT and N IT for s-Si 0.4 Ge 0.6 channel, (b) record high hole mobility= 450 cm2/Vs owing to compressive strain imparted by Si 0.7 Ge 0.3 strain relaxed buffer (SRB), (c) low R EXT =150 Ω-µm due to highly active, strained source/drain SiGe process and novel p++ cap layer, (d) optimized source/drain tip and junction to minimize GIDL impact to I OFF . Additionally, the impact of operating temperature on GIDL and I OFF is comprehensively studied to prescribe optimal V CC range of operation for this technology.

We report a short channel high performance Ge PMOS integrated with Si NMOS in sequential monolithic 3D stacking. A layer transfer Ge PMOS with record I ON = 497 μA/μm at I OFF = 8nA/μm and I ON = 630 μA/μm at I OFF = 100nA/μm and V DS = -0.5V is achieved for the first time. Optimized design of metal gate and contact on bottom Si NMOS device layer, along with a low process thermal budget developed for Ge layer transfer and top Ge PMOS device fabrication, allow for sequential stacking with no degradation on each MOS device characteristics. Heterogeneous 3D stacked Ge-Si CMOS inverter is also successfully demonstrated with drive performance maintained on Ge PMOS and Si NMOS.

Perhaps the greatest challenge facing quantum computing hardware development is the lack of a high throughput electrical characterization infrastructure at the cryogenic temperatures required for qubit measurements. In this article, we discuss our efforts to develop such a line to guide 300mm spin qubit process development. This includes (i) working with our supply chain to create the required cryogenic high volume testing ecosystem, (ii) driving full wafer cryogenic testing for both transistor and quantum dot statistics, and (iii) utilizing this line to develop a quantum dot process resulting in key electrical data comparable to that from leading devices in literature, but with unprecedented yield and reproducibility.

We investigate the structural and quantum transport properties of isotopically enriched Si28/SiO228 stacks deposited on 300-mm Si wafers in an industrial CMOS fab. Highly uniform films are obtained with an isotopic purity greater than 99.92%. Hall-bar transistors with an oxide stack comprising 10 nm of Si28O2 and 17 nm of Al2O3 (equivalent oxide thickness of 17 nm) are fabricated in an academic cleanroom. A critical density for conduction of 1.75×1011cm-2 and a peak mobility of 9800cm2/Vs are measured at a temperature of 1.7 K. The Si28/SiO228 interface is characterized by a roughness of Δ=0.4nm and a correlation length of Λ=3.4nm. An upper bound for valley splitting energy of 480μeV is estimated at an effective electric field of 9.5 MV/m. These results support the use of wafer-scale Si28/SiO228 as a promising material platform to manufacture industrial spin qubits.

Quantum computing's value proposition of an exponential speedup in computing power for certain applications has propelled a vast array of research across the globe. While several different physical implementations of device level qubits are being investigated, semiconductor spin qubits have many similarities to scaled transistors. In this article, we discuss the device/integration of full 300mm based spin qubit devices. This includes the development of (i) a 28 Si epitaxial module ecosystem for growing isotopically pure substrates with among the best Hall mobility at these oxide thicknesses, (ii) a custom 300mm qubit testchip and integration/device line, and (iii) a novel dual nested gate integration process for creating quantum dots.

Reducing the delay of backend interconnects is critical in delivering improved performance in next generation computer chips. One option is to implement interlayer dielectric (ILD) materials with increasingly lower dielectric constant (k) values. Despite industry need, there has been a recent decrease in study and production of these materials in academia and business communities. We have generated a backbone and porogen system that allows us to control porosity from 0 to 60% volume, achieve k-values from 3.4 to 1.6, maintain high chemical stability to various wet cleans, and deliver uniquely high mechanical strength at a given porosity. Finite element modeling and experimental results demonstrate that further improvements can be achieved through control of the pore volume into an ordered network. With hopes to spur more materials development, this paper discusses some molecular design and nanoscale hierarchical principles relevant to making next generation low-k ILD materials.

Ultrastable glasses are generated by vapor deposition on substrates heated near the glass transition temperature (Tg), but it is unclear if the remarkable properties of such glasses are present in ultrathin (100 nm) films. Here, we demonstrate that the moduli of 50 nm thick N,N'-di(1-naphthyl)-N,N'-diphenyl-(1,1'-biphenyl)-4,4'-diamine (NPD) film can be increased from 1.5 to 2.5 GPa by simply increasing the temperature of the substrate during deposition with a maximum in modulus found at T/Tg = 0.94. This maximum in modulus is the same modulus obtained for very thin (15 nm) NPD films deposited at 295 K (T/Tg = 0.80). However, the modulus of films deposited at this lower temperature abruptly decreases to approximately 1.5 GPa for thicker films; the modulus from deposition at T/Tg = 0.94 is thickness independent. In addition to the thin film modulus, the substrate temperature significantly impacts the water uptake in NPD films. From QCM, the volume fraction of water at equilibrium with nearly saturated water vapor decreases from nearly 4% to less than 1% as the substrate temperature increases from T/Tg = 0.82 to T/Tg = 0.93. The substrate temperature provides a simple route to control mechanical properties and water uptake into vapor-deposited NPD, and these concepts are likely extendable to other organic electronic materials; the increased moduli and decreased water uptake could enable improved performance and lifetime of small molecule glasses for a variety of organic electronic applications.

To lower interconnect signal delay, the industry continues to work on the integration of low-k interlayer dielectrics (ILD). Porosity is often added to further reduce dielectric constant and significantly impact capacitance. These porous dielectric films are most commonly deposited via Chemical Vapor Deposition (CVD), delivering a random order to the pore structure. Disordered films suffer from a reduction in mechanical properties, which ultimately limits the maximum porosity obtained due to film collapse. Control of porosity, pore size distribution and pore geometry is needed to extend the porosity beyond conventional percolation thresholds. Here we present the case study of a periodic mesoporous organosilica (PMO) film. We optimize solution processing to obtain an ordered film and characterize the film porosity, pore size distribution, geometry and mechanical properties. The PMO film is tested in both a dual damascene and replacement back end integration flow.

Planar capacitors can quickly test material properties of metals and dielectrics for interconnects. A sidewall capacitor device is used to evaluate metal thin-film barriers. Etch stop planar capacitors in turn can test multi-layer etch stops, exposing differences between leaky and good etch stop films. Fillable planar capacitors are also fabricated and results presented for that class of fill materials.