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300mm Heterogeneous 3D Integration of Record Performance Layer Transfer Germanium PMOS with Silicon NMOS for Low Power High Performance Logic Applications
- Source :
- 2019 IEEE International Electron Devices Meeting (IEDM).
- Publication Year :
- 2019
- Publisher :
- IEEE, 2019.
-
Abstract
- We report a short channel high performance Ge PMOS integrated with Si NMOS in sequential monolithic 3D stacking. A layer transfer Ge PMOS with record I ON = 497 μA/μm at I OFF = 8nA/μm and I ON = 630 μA/μm at I OFF = 100nA/μm and V DS = -0.5V is achieved for the first time. Optimized design of metal gate and contact on bottom Si NMOS device layer, along with a low process thermal budget developed for Ge layer transfer and top Ge PMOS device fabrication, allow for sequential stacking with no degradation on each MOS device characteristics. Heterogeneous 3D stacked Ge-Si CMOS inverter is also successfully demonstrated with drive performance maintained on Ge PMOS and Si NMOS.
- Subjects :
- 010302 applied physics
Fabrication
Materials science
Silicon
business.industry
Stacking
chemistry.chemical_element
Germanium
Hardware_PERFORMANCEANDRELIABILITY
02 engineering and technology
021001 nanoscience & nanotechnology
01 natural sciences
PMOS logic
chemistry
0103 physical sciences
Hardware_INTEGRATEDCIRCUITS
Optoelectronics
Inverter
0210 nano-technology
business
Metal gate
NMOS logic
Hardware_LOGICDESIGN
Subjects
Details
- Database :
- OpenAIRE
- Journal :
- 2019 IEEE International Electron Devices Meeting (IEDM)
- Accession number :
- edsair.doi...........75e7b3524af2d1b2c9ac22c6739970bb
- Full Text :
- https://doi.org/10.1109/iedm19573.2019.8993626