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Monte-Carlo radiation transport code is coupled with SPICE circuit level simulation to identify regions of single event upset vulnerability in an SEU hardened flip-flop, as well as predict single event upset cross sections and on-orbit soft error rates under static and dynamic operating conditions. Index Terms--Geant4, MRED, rate prediction, SEU, SPICE.

As integrated circuits become smaller and more complex, it has become increasingly difficult to simulate their responses to radiation. The distance and time scales of relevance extend over orders of magnitude, requiring a multi-scale, hierarchical simulation approach. This paper demonstrates the use of multi-scale simulations to examine two radiation-related problems: enhanced low-dose-rate sensitivity (ELDRS) in bipolar transistors and single-event effects (SEE) in CMOS integrated circuits. Examples are included that demonstrate how information can be passed from simulation tools operating at one level of abstraction to those operating at higher levels, while maintaining accuracy and gaining insight. Index Terms--Integrated circuits, multi-scale simulation, radiation, single-event effects, total ionizing dose.

Heavy ion cross section data taken from a hardened-by-design circuit are presented which deviate from the traditional single sensitive volume or classical rectangular parallelepiped model of single event upset. TCAD and SPICE analysis demonstrate a SEU mechanism dominated by multiple node charge collection. Monte Carlo simulation is used to model the response and predict an on-orbit error rate. Index Terms--Geant4, MRED, rate prediction, SEU.

This work draws on experimental and simulation results to derive a generalized SEU response model for bulk SiGe HBTs. The model was validated using published heavy ion and new proton data gathered from high-speed HBT digital logic integrated circuits fabricated in the IBM 5AM SiGe BiCMOS process. Calibrating to heavy ion data was sufficient to reproduce the proton data without further adjustment. The validated model is used to calculate upset event rates for low-earth and geosynchronous orbits under typical conditions. Index Terms--Deep trench isolation, Geant4, geosynchronous orbit, low-earth orbit, rate prediction, silicon-germanium HBT, single-event upset.

The RADSAFE simulation framework is described and applied to model SEU in a 0.25 [micro]m CMOS 4 Mbit SRAM. For this circuit, the RADSAFE approach produces trends similar to those expected from classical rectangular parallelepiped models, but more closely represents the physical mechanisms responsible for SEU in the SRAM circuit. Index Terms--GEANT4, heavy-ion, RADSAFE, SEU, TCAD.

Three-dimensional TCAD models are used in mixed-mode simulations to analyze the effectiveness of well contacts at mitigating parasitic PNP bipolar conduction due to a direct hit ion strike. 130 nm and 90 nm technology are simulated. Results show careful well contact design can improve mitigation. However, well contact effectiveness is seen to decrease from the 130 nm to the 90 nm simulations. Index Terms--Guard contacts, singe-event effects, technology computer-aided design (TCAD) modeling, parasitic bipolar conduction.

Simulation results for the full galactic cosmic ray environment demonstrate that current accelerator-based test methods using linear energy transfer as the engineering metric to characterize single event effects are not sufficient to capture the nuclear reaction portion of the response. Nuclear reactions contribute significantly to on-orbit single-event rates as compared to those from direct ionization induced by the primary ions. Based on these results, the applicability of current single-event test methods to predicting on-orbit event rates is examined and improved procedures are identified. For devices with critical charge values that are in the range where nuclear reactions may play a role in determining the event rate, ground-based tests should include irradiation with several types of ions of different energies to identify the contribution of these reactions to the measured SEE cross section. Index Terms--Nuclear reactions, single event effect rate, single event effects.

A novel mechanism for upset is seen in a commercially available 0.25 [micro]m 10-T SEE hardened SRAM cell. Unlike traditional multiple node charge collection in which diffusions near a single event strike collect the deposited carriers, this new mechanism involves direct drift-diffusion collection at an NFET transistor in conjunction with parasitic bipolar conduction in nearby PFET transistors. The charge collection with the parasitic bipolar conduction compromise the SEE hardened design, thus causing upsets. The mechanism was identified using laser testing and three-dimensional TCAD simulations. Index Terms--Charge sharing, parasitic bipolar, single event upset.

Simulations show that neglecting ion-ion interaction processes (both particles having Z > 1) results in an underestimation of the total on-orbit single event upset error rate by more than two orders of magnitude for certain technologies. The inclusion of ion-ion nuclear reactions leads to dramatically different SEU error rates for CMOS devices containing high Z materials compared with direct ionization by the primary ion alone. Device geometry and material composition have a dramatic effect on charge deposition in small sensitive volumes for the spectrum of ion energies found in space, compared with the limited range of energies typical of ground tests. Index Terms--Charge deposition, Geant4, heavy ion, MRED, single-event upset (SEU), SEU error rate.

Heavy ion irradiation was simulated using a Geant4 based Monte-Carlo transport code. Electronic and nuclear physics were used to generate statistical profiles of charge deposition in the sensitive volume of an SEU hardened SRAM. Simulation results show that materials external to the sensitive volume can affect the experimentally measured cross-section curve. Index Terms--Cross section, Geant4, MRED, single event upset.

Heavy-ion measurements are used to define a multiply nested sensitive-volume model for a 180-nm static random access memory (SRAM) test structure using the Monte Carlo radiative energy deposition (MRED) tool. We demonstrate that the fundamental assumptions of simple rectangular-parallelepiped (RPP) or integral-RPP models are inappropriate for single-event latchup (SEL) in this test structure, indicating that more advanced modeling is needed. We develop an MRED model that agrees well with latchup data at normal incidence and at roll and tilt angles of 60°. This process should facilitate estimates of SEL cross section and event rates for this and similar technologies in space environments. [ABSTRACT FROM AUTHOR]

Silicon-on-insulator latch designs and layouts that are robust to multiple-node charge collection are introduced. A general Monte Carlo radiative energy deposition (MRED) approach is used to identify potential single-event susceptibilities associated with different layouts prior to fabrication. MRED is also applied to bound single-event testing responses of standard and dual interlocked cell latch designs. Heavy ion single-event testing results validate new latch designs and demonstrate bounds for standard latch layouts. [ABSTRACT FROM AUTHOR]

New mechanisms of radiation sensitivity, such as low-energy proton SEU, potentially hinder the ability to define part-level failure rates and perform worst-case analysis. Ground-based radiation testing demonstrates sensitivity and is useful for understanding mechanisms, but alone is not enough to quantify error rates. If radiation-induced error rates cannot be obtained through direct integration of the part response with the space environment, validated models must be developed. Models for SEU rate predictions for memories sensitive to low-energy protons have been proposed in a number of recent publications. In this paper, we use a CubeSat platform and crowd-sourced monitoring by the worldwide amateur radio community to measure the on-orbit response of a memory useful for evaluation of these models. We find that even for memories with no discernible proton SEU threshold, classical models for proton rate prediction perform well. This illustrates the capability of small satellite missions to complement ground based tests. [ABSTRACT FROM PUBLISHER]

NPN and PNP bipolar junction transistors of varying sizes are irradiated with 4-MeV protons and 10-keV X-rays to determine the amount of ionization-related degradation caused by protons and calculate an improved estimate of displacement-related degradation due to protons. While different ratios of degradation produced by displacement damage and ionization effects will occur for different device technologies, this general approach, with suitable margin, can be used as a screen for sensitivity to neutron-induced displacement damage. Further calculations are performed to estimate the amount of degradation produced by 1-MeV equivalent neutron displacement damage compared to that produced by the displacement damage due to protons. The results are compared to previous work. [ABSTRACT FROM PUBLISHER]

MRED is a Python-language scriptable computer application that simulates radiation transport. It is the computational engine for the on-line tool CRÈME-MC. MRED is based on c++ code from Geant4 with additional Fortran components to simulate electron transport and nuclear reactions with high precision. We provide a detailed description of the structure of MRED and the implementation of the simulation of physical processes used to simulate radiation effects in electronic devices and circuits. Extensive discussion and references are provided that illustrate the validation of models used to implement specific simulations of relevant physical processes. Several applications of MRED are summarized that demonstrate its ability to predict and describe basic physical phenomena associated with irradiation of electronic circuits and devices. These include effects from single particle radiation (including both direct ionization and indirect ionization effects), dose enhancement effects, and displacement damage effects. MRED simulations have also helped to identify new single event upset mechanisms not previously observed by experiment, but since confirmed, including upsets due to muons and energetic electrons. [ABSTRACT FROM AUTHOR]

Physical mechanisms of single-event effects that result in multiple-node charge collection or charge sharing are reviewed and summarized. A historical overview of observed circuit responses is given that concentrates mainly on memory circuits. Memory devices with single-node upset mechanisms are shown to exhibit multiple cell upsets, and spatially redundant logic latches are shown to upset when charge is collected on multiple circuit nodes in the latch. Impacts on characterizing these effects in models and ground-based testing are presented. The impact of multiple-node charge collection on soft error rate prediction is also presented and shows that full circuit prediction is not yet well understood. Finally, gaps in research and potential future impacts are identified. [ABSTRACT FROM PUBLISHER]

Neutron-induced charge collection data and computer simulations presented here show that the presence of high-Z materials, like tungsten, can increase the single event upset (SEU) and multiple cell upset (MCU)cross sections of high critical charge (Qcrit) devices exposed to the terrestrial neutron environment because of interactions with high energy (> 100~\ MeV) neutrons. Time-of-flight data and computer simulations presented here demonstrate that 14 MeV neutrons do not produce highly ionizing secondary particles. Thus, 14 MeV neutrons can only simulate the SEU response of 65 nm SRAM devices in the terrestrial neutron environment for devices with a Qcrit < 27~\rm fC, and can simulate the 2-bit MCU response to within a factor of two only for very low Qcrit devices, < 1.2~fC.Additionally, it is shown that 14 MeV neutrons cannot adequately simulate the 3 or more bit MCU response for typical 65 nm SRAM devices. [ABSTRACT FROM PUBLISHER]

A new methodology of prediction for SEU is proposed based on SET modeling. The modeling of multi-node charge collection is performed using the ADDICT model for predicting single event transients and upsets in bulk transistors and SRAMs down to 65 nm. The predicted single event upset cross sections agree well with experimental data for SRAMs. [ABSTRACT FROM AUTHOR]

SEU enhancements were introduced into a radiation hardened 90 nm CMOS technology to achieve upset immunity. An incremental enhancement approach that enables various SEU/performance trade-off was demonstrated on the same basic SRAM cell to achieve various degrees of hardness, by the selective utilization of enhancement features. Single event upset testing, as well as MRED simulation, have demonstrated a significant enhancements achieved with a minimal performance penalty. [ABSTRACT FROM AUTHOR]

Heavy-ion measurements on 40-nm flip-flops indicate pattern dependence of cross-section resulting from local control logic upsets, such as clock nodes. A Monte-Carlo model of the flip-flop, calibrated to the heavy-ion data, is used to analyze the impact of multi-node charge collection within a flip-flop due to a single particle strike. Depending on the nodes that collect charge, multi-node charge collection can either increase or decrease the vulnerability of the cell. For neutrons, the overall effect of such events was found to be a net increase in cross-section by up to 16%. [ABSTRACT FROM AUTHOR]

The RADSAFE simulation framework is described and applied to model SEU in a 0.25 µm CMOS 4 Mbit SRAM. For this circuit, the RADSAFE approach produces trends similar to those expected from classical rectangular parallelepiped models, but more closely represents the physical mechanisms responsible for SEU in the SRAM circuit. [ABSTRACT FROM AUTHOR]

The charge required to store (or potentially disturb) a digital logic signal decreases as feature sizes in advanced devices decrease. As a result, the soft-error rate has become a significant reliability issue for highly scaled technologies. Single-event transients (SETs), or glitches that originate in logic circuits, are one of the most important categories of soft errors. In this letter, SETs produced by heavy ions and alpha particles are measured using a specially designed IC. The first results identifying the conditions under which an alpha particle deposits enough charge to create a SET in a bulk 90-nm CMOS technology are presented. [ABSTRACT FROM AUTHOR]

A combination of commercial simulation tools and custom applications utilizing Geant4 physics libraries is used to analyze thermal neutron induced soft error rates in a commercial bulk CMOS SRAM. Detailed descriptions of the sensitive regions based upon technology in computer-aided design calibration are used in conjunction with a physics-based Monte Carlo simulator to predict neutron soft error cross sections that are in good agreement with experimental results. [ABSTRACT FROM AUTHOR]