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The principal design concern in today's very large-scale integration (VLSI) industry is power dissipation. Power dissipation in a chip rises reliability issues. Static power dissipation places a bottleneck in scaling down the dimensions and supply voltage of metal oxide semiconductor field effect transistor (MOSFET). Short channel effects (SCEs) put a limit on MOSFET scaling. At the lower technology nodes, the control of the gate over the channel is lost in MOSFET. Fin-shaped field effect transistor (FinFETs) uses multiple gates to gain much electrostatic control over the channel. FinFET not only improves the drive current but also reduces the subthreshold leakage. This paper proposes a novel power-efficient technique for the nanoscale regime. The simulation results are derived using Mentor Graphics at a 16 nm node. The power is reduced by 91.45% and 89.01% in the proposed MOSFET and FinFET-based inverter, respectively. A chain of 5-inverters is designed as a benchmark circuit to check the performance comparisons. In the proposed MOSFET and FinFET-based benchmark circuit, there is a power delay product (PDP) reduction of 80.28%, and 99.87%, respectively. The effect of process voltage and temperature (PVT) variations for the robustness of the technique is also discussed. The proposed technique provides the power-efficient and robustness operation against the variations as compared to the other methods. [ABSTRACT FROM AUTHOR]

The emergence of high-form-factor electronics has led to a demand for high-density integration of inorganic thin-film devices and circuits with full stretchability. However, the intrinsic stiffness and brittleness of inorganic materials have impeded their utilization in free-form electronics. Here, we demonstrate highly integrated strain-insensitive stretchable metal-oxide transistors and circuitry (442 transistors/cm2) via a photolithography-based bottom-up approach, where transistors with fluidic liquid metal interconnection are embedded in large-area molecular-tailored heterogeneous elastic substrates (5 × 5 cm2). Amorphous indium-gallium-zinc-oxide transistor arrays (7 × 7), various logic gates, and ring-oscillator circuits exhibited strain-resilient properties with performance variation less than 20% when stretched up to 50% and 30% strain (10,000 cycles) for unit transistor and circuits, respectively. The transistors operate with an average mobility of 12.7 (± 1.7) cm2 V−1s−1, on/off current ratio of > 107, and the inverter, NAND, NOR circuits operate quite logically. Moreover, a ring oscillator comprising 14 cross-wired transistors validated the cascading of the multiple stages and device uniformity, indicating an oscillation frequency of ~70 kHz. Developing integrated stretchable metal-oxide transistors and circuits is challenging. Here, Kang et al. leveraged molecular-tailored elastic substrates for enhanced adhesion, thus achieving high performance and logical operation across various circuits under high strain. [ABSTRACT FROM AUTHOR]

This paper presents a new process, voltage and temperature (PVT) tolerant 7-stage ring type current starved voltage-controlled oscillator (CS-VCO). In this, a 7-stage ring VCO is proposed using power gated technique for phase locked loop (PLL) application. PLL plays a major role in clock and data recovery, Global Positioning System (GPS) system and satellite communications. For the high-speed application of PLL it is designed using 7-stage inverter delay cell with MOS current mode logic (MCML) technique. The circuit undergoes process, voltage and temperature variations with different parameters such as average power, oscillation frequency, phase noise, tuning range and output noise. The Monte-Carlo analysis justifies the proposed design provides better results. The circuit is simulated under 45 nm CMOS technology using cadence virtuoso. The average power consumption of the proposed circuit is 29.368 µW with the oscillation frequency of 3.06 GHz. The output noise and the phase noise of the proposed VCO are -161.55 dB and -125.92 dBc/Hz respectively. It achieves the frequency tuning range (FTR) of 95.09 %. The obtained simulation results are highly robust with PVT making the circuit suitable for PLL application. [ABSTRACT FROM AUTHOR]

In this work, a novel enhancement-mode GaN p-MISFET with a buried back gate (BBG) is proposed to improve the gate-to-channel modulation capability of a high drain current. By using the p-GaN/AlN/AlGaN/AlN double heterostructure, the buried 2DEG channel is tailored and connected to the top metal gate, which acts as a local back gate. Benefiting from the dual-gate structure (i.e., top metal gate and 2DEG BBG), the drain current of the p-MISFET is significantly improved from −2.1 (in the conv. device) to −9.1 mA/mm (in the BBG device). Moreover, the dual-gate design also bodes well for the gate to p-channel control; the subthreshold slope (SS) is substantially reduced from 148 to ~60 mV/dec, and such a low SS can be sustained for more than 3 decades. The back gate effect and the inherent hole compensation mechanism of the dual-gate structure are thoroughly studied by TCAD simulation, revealing their profound impact on enhancing the subthreshold and on-state characteristics in the BBG p-MISFET. Furthermore, the decent device performance of the proposed BBG p-MISFET is projected to the complementary logic inverters by mixed-mode simulation, showcasing excellent voltage transfer characteristics (VTCs) and dynamic switching behavior. The proposed BBG p-MISFET is promising for developing GaN-on-Si monolithically integrated complementary logic and power devices for high efficiency and compact GaN power IC. [ABSTRACT FROM AUTHOR]

Background and Objectives: The H-bridge (HB) driver design with high efficiency is one of the most challenging issues in power systems that drive AC/DC loads. HB driver circuit based upon complementary MOSFET type used as a driving system of DC motor, power converters, and battery charger for electrical vehicles. In Driving DC motors, dead-time (DT) generation has been considered a major factor such as preventive power line short-circuits (shoot-through) over high and low-side MOSFETs. In this paper, the HB driver is designed for linear actuators with consideration for the prevention of shoot-through. Methods: The propagation delay of logic gates are used to postpone the arrival gate drive signal for high/low side MOSFETs resulting in short circuit elimination on the DC source. Results: As mentioned, logic gates' propagation delay by their values causes interruption between the high and low-side power switches gate drive signal resulting in shoot-through elimination. Although the existence of DT influences the performance of the rotational speed and output torque of a DC motor by increasing the distortion and pulse interval, Linear actuators due to low-velocity linear motion do not require the PWM control, therefore DT has no substantial effect on driver performance. Conclusion: Simulation and experimental results validate the method proposed in this paper. According to the specifications of the circuit designed in this paper, for loads that do not need rotational speed control, logic gates with proper propagation delay can be chosen to eliminate short circuits in complementary MOS switches without requiring DT compensation methods. [ABSTRACT FROM AUTHOR]

For digital applications, researchers are exploring the use of Tunnel Field-Effect Transistors (TFETs) as an alternative to Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). TFETs offer unique qualities that can be harnessed in digital applications. The presented work focuses on the Drain Engineering Dual Metal Gate based Charge Plasma TFET (DE-DMG-CP-TFET) and its ability to implement various logic functions utilizing 2D device simulations. This simulation refers to employing computational tools to analyze electronic devices in two spatial dimensions, considering parameters such as current-voltage characteristics, electric field analysis, and energy band diagrams. This simulation-based approach enables a comprehensive understanding of the device's operation under different conditions and facilitates the optimization of its performance. The simulations provide insights into the impact of design parameters, material properties, and device configurations on its functionality. By leveraging the ambipolar nature and gate-controlled tunneling capability of TFETs, compact logic functions can be realized by carefully designing the gate-source overlap and selecting an appropriate silicon body thickness. This research highlights the potential of TFETs in compact logic implementation and demonstrates the value of two-dimensional device simulations in understanding device behavior and optimizing performance. It is demonstrated that by biasing the two gates individually, a single DE-DMG-CP-TFET may implement logic operations like OR, AND, NAND and NOR. Using a gate-source overlap (LOV) and picking the right silicon body thickness are crucial for obtaining distinct logic functions from a DE-DMG-CP-TFET. For digital applications, researchers are looking into Tunnel Field-Effect Transistors (TFETs) as possible substitute for MOSFETs. Utilizing two-dimensional device simulations, a Drain Engineering Dual Metal Gate-based Charge Plasma TFET (DE-DMG-CP-TFET) is presented to implement various logic functions. It is demonstrated that by biasing the two gates individually, a single DE-DMG-CP-TFET may implement logic gates operation. Using a gate-source overlap and picking the right silicon body thickness are crucial for obtaining distinct logic functions from a DE-DMG-CP-TFET [ABSTRACT FROM AUTHOR]

A new type of heterojunction non-volatile memory transistor (H-MTR) has been developed, in which the negative transconductance (NTC) characteristics can be controlled systematically by a drain-aligned floating gate. In the H-MTR, a reliable transition between N-shaped transfer curves with distinct NTC and monolithically current-increasing transfer curves without apparent NTC can be accomplished through programming operation. Based on the H-MTR, a binary/ternary reconfigurable logic inverter (R-inverter) has been successfully implemented, which showed an unprecedentedly high static noise margin of 85% for binary logic operation and 59% for ternary logic operation, as well as long-term stability and outstanding cycle endurance. Furthermore, a ternary/binary dynamic logic conversion-in-memory has been demonstrated using a serially-connected R-inverter chain. The ternary/binary dynamic logic conversion-in-memory could generate three different output logic sequences for the same input signal in three logic levels, which is a new logic computing method that has never been presented before. Reconfigurable logic is desirable for high-density information processing. Here, the authors demonstrate a binary/ternary logic conversion-in-memory, which can operate in both binary and ternary logic systems to implement various types of logic gates. [ABSTRACT FROM AUTHOR]

In this work, we study experimentally the impact of different gate dielectric stacks on the subthreshold behavior of cryogenic MOSFETs. While in room temperature devices, silicon nitride deteriorates the off-state of MOSFETs it turns out that at cryogenic temperatures an appropriately thin, grown silicon nitride layer in combination with a high-k gate dielectric counteracts the saturation of the inverse subthreshold slope and inflection phenomena. As a result, steep slope cryogenic MOSFETs with strongly improved subthreshold behavior are demonstrated. [ABSTRACT FROM AUTHOR]

In this paper, a novel superjunction MOSFET with ohm contact in the termination region and dual Schottky contacts in the cell region is proposed and experimentally demonstrated. The dual Schottky contacts consisting of the N-type Schottky contact and the P-type Schottky contact suppress the hole injection in the cell region, thereby reducing the reverse recovery charge and enhancing the current density in the termination region. The high current density and the ohm contact in the termination region provide sufficient slowly extracted non-equilibrium holes during the reverse reduction period, which contributes to a significantly improved softness. Experimental results show that, in comparison with the conventional superjunction MOSFET, 66.2% reduction in reverse recovery charge and 137.5% improvement in softness factor can be obtained in the proposed superjunction MOSFET. [ABSTRACT FROM AUTHOR]

Conventional digital LLC synchronous rectifier (SR) control typically uses detection circuits to sense the drain-source voltage of SR MOSFET in low output voltage applications, or gives SR duty cycle only considering the switching frequency in the microcontroller. They are difficult to be applied to the applications of 700-V high voltage and 6.6-kW high power directly due to the high dv/dt and large SR duty cycle variations, which poses serious challenge for SRs control. A bidirectional impedance-based SR driving scheme is presented for high-voltage SiC LLC converter. Based on the LLC equivalent impedance, mathematical models are built to calculate the SR on-time in the forward and reverse modes, which can be tuned timely when the switching frequency and load vary. Thus, both bidirectional LLC performance with high efficiency and high immunity to the switching noise can be achieved without adding auxiliary circuits. A prototype of 300-kHz 6.6-kW SiC bidirectional LLC charger was built. Compared to the conventional SR method, the LLC efficiencies improve 0.3% in the forward and reverse modes at full load by using the proposed SR driving scheme. [ABSTRACT FROM AUTHOR]

The single gate driven series connected power device stack possesses the advantages of high compactness and low cost. However, research of its short circuit (SC) characteristic remains uncovered. This article fills this gap and points out that, with the single gate driver it has the potential of over-current limitation. Furthermore, based on it, an improved single gate driven silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (mosfet) stack with strong antishort circuit fault capabilities is proposed. By adding auxiliary circuits to adjust the driving process of the single gate driver, the SiC mosfet stack can be automatically turned off in both SC conditions of fault under load and hard switch fault, while the normal working principle of the stack is not influenced. Neither active control nor overcurrent detection is required, which is the biggest merit of the proposed topology. Its design and analysis are presented in detail, followed by the validation by conducting simulations and experiments. [ABSTRACT FROM AUTHOR]

A novel methodology for total ionizing dose (TID) hardening of Silicon-on-insulator (SOI) MOSFET is demonstrated by employing a superior type of void embedded SOI (VESOI) substrate. With the successful removal of most of the radiation sensitive area in buried oxide, the TID tolerance of VESOI MOSFET is significantly enhanced in comparison to its conventional SOI counterpart. In particular, the shift of threshold voltage (${V}_{\text {th}}$) and subthreshold swing is only −38.9mV and 11.6mV/dec at radiation doses up to 2Mrad(Si). Further device simulation shows that the radiation immunity can withstand misalignment between the gate and embedded void in a wide range. Our VESOI substrates, offering both high compatibility with planar CMOS process and versatile void embedded device design, exhibit great potential in the development of anti-radiation SOI devices. [ABSTRACT FROM AUTHOR]

Remotely driven smart actuator technology by microwave is attractive since it simplifies and reduces the complexity and weight of the remote system. A rectifying antenna (rectenna) array receives and converts microwave power into DC power for actuators, and the power collected from the rectenna array should be accurately allocated and distributed to each actuator. In this research, a new power distribution (PD) logic circuit is studied to control an actuator array effectively. The PD logic circuit was designed and tested to validate it. The preliminary design was tested for a 4 × 4 piezoelectric actuator array with a 16 dual-gate MOSFET array and a computer-controlled 16-channel DAC board. Additionally, power compensation as a remedial approach for a partial power failure of the array was integrated. This PD scheme with a new logic device simplifies the thousands of control cables required for connecting each array element. The performance and limitations of the designed PD circuit are discussed. [ABSTRACT FROM AUTHOR]

The shape of the channel cross section in rectangular nanowire (NW) gate-all-around (GAA) MOSFETs turns trapezoidal due to process variations. In this article, the impact of process-induced inclination of sidewalls on gate-induced drain leakage (GIDL) current in the trapezoidal channel NW GAA MOSFETs has been systematically investigated using experimental and calibrated TCAD simulation results. The GIDL current has also been analyzed against the variation in other device parameters, such as channel length, height, and width. The lateral band-to-band tunneling (L-BTBT) mechanism at the channel/drain junction has been considered in simulations to obtain the GIDL current. The investigation reveals that the GIDL current increases up to two times if the process-induced sidewalls inclination angle increases from 0° to 20°. [ABSTRACT FROM AUTHOR]

Shallow trench isolation drain extended MOS (STI-DeMOS) devices, known for their superior gate oxide reliability under high drain voltages, are widely used for the integration of CMOS-compatible high-voltage devices. However, they offer moderate high-frequency performance that limits the use of these devices even in mid-band 5G applications. A novel island drain and a double-gate drain-extended MOS (IDDG DeMOS) device with improved high-frequency performance is proposed in this work. The proposed device has a core MOSFET and an STI-DeMOS with a self-aligned pocket well, both feature a shorter channel length than a typical STI-DeMOS device. The shorter gate length enhances the proposed device’s RF performance without degrading the breakdown voltage. We have performed simulations using a well-calibrated deck in the Sentaurus TCAD environment. We have shown an increase in the transit frequency from 25 GHz in STI-DeNMOS to 53 GHz in the proposed IDDG DeNMOS device, and from 11 to 31 GHz for a p-type device at a 65-nm technology node. This work also presents the well edge variation immunity of the proposed device. All these features are achieved in the mainstream SoC-compatible CMOS process flow without any additional fabrication mask or process complexity. [ABSTRACT FROM AUTHOR]

Achieving a self-aligned structure has been an essential key to the development of silicon-based MOSFET technology over the past several decades. However, it is usually challenging to achieve such self-alignment in layered material-based devices due to the lack of conventional doping processes such as ion implantation. In this work, we demonstrate an electrically defined self-aligned test structure using two partially overlapping top gates and a bottom gate in a WSe2/SnSe2 van der Waals (vdW) heterojunction. The test structure allows us to discern the properties of the heterojunction without any confounding series resistance effect arising from the WSe2/metal contact junction. By controlling the individual gates in the test structure, we reconfigurably achieve both p-type TFET operation with a minimum subthreshold slope < 60 mV/decade and n-type MOSFET operation. The structure will be useful to test self-aligned device operations in layered materials without the confounding effect of gate-dependent large contact resistance. [ABSTRACT FROM AUTHOR]

Several important aspects related to the phenomena of ac gate-bias stress-induced threshold-voltage degradation in SiC MOSFETs are presented. These include a detailed investigation of the particular sensitivity of trench-geometry devices when exposed to a negative gate-bias overstress, the specific conditions that drive this degradation, and its recovery by the application of a dc negative bias temperature stress. [ABSTRACT FROM AUTHOR]

In this work, the intentional insertion of slots in metal gate (MG) is introduced to solve the dishing issue for the double-diffused drain MOSFET (DDDMOSFET) fabrication. For traditional DDDMOSFET, the gate oxide layer in slots will be reserved to improve the device reliability, which requires an additional photomask to screen the gate/slot regions during the following sidewall formation and source/drain (S/D) implantation. This makes the process more complicated with increased cost. Without that additional photomask, it is proposed that the removal of gate oxide layer in slots can directly allow the floating S/D formation and the followed Ni silicidation there. It is demonstrated that such a novel process can not only relieve the MG dishing issue but can also effectively result in ~16% higher ON current and comparable OFF current for both N- and P-DDDMOSFETs without threshold voltage shift after applying electrical stress on gates. It is also revealed that the floating silicided S/Ds in slots have negligible influence on device breakdown characteristics. By saving one photomask, this work proposes a novel solution for the effective integration of core devices with very small feature sizes and high-voltage (HV) devices with large feature sizes in the same die, which is a common challenge for display driver chip fabrication using high- ${k}$ /MG (HK/MG) technology. [ABSTRACT FROM AUTHOR]

Wide-bandgap (WBG) power devices have better dynamic characteristics and higher working temperatures compared to traditional Si devices and are more suitable for high-frequency and high-voltage applications because of fast turn-on and turn-off speeds. The main obstacle for the use of WBG devices is the high-frequency oscillation (HF-Osc) in voltage and current during the switching process. In this article, a new method of predicting the SiC mosfet switching behavior (including HF-Osc and slow switching) is proposed. First, the models of nonlinear capacitances are improved and parasitic elements are taken into account for improving the RLC equivalent circuit of the mosfet switching transient. On this basis, the LC equivalent frequency is obtained. Then, a new method is proposed to obtain the SiC mosfet instantaneous frequency. The comparison between them in the time domain makes it possible to analyze the SiC mosfet switching behavior. The prediction method is verified using a CREE SiC mosfet via a double pulse test. Experimental and simulation results show that the prediction method is effective in describing the HF-Osc characteristics. The proposed method can be used to effectively improve the mosfet HF-Osc, which provides guidance for the application of SiC mosfets. [ABSTRACT FROM AUTHOR]

This paper proposes a novel method to adaptively select the best driver to load transistor fin ratio of CMOS FinFET logic inverter according to the best values of noise margins and inflection voltage with a comparison of the use of different and combined Si and Ge as a load and/or driver semiconductor channel in CMOS FinFET inverter logic circuit. The methodology of optimizing the driver to load transistor fin ratio depends strongly on improving the noise margins and inflection voltage of the output characteristics of CMOS logic inverter. The first step in this investigation of CMOS-FinFET-inverter is to obtain the output characteristics (Id-Vd) of the FinFET, and then use the MATLAB simulation model to create CMOS Fin- FET transfer characteristics. Transfer characteristics of CMOS-FinFET-logic inverter are studied with fin ratios Np/Nn of 5/1, 4/1, 3/1,2/1, 1/1, 1/2, 1/3, 1/4, 1/5. Noise margins and inflection voltage are used as critical factors to obtain the optimal fin ratio (Np/Nn). The results indicate that optimization depends strongly on the fin ratio for all combined semiconductor loads to FinFET driver inverters. The results show that the best ratios for Si:Si, Si:Ge, Ge:Si, and G:Ge are 2:1, 1:4, 2:1, and 1:3 respectively. [ABSTRACT FROM AUTHOR]

Narrow-channel accumulated body nMOSFET devices with p-type side gates surrounding the active area have been electrically characterized between 100 and 400 K with varied side-gate biasing (${V}_{\text {side}}$). The subthreshold slope (SS) and drain induced barrier lowering (DIBL) decrease and threshold voltage (${V}_{t}$) increases linearly with reduced temperature and reduced side-gate bias. Detailed analysis on a 27 nm $\times $ 78 nm (width $\times $ length) device shows SS decreasing from 115 mV/dec at 400 K to 90 mV/dec at 300 K and down to 36 mV/dec at 100 K, DIBL decreasing by approximately 10 mV/V for each 100 K reduction in operating temperature, and ${V}_{t}$ increasing from 0.42 to 0.61 V as the temperature is reduced from 400 to 100 K. ${V}_{t}$ can be adjusted from ~0.3 to ~1.1 V with ~0.3 V/V sensitivity by depletion or accumulation of the body of the device using ${V}_{\text {side}}$. This high level of tunability allows electronic control of ${V}_{t}$ and drive current for variable temperature operation in a wide temperature range with extremely low leakage currents (<10−13 A). [ABSTRACT FROM AUTHOR]

Power consumption and especially leakage power are the main concerns of nano MOSFET technology. On the other hand, binary circuits face a huge number of interconnection wires, which results in power dissipation and area. Researchers introduced emerging nanodevices and multiple-valued logic (MVL) as two feasible solutions to overcome the challenges mentioned above. Carbon nanotube field-effect transistor (CNFET) is one of the emerging technologies that has some unique properties and advantages over MOSFET, such as adjusting the carbon nanotube (CNT) diameters to have the desired threshold voltage and have the same mobility as P-FET and N-FET transistors. In this paper, we present a novel method for designing ternary logic circuits based on CNFETs. Each of our designed logic circuits implements a logic function and its complementary via a control signal. Also, these circuits have a high impedance state, which saves power while the circuits are not in use. Moreover, we designed a two-digit adder/ subtractor and a power-efficient ternary logic arithmetic logic unit (ALU) based on the proposed gates. The proposed ternary circuits are simulated using HSPICE via standard 32 nm CNFET technology. The simulation results indicate the designs' correct operation under different process, voltage, and temperature (PVT) variations. Also, simulation results show that the two-digit adder/ subtractor using our proposed gates has 12X and 5X lower power consumption and power-delay product (PDP), respectively, compared to previous designs. [ABSTRACT FROM AUTHOR]

This article presents quick analytical prediction methods of switching loss, turn-on/off overvoltage, di/dt, and dv/dt for SiC metal–oxide–semiconductor field-effect transistor based on device datasheet. First, the switching process is analyzed and the simplification principles are discussed based on charge conservation and flux conservation. Second, the analytical equations of switching loss, turn-on/off overvoltage, di/dt, and dv/dt are derived. Third, experimental results under different operating conditions are presented to validate the proposed methods. It is found that the average prediction error is 10.11%. Finally, relationships between switching performance and different parameters, such as parasitic capacitance, parasitic inductance, dc-voltage, and load current, are analyzed and summarized based on the proposed prediction methods. [ABSTRACT FROM AUTHOR]

A unified model for multigate negative capacitance transistors with self-heating effects (SHEs) is developed. With a metal–ferroelectric–insulator–semiconductor (MFIS) structure, thermal effects result in different temperature rises in the channel and ferroelectric layer. A gate control equation for the double-gate and gate-all-around MFIS structures is developed, on top of which both the current–voltage and charge–voltage characteristics are covered. The formulations describe dependences of ferroelectric layer thickness, with backward compatibility for MOSFETs. A unified thermal network is then proposed for SHE, capturing the essential physics of couplings between ferroelectric temperature and conduction current. The model has been verified with TCAD simulations and implemented for circuit simulations. [ABSTRACT FROM AUTHOR]

The threshold voltage (${V}_{\text {th}}$) instability induced by gate stress has always been a significant reliability issue for silicon carbide (SiC) MOSFET. The negative bias temperature instability (NBTI) of 4H-SiC p-channel MOSFET (pMOS) was studied experimentally at 200 °C and compared with that of 4H-SiC n-channel MOSFET (nMOS). It is shown that the ${V}_{\text {th}}$ drift of pMOS after 20 ks of negative stress −18 or −30 V is around twice that of nMOS. The behavior of the interface traps after stress is also analyzed quantitatively. It is concluded that the hole oxide traps are the dominant mechanism resulting in this large ${V}_{\text {th}}$ drift difference between pMOS and nMOS, and the interface traps have little contribution to the threshold voltage drift in this study. Moreover, in a double logarithmic plot, the ${V}_{\text {th}}$ recovery curves at a gate voltage of 0 V indicate that nMOS has a faster recovery than pMOS at the initial time. And the slope of ${V}_{\text {th}}$ recovery curve for pMOS becomes larger after 100 s. [ABSTRACT FROM AUTHOR]

Gate-oxide degradation has been one of the critical reliability concerns of silicon carbide (SiC) metal–oxide–semiconductor-field-effect transistors (mosfets), which could be monitored through aging-sensitive parameters. In this article, an online gate-oxide degradation monitoring method for planar SiC mosfets is proposed by extracting gate charge time at a specific range of gate voltage. It is based on the findings that the input capacitances of planar SiC mosfets change significantly over gate-oxide degradation, which is theoretically analyzed and experimentally verified. The capacitance variations are converted into the gate charge time as the new aging-sensitive parameter. The new parameter measurement circuit is proposed and integrated into the gate driver module. The article results indicate that the new parameter varies noticeably with gate-oxide degradation and the difference of this parameter caused by junction temperature is much smaller than that caused by degradation. Besides, the parameter is immune to package degradation and load current. The condition monitoring method can be implemented online since the parameter is extracted during the off-state of SiC mosfet devices, which does not affect normal operation. The confirmatory experiment is carried out to verify the correctness of the proposed method. [ABSTRACT FROM AUTHOR]

For silicon carbide power mosfets, high dv/dt in switching may bring about a high level of electromagnetic interference. This letter shows that the dv/dt rate decreases at lower load currents. A dynamic dv/dt control strategy is then proposed for switching loss reduction in the whole operating range, by maintaining the dv/dt at the maximum acceptable level. The effectiveness of the proposed control strategy is verified by an experiment, showing that the total switching loss can be reduced by as much as 22% at 30% load. Furthermore, the simulation shows that a power loss reduction of 11.4% can be obtained for an electric vehicle converter which typically operates at light loads for most of the time. [ABSTRACT FROM AUTHOR]

This article introduces the negative feedback into the gate drive. It proposes a negative feedback active gate drive (NFAGD) for silicon carbide devices to fully utilize their potential of high switching-speed capability in a phase-leg configuration. An auxiliary P-channel mosfet is introduced to construct a negative feedback control mechanism. Due to the negative feedback mechanism, the proposed drive can automatically attenuate the disturbance from the complementary device of the phase-leg. Compared to conventional gate drives, the proposed drive can suppress the crosstalk without influencing the switching speed, thus enables coordinated optimization of gate voltage stability and switching behavior. This article analyzes the operation principle and then recommend the fundamental design principle for the proposed NFAGD. Finally, experiment results demonstrate the effectiveness of the proposed NFAGD. [ABSTRACT FROM AUTHOR]

Metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short‐channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large‐scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor‐level input‐controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low‐power ICS approach is extensively discussed to verify its importance in low‐power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low‐power and high‐speed techniques at a 22‐nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5‐inverters. [ABSTRACT FROM AUTHOR]

This research article proposes a floating memristor emulator configuration based on n-type MOSFETs only. The proposed memristor comprises three nMOS and an extra nMOS for an external grounded capacitor. Compared to the existing literature, the proposed floating MOS memristor enables a simple design without any sophisticated design complexity. The actual fingerprint of the memristor as a pinched hysteresis loop with different frequency domains and composite characteristics as incremental and decremental are well examined using computer simulation with 90-nm CMOS technology parameters for MOSFETs. The power consumed by the proposed circuit is $2.6~\mu \text{W}$. In addition, an experimental test using off-the-shelf components is investigated to verify the theoretical and simulated results. Moreover, the proposed nMOS-memristor emulator application is suitable for the modulation and demodulation of binary frequency-shift keying (BFSK) and Boolean logic gates. [ABSTRACT FROM AUTHOR]

In this work, a new type of graphene ICs only comprising multiple graphene field-effect transistor (GFET) components is first reported. Based on the GFET design that enables homogeneous electrical characteristics in batch-made devices, the practicality and functionality significances of multi-GFET integration are experimentally demonstrated via high-fidelity amplifiers for baseband analog signals. Different from the quadratic relationship of the gate-controlled current output (in saturation region) in the traditional silicon-based MOSFETs, the saturation current output of GFETs relating to the gate-controls possesses high linearity. This advantage overcomes the inherent nonlinear distortion issues in the existing silicon MOSFET amplifiers and potentially provides a promising scenario for the accurate preamplification of weak analog signals. Besides, the novel circuit configuration and signaling principle may expand the developmental paradigm of analog amplifiers and set groundwork for the development and practicalization of advanced carbon-based nanoelectronic ICs. [ABSTRACT FROM AUTHOR]

The reliability of SiC MOSFETs under harsh operating conditions, such as short circuit (SC) stress, remains a major concern. In this article, a dedicated aging platform is developed to study the degradation of SiC planar- and trench-gate MOSFETs under repetitive SC conditions. The static characteristics of the devices are monitored in real-time during the test. Depending on the gate bias used in the experiments, a bidirectional ${V}_{\text {TH}}$ shift in both types of devices is observed, yet with a different degradation rate. The underlying degradation mechanisms investigated by device simulation reveal that the damaged region in the SiC planar-gate MOSFET is located near the channel area, while at the trench corner in the SiC trench-gate MOSFET. These research outcomes enable better understanding of the degradation mechanisms of different SiC MOSFET structures and possible ruggedness improvements in the future. [ABSTRACT FROM AUTHOR]

[Display omitted] • Strain modulation mechanism on two-dimensional Te transistor was investigated. • Tensile/compressive strains to Te were relaxed by interfacial/stacked layer. • Synergistic effects of strain and crystallinity engineering were proposed. • Te transistor showed enhanced property with a high mobility of 12.05 cm2/V·s. • Te transistor exhibited excellent stability under long-term and PBS/NBS tests. Two-dimensional p-type material, tellurium (Te), has been of particular interest owing to its extraordinary electronic, optoelectronic, and thermoelectric properties. Here, we report a promising strategy to demonstrate enhanced performance Te transistor via strain modulation effect. The compressive and tensile strains were induced to the room-temperature-sputtered Te channel layer by stacking with various metal interfacial layers, followed by the strain relaxation and deoxidization effects caused by the deposition of the aluminum oxide via atomic layer deposition process. The strain engineering mechanism was comprehensively investigated by various characterizations, and both strain modulation and deoxidization-assisted crystallinity improvement were shown to synergistically enhance the charge transport of Te transistor. As a result, the improvement in the device performance with uniformity was clearly achieved, demonstrating the carrier mobility of 12.05 cm2/V·s, the threshold voltage of 0.09 V, and the subthreshold swing of 4.34 V/decade. This further results in the stable long-term operation over 28 days and excellent electrical stability under harsh negative and positive biasing conditions. Thus, this study presents a novel strategy of strain modulation for improving the performance of Te transistor, which has great potentials for complementary-metal–oxide–semiconductor logic circuits. [ABSTRACT FROM AUTHOR]

While the theoretical maximum of the memory window $\Delta {V}_{t}$ in a ferroelectric field-effect transistor (FEFET) is $2{E}_{C}{t}_{F}$ , ${E}_{C}$ and ${t}_{F}$ being coercive field and FE thickness, respectively, experimentally $\Delta {V}_{t}$ is observed to be much less than that, even in the case of complete polarization switching in the ferroelectric layer. This occurs because trapped charges in the gate oxide stack partially or completely screen the ferroelectric polarization, only a fraction of which gets “electrostatically” reflected in the semiconductor channel. In this article, we provide a generalized experimental framework to quantify the efficiency of practical FEFETs in converting the switched ferroelectric polarization into the memory window. To that end, we propose three efficiency metrics: 1) switched ferroelectric polarization $\Delta {P}_{F}$ to memory window conversion ratio, $\eta _{MW}=\Delta {V}_{t}/\Delta {P}_{F}$ ; 2) switched ferroelectric polarization to the semiconductor charge ($\Delta {Q}_{S}$) conversion efficiency or the charge conversion efficiency $\eta _{c}=\Delta {Q}_{s}/\Delta {P}_{F}$ ; and 3) the ratio of memory window to the width of polarization versus gate voltage hysteresis characteristics ($\Delta {V}_{P}$) or the voltage conversation efficiency $\eta _{V}=\Delta {V}_{t}/\Delta {V}_{P}$. We measure and compare these efficiency metrics in n-type and p-type FEFETs, fabricated in different facilities by different groups. In all the cases, we find that the maximum values of memory window efficiency $(\eta _{MW})_{max}$ , charge conversion efficiency $(\eta _{c}$) $_{max}$ , and voltage conversion efficiency ($\eta _{V}$) $_{max}$ are in the range: 2.5–5.5 Vm2/C, 4%–10%, and 5%–20%, respectively. [ABSTRACT FROM AUTHOR]

A contact resistance (${R}_{c}$) becomes a major parasitic resistance in highly scaled modern semiconductor devices. A wrap-around contact (WAC) has been suggested as a promising solution to reduce the ${R}_{c}$ , because its contact area is larger than that for the conventional top contact (TC) structure. Therefore, in this article, the electrical and thermal characteristics are widely investigated in vertically stacked gate-all-around (GAA) MOSFET with a WAC by using a 3-D technology computer-aided design (TCAD) simulation. First, compared with the TC, the WAC shows 1.74 times higher ON-state current. It is attributed in part to the low ${R}_{c}$ and in part to the low source–drain resistance (${R}_{\text {SD}}$). Furthermore, thermal resistance (${R}_{\text {th}}$) is also reduced by 9.73% in WAC, which improves self-heating effects (SHEs). Considering the results, it is expected that the WAC structure could be an attractive candidate to simultaneously improve device performance and reliability. [ABSTRACT FROM AUTHOR]

The effects of total ionizing dose (TID) on MOSFETs fabricated in a 22-nm fully depleted silicon-on-insulator (FD-SOI) technology are analyzed. TID causes positive-trapped charge to accumulate in transistor isolation regions [e.g., the buried oxide (BOX)], thereby generating negative TID-induced threshold-voltage shifts $\Delta V_{\mathrm {th}}$ that facilitate nMOSFET turn-on and inhibit pMOSFET turn-on. Back-gate biasing options in the technology can be used to offset the threshold-voltage shifts. Applying a bias to the back gates of MOSFETs in a conventional-well back-gate configuration mitigates TID-induced $\Delta V_{\mathrm {th}}$ in nMOSFETs (where a negative bias is applied to the P-well back-gate), while enhancing the same in pMOSFETs (where a positive bias is applied to the N-well back-gate). To mitigate and potentially reverse TID-induced $\Delta V_{\mathrm {th}}$ of both nMOSFETs and pMOSFETs simultaneously, a single back-gate bias can be applied to MOSFETs in a common isolated P-well back-gate configuration. 3-D technology computer-aided design (3-D TCAD) device simulation results of the 22-nm FD-SOI technology confirm the conventional-well circuit-level radiation response and support the effectiveness of using the common isolated P-well back-gate configuration for TID mitigation. These results justify the utility of dynamically tuning back-gate bias according to actively monitored TID-induced $\Delta V_{\mathrm {th}}$ feedback. [ABSTRACT FROM AUTHOR]

Parallel devices in nonuniform conditions can easily lead to reduced overall reliability or even failure due to uneven energy distribution. Especially under long-term avalanche stresses, the degradation of the device may have a great impact on the electrical parameters and performance. To study the degradation tendency and aging mechanism of parallel-connected silicon carbide (SiC) MOSFET, the repetitive unclamped inductive switching (UIS) experiments are carried out in this article. Technology computer-aided design (TCAD) simulations are utilized to simulate the temperature change and current distribution of the chip during an avalanche. The results showed that for planar and trench devices, the electrical parameters drifts are different during repetitive avalanches. The degradation rates are unequal for parallel devices with different case temperatures. Two degradation mechanisms, including hot holes injection and trapping in the gate oxide and metal aging, are found to dominate in the repetitive avalanche process. The findings are helpful for better understanding of degradations for parallel repetitive avalanches in device applications. [ABSTRACT FROM AUTHOR]

Thermal impedance is required to describe static and fast dynamic thermal behavior in silicon-on-insulator (SOI) devices. This study presents an empirical physical model, which accounts for gate length, for calculating the thermal impedance of multi-finger partially depleted (PD) SOI MOSFETs at room temperature. For the first time, the parameters of the model are obtained from measurements of ac conductance and the characteristic thermal frequency determination. The model shows decreasing thermal resistance and linearly augmented thermal capacitance with increasing gate length from 0.18 to 2.50 $\mu \text{m}$. Thus, thermal time constants of ~760 ns, extracted from a variety of gate lengths, are correctly predicted. [ABSTRACT FROM AUTHOR]

With increasing applications of silicon carbide power MOSFETs, more attention is being paid to reliability issues, among which the long-term stability of the gate threshold voltage is of paramount importance. In this article, laboratory experiments are conducted to investigate the threshold voltage instability under ac gate stresses with different duty ratios, and on and off-state gate voltages. It is found that no prominent drift would occur even for bipolar gate stresses, as long as the off-state gate voltage is within (higher than) the critical negative bias voltage which is related to the device fabrication process. Furthermore, not only the gate voltage swing but also the gate voltage polarity will affect the speed of threshold voltage drift when it occurs. The findings are intended for better understanding and management of potential threshold voltage drift in device applications. [ABSTRACT FROM AUTHOR]

This article introduces a 4 kV/120 A solid-state dc circuit breaker (DCCB) based on discrete SiC mosfets. The DCCB is designed in a five-layer tower structure. Each layer consists of a circular main conduction branch and an attached gate driver. There are two primary benefits of the proposed DCCB. First, it reduces conduction loss with multiple devices in parallel. Second, it achieves an ultrafast response speed with SiC mosfets. Moreover, the gate drivers of the DCCB are powered by a domino inductive power transfer (IPT) system. It achieves the load-independent constant-voltage output characteristics, which means the outputs are immune to load variations. An IPT system prototype is implemented to test the power transfer performance. At 500-kHz frequency, the total output power reaches 15.73 W, which is sufficient to power on five gate drivers, with a peak transfer efficiency of 75.4%. The IPT system is tested to power a 4 kV/120 A DCCB prototype. It validates that the DCCB is effective to turn off 120 A current within 3.5 μs. [ABSTRACT FROM AUTHOR]

In this letter, we comprehensively investigate the electrical properties of the 1200 V planner-gate 4H-SiC power metal–oxide–semiconductor field-effect transistors under the mechanical strains. Three kinds of strains, including the biaxial strain, uniaxial strain parallel to the gate channel, and uniaxial strain perpendicular to the gate channel, are applied using the wafer bending system. It is found that all kinds of compressive strains improve the drain current (Id) under the same gate voltage (Vg) and shift the threshold voltage (Vth) negatively, while the tensile strains decrease Id and shift Vth positively. The Vth shift mainly results from the strain modulated band structure in the poly-Si gate. Under the same overdrive gate voltage (Vov), biaxial strains merely change Id, while both the parallel and perpendicular uniaxial compressive strains enhance Id. The uniaxial compressive strain elevates the electron mobility in the inverted channel by repopulating more electrons into the valleys with a smaller conduction effective mass, which results in the current improvement. [ABSTRACT FROM AUTHOR]

We demonstrate a HfZrO2 (HZO) ferroelectric field-effect transistor fabricated on a silicon-on-insulator substrate, targeting MHz synaptic device applications. Stable multistate weights were implemented with robust retention, excellent linearity, and symmetric potentiation/depression (P/D) in the fabricated HZO ferroelectric field-effect transistors (FeFETs). To further improve the linearity and symmetry of the P/D and to expand the operating condition of the FeFETs as a synaptic device, a novel incremental drain-voltage-ramping method was proposed, and its compatibility was verified thoroughly. The results revealed that a linear and symmetric P/D with stable repeatability was obtained under a wide range of operating conditions, and a learning accuracy of 95% was achieved through MNIST pattern recognition simulations. [ABSTRACT FROM AUTHOR]

The design of ternary Logic gates-Ternary NAND, Ternary NOR and Standard Ternary Inverter based on the 18nm FinFET technology is proposed. The Ternary logic systems replaced Existing Binary logic systems with their good operating speed, energy efficiency, information density and Reduced circuits like chip area and interconnections. Instead of using large Resistors, the proposed model consists of 18nm FinFETs, reducing the number of resistors used. The proposed ternary logic gates are then used to carry the arithmetic operations that are basic and implement various complex functions. These ternary logic gates show the significant advantages of chip area, energy and power consumptions, denser fabrication and component count. The ternary half-adder and ternary half-subtractor circuits are then implemented by utilizing the proposed gates and then verified through the simulations. The results are then compared with the existing designs of MOSFET based Ternary logic gates. The parameters like power consumption are compared with the current MOSFET models, and then the proposed models are simulated. For simulations, Cadence Virtuoso tool and MATLAB are used to verify the authenticity of proposed designs. [ABSTRACT FROM AUTHOR]

The drain to gate capacitance (Miller capacitance) of SiC MOSFETs leads to the Miller effect during switching transients. The Miller capacitance in a phase-leg configuration causes the crosstalk, the interaction between the two complementary switches, and the Miller plateau during the switching transient. The Miller effect reduces the switching speed, reduces reliability, and increases electromagnetic interference. In this article, by injecting a mirror cancellation current, the effects of Miller capacitance are canceled. The proposed technique includes a two-stage sensing and injection network to compensate for the nonlinearity of the Miller capacitance. The proposed technique can suppress both positive and negative gate voltage spikes induced by the crosstalk and reduce the switching power loss with the increased switching speed. Because no external control signals are required in the proposed technique, it can work with almost all commercial gate drivers. The detailed design for this proposed technique is presented in this article. The proposed technique was validated with both simulations and experiments. [ABSTRACT FROM AUTHOR]

The trade-off relationship between specific on-resistance and short-circuit withstand time in 1.2 kV 4H-SiC MOSFETs was drastically increased using a novel device structure. MOSFETs with deep P-well-formed using channeling implantation were firstly demonstrated to improve short-circuit ruggedness (~4 times longer than conventional MOSFET) with no negative impact on specific on-resistance. Proposed MOSFETs achieved short-circuit withstand time of $8~\mu \text{s}$. Channeling implant with low energy was conducted to form deep P-well junctions. Fabrication of a deep P-well using channeling implantation is demonstrated using no additional nor complicated processes when compared to the conventional MOSFET fabrication process. A comparison between the conventional and novel designs was performed in terms of the output characteristics, blocking behaviors, and short-circuit ruggedness. [ABSTRACT FROM AUTHOR]

Stress-induced damage in a MOSFET can be cured by Joule heating, which can be produced by an intentional forward junction current (${I}_{\textbf {FWD}}$). This curing effect can be further enhanced by the simultaneous application of gate biasing, which does not influence the ${I}_{\textbf {FWD}}$. A MOSFET was intentionally degraded by harsh hot-carrier injection (HCI) then the damage was cured and nearly returned to its pristine state. The improved self-curing effect was quantitatively verified using low-frequency noise (LFN) analyses. Self-curing by internal heat from the ${I}_{\textbf {FWD}}$ more effectively cured the HCI damage than a nonself-curing using external heat from a hot chuck. [ABSTRACT FROM AUTHOR]

In this letter, p-type ferroelectric field-effect-transistors (FeFETs) based on HfO2 and embedded in GlobalFoundries 28 nm bulk high- ${k}$ metal gate (HKMG) technology (28SLPe) are systematically investigated and compared to their n-type counterparts. We show that the two device types, based on Si channel, exhibit a symmetric memory window (MW) and very similar switching behavior, yet profoundly different trapping kinetics. In contrast to n-FeFETs, p-FeFETs display a full MW immediately after the write operation and apparently no parasitic electron trapping. Based on this, we demonstrate an immediate read-after-write operation. Finally, we illustrate how slight structural changes of the gate stack, such as the introduction of the SiGe channel material, can enhance charge trapping and nullify the above-mentioned advantages. [ABSTRACT FROM AUTHOR]

Complementary circuits based on organic electrochemical transistors (OECTs) are attractive for the development of inexpensive and disposable point‐of‐care bioelectronic devices. Ambipolar OECTs, which employ a single channel material, could decrease the fabrication complexity and manufacturing costs of such circuits. An ideal channel material for ambipolar OECTs should be electrochemically stable in aqueous environments, afford facile ion insertion for both cations and anions, and also facilitate high and balanced electron and hole transport. In this study, triethylene glycol functionalized diketopyrrolopyrrole (DPP)‐based polymer is proposed for the development of ambipolar OECTs. It is shown that DPP‐based OECTs have a high and comparable figure of merit for both n‐ and p‐type operations. Logic NOT, NAND, and NOR operations with corresponding complementary circuits constructed from identical DPP‐based OECT devices are demonstrated. This study is an important step toward the development of sophisticated complementary metal–oxide–semiconductor‐like logic circuits using single‐component OECTs. [ABSTRACT FROM AUTHOR]