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A reconfigurable binary/ternary logic conversion-in-memory based on drain-aligned floating-gate heterojunction transistors.
- Source :
- Nature Communications; 6/23/2023, Vol. 14 Issue 1, p1-11, 11p
- Publication Year :
- 2023
-
Abstract
- A new type of heterojunction non-volatile memory transistor (H-MTR) has been developed, in which the negative transconductance (NTC) characteristics can be controlled systematically by a drain-aligned floating gate. In the H-MTR, a reliable transition between N-shaped transfer curves with distinct NTC and monolithically current-increasing transfer curves without apparent NTC can be accomplished through programming operation. Based on the H-MTR, a binary/ternary reconfigurable logic inverter (R-inverter) has been successfully implemented, which showed an unprecedentedly high static noise margin of 85% for binary logic operation and 59% for ternary logic operation, as well as long-term stability and outstanding cycle endurance. Furthermore, a ternary/binary dynamic logic conversion-in-memory has been demonstrated using a serially-connected R-inverter chain. The ternary/binary dynamic logic conversion-in-memory could generate three different output logic sequences for the same input signal in three logic levels, which is a new logic computing method that has never been presented before. Reconfigurable logic is desirable for high-density information processing. Here, the authors demonstrate a binary/ternary logic conversion-in-memory, which can operate in both binary and ternary logic systems to implement various types of logic gates. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 20411723
- Volume :
- 14
- Issue :
- 1
- Database :
- Complementary Index
- Journal :
- Nature Communications
- Publication Type :
- Academic Journal
- Accession number :
- 164492633
- Full Text :
- https://doi.org/10.1038/s41467-023-39394-5