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In the paper, the novel topology of the resonant DC link three-level soft-switching inverter is proposed to reduce switching losses and improve the efficiency of three-level inverter at high switching frequency. Symmetrical auxiliary resonant circuits are set in the DC link of three-level hard-switching inverter. Moreover, the terminal voltage of the resonant capacitors between the DC buses periodically drops to zero via the resonance of auxiliary circuits. Furthermore, under such condition, the main switches of the three-level inverter would be operated, in order to achieve zero-voltage switching. Based on the equivalent circuits in different operating modes, the paper analyses the working process of the soft-switching inverter in detail. In addition, a 3 kW laboratory prototype of resonant DC link three-phase three-level soft-switching inverter is built. The experimental results show that the main switches and auxiliary switches of the inverter are operated under soft-switching conditions, and the efficiency is significantly improved compared with the three-level hard-switching inverter. Therefore, the proposed topology can effectively reduce switching losses and prove to be more practical in engineering. [ABSTRACT FROM AUTHOR]

An auxiliary switching device is usually set on the DC bus of the resonant DC link inverter, which restricts the efficiency of the inverter and is also one of the reasons for its not extensive application and promotion in the high-power field. To solve the problem, auxiliary circuits and DC bus of the resonant DC link soft-switching inverter designed in this paper are connected in parallel, and auxiliary switching devices and resonant elements are not connected in series on the DC bus, which help to improve the efficiency and reduce the power losses of the auxiliary resonant circuits. Based on the equivalent circuits in different operating modes, the paper analyzes the working process of the soft-switching inverter, soft-switching realization conditions and design rules. A 10 kW laboratory prototype is built, and through the comparison of the experimental results from it and the hard-switching inverter, it is shown that the efficiency improvement value of the designed inverter at full load is higher than that at light load. Therefore, the soft-switching inverter designed in this paper is conductive to reducing the power losses of the auxiliary resonant circuits and ensuring the efficient use of the electric energy. [ABSTRACT FROM AUTHOR]

This article is an interesting substrate material for environmental-friendly printable electronics. In this study, screen-printed RFID tags on paper substrate are examined. Their reliability was tested with low temperature, high temperature, slow temperature cycling, high temperature and high humidity and water dipping test. Environmental stresses affect the tag antenna impedance, losses and radiation characteristics due to their impact on the ink film and paper substrate. Low temperature, temperature cycling and high humidity did not have a radical effect on the measured parameters: threshold power, backscattered signal power or read range of the tags. However, the frequency response and the losses of the tags were slightly affected. Exposure to high temperature was found to even improve the tag performance due to the positive effect of high temperature on the ink film. The combined high humidity and high temperature had the most severe effect on the tag performance. The threshold power increased, backscattered power decreased and the read range was shortened. On the whole, the results showed that field use of these tags in high, low and changing temperature conditions and high humidity conditions is possible. Use of these tags in combined high-humidity and high-temperature conditions should be carefully considered. [ABSTRACT FROM AUTHOR]

Approximate computing is an emerging paradigm that can tolerate some loss of accuracy to improve the energy consumption and design complexity. Multiplication is one of the important computational components in various digital signal processing (DSP) applications. Improvement of multipliers, as the building blocks of an approximate computing systems, has received significant attention. Compressors are key elements in an approximate multiplier to have an optimal design with high performance. This paper proposes an approximate/exact 4–2 compressor and an exact 5–2 compressor in carbon nanotube field-effect transistors (CNTFET) technology for utilisation in an approximate multiplier. Four efficient designs for utilising the proposed compressors are introduced and analysed for a Wallace multiplier. All of the proposed circuits are analysed in 32 nm CNTFET Stanford technology and are simulated by HSPICE. In addition, as an image processing application of approximate multipliers, this paper compares the quality metrics of the image multiplication for the proposed designs and previously presented approximated multipliers. For example, the proposed schemes provide excellent results in structural similarity index up to 99%, and peak signal-to-noise ratio more than 45 dB. Also, it uses figure of metric (FOM) that includes the accuracy and quality metrics of the approximate multipliers. The simulation results demonstrate the efficiency of proposed designs. [ABSTRACT FROM AUTHOR]

In this paper, a Dickson-based RF-DC (Radio frequency power to direct current power) rectifier for energy harvesting system is designed. Dickson double-voltage structure, voltage-dividing structure and switching transistors are integrated in the system to fulfil the synchronous rectifying function, which can upgrade PCE (Power Conversion Efficiency) value, reduce the threshold voltage and decrease the leakage current, etc.. The simulation is conducted on the designed synchronous rectifier for energy harvesting of 900 MHz signal. It shows that when the input voltage $${V_{IN}} = 1V$$ V IN = 1 V , the peak output DC voltage can be stabilised at 1.8 V with the assistance of LDO (Low dropout) regulator, while the reverse leakage current is below 20 µA and the PCE value reaches 58%. The designed rectifier is assembled and tested in the paper. Both the simulation and testing results demonstrate the feasibility of the proposed synchronous rectifier. [ABSTRACT FROM AUTHOR]

This paper presents the performance analysis of a five-level T-type multilevel inverter (MLI) based six-phase induction motor drive (SPIMD) for high-power industrial applications. In the adopted T-type MLI, the sensorless self-capacitor voltage balancing control is designed, which controls the voltage across the capacitor at half the magnitude of the direct current (DC) source value, creating a symmetrical five-level output voltage waveform. Moreover, self-capacitor voltage balancing control reduces complexity and improves system performance. The SPIMD with distributed neutral is taken as the load, and the whole system is simulated using MATLAB/Simulink software. The system's performance is determined by considering the power loss and efficiency. This paper also presents a comparative performance analysis of the adopted T-type, cascaded h-bridge (CHB) and Flying Capacitor (FC) MLI-based SPIMD. Finally, a prototype is developed as a proof of concept and tested experimentally to validate the analytical development of the adopted system. [ABSTRACT FROM AUTHOR]

This paper describes a printed Thai character recognition method which uses topological properties. The recognition system is divided into two stages. In the rough classification stage, a thinning technique is applied to eliminate noise and fine features. The thinned characters are separated into cluster domains by using a linear decision function based on the height and width of each character. In the fine classification stage, the ‘connected numbers’ of points in the character pattern are computed. Topological properties are then used to distinguish between the characters. [ABSTRACT FROM AUTHOR]

A method of comparing the basic performance of electron guns is described. The method is applied to some recently computed results on two versions of an electron gun which has a hairpin-filament cathode.
In an interesting and useful paper by Worster (1979 a), hereafter referred to as JW, computed results are given relating to two electron guns. When the performance of the guns was compared it was concluded that one gun was better than the other in all respects. However, in making the comparison the electron beam divergence was not taken into account. Although the method of comparison used in JW may, of course, be satisfactory for some purposes, the computed results in JW are comprehensive enough to provide information for an alternative method of comparison which includes beam divergence. Such an alternative method, described in this note, leads to different conclusions. [ABSTRACT FROM AUTHOR]

In this paper, we present a design method for a highly efficient retrodirective array (RDA)-based microwave power transfer (MPT) system for the mMTC scenario, and evaluate its characteristics through experiments. Long-range wireless power transfer is required to effectively support the mMTC situation. RDA-based MPT controls and tracks the power beam towards the device within a certain range and it enables efficient power transfer. The overall link budget analysis is examined first and the required antenna gain is calculated. The required antenna gain can be secured using multiple-antenna modules. So, it is possible to design an RDA-based MPT system. In this paper, we implement a reduced RDA-based MPT system and evaluate its characteristics to confirm the feasibility of this design method. Through experiments, it has been confirmed that additional gain can be secured by using multiple antenna modules, and the RDA function can be effectively operated to effectively make a power beam in the direction of the power receiver. Conclusively, the gain of about 2.2dB increased whenever the number of antennas is doubled. The experimental results also show that the RDA-based MPT system designed in this paper is capable of adaptive power beamforming from −30 degrees to 30 degrees. [ABSTRACT FROM AUTHOR]

This paper proposes an efficient design of Hamming (11, 7) encoder utilising Full Swing-Gate Diffusion Input (FS-GDI) approach in 65 nm technology nano-size node. The proposed design of Hamming codes aims to improve the power and area efficiency through reducing of transistors count by employing power-efficient logic style. Encoding circuits of Hamming code (11, 7) and (7, 4) are designed using the various traditional and proposed approaches. The amount of consumed power, delay time, Power Delay Product (PDP) and hardware simplicity are employed as a metrics for evaluating the efficiency of the proposed designs of encoding circuits. The simulation experiments are executed utilising Cadence Virtuoso simulator package. These experiments revealed that the proposed designs of Hamming encoding circuits achieve delay time reduction by 50.91% and 20% for Hamming codes (7, 4) and (11, 7), respectively. Also, hardware (H/W) simplicity and area efficiency of the circuits are improved by 50% compared to CMOS-based circuits. From the results analysis, the proposed FS-GDI based Hamming encoding circuits achieve efficient power and delay optimising. Hence, the power consumption, delay and area in communications systems and DSP circuits due to encoding process are reduced. The whole performance of DSP circuits can be more power/area efficient. [ABSTRACT FROM AUTHOR]

Examines the characteristics of travelling waves along the non-linear transmission lines for monolithic integrated circuits. Analysis of slow-wave structures like MIS and Schottky-barrier strip lines; Examination of suitable equivalent circuits leading to characteristic wave equations; Parameters of the non-linearity, dispersion and dissipation and the boundary conditions of practical devices.

Examines the use of distributed, monolithic travelling-wave amplifiers. Guidance on reducing amplifier noise by rendering dipole-domain-generated noise contributed by the individual field effect transistor (FET); Use of insulated gate FET to permit higher gate breakdown voltage operation in the accumulation mode; Reduction of even harmonics and the improvement of efficiency.

Discusses the statistical properties of randomly generated boolean functions. Effect of prime implicant errors in the minimization algorithms; Relationship between the number of variables in the boolean expression on the k-subcube probability to be a prime implicant.

Electronic devices are persisting as the integral part in various medical devices. These devices require SRAMs (Static Random Access Memory) with power efficient capability to handle the data, as they occupy most of the die area. Especially, wearable devices are bringing new challenges in the design of an IC, where high stability and low static power dissipation are very much required. In this paper, two new Carbon Nanotube Field Effect Transistor (CNTFET) based 9T SRAM cell topologies are presented to improve the leakage power dissipation at standby mode while maintaining the stability of the cell. Differential bitlines with decoupled read port are used to assist the read disturbance and the subthreshold lowering as well as stack of transistors are employed to curtail the leakage power. The circuits are implemented at 900 mv in Cadence using CNTFET technology. The Architecture with a 4 × 4 array matrix of the proposed 9T cells is designed. These are found to be the better ones yielding good results compared to the existing designs. [ABSTRACT FROM AUTHOR]

All-pass transformation (APT)-based variable digital filters (VDFs) can be used in different biomedical signal-processing applications, particularly in electrocardiograph denoising. In this paper, arithmetic optimised APT-VDF is proposed by modifying the hardware structure of APT-VDF based on arithmetic perception to enhance the performance in terms of area, speed and power consumption. The core blocks of the suggested Arithmetic Optimised APT-VDF (AOAPT-VDF)are adders and multipliers. This paper introduces a new reusable Vedic multiplier with redundant detection unit to identify redundant computations while generating the partial products. Also, a new Carry select adder (CSLA) with simplified combinational logics is proposed to improve the performance of the CSLA by simplifying the partial sum and carry generation logics without requiring Ripple Carry Adders. The proposed Reusable Vedic Multiplier with Redundant Detection Logic (RVM-RDL) also reuses the same vertical and cross-product generation units repetitively to reduce the area while increasing the bit length. The effectiveness of the suggested AOAPT is analysed utilising the MIT-BIH Arrhythmia Database. The proposed AOAPT-VDF consumes only 0.21 $$W$$ W power and achieves a 235.50 MHz operating frequency. [ABSTRACT FROM AUTHOR]

The first part of the paper discusses designing of the lowpass filter that gives both a constant group delay over the passband and a sharp cut-off slope, which is one of the most difficult challenges in continuous-time signal processing. Furthermore, equalisation of the group delay distortion of the Chebyshev filter has been performed through a cascade connection of the allpass filters. The Newton–Raphson method is applied for solving the system of nonlinear equations that calculate the allpass filter parameters for equalising the constant group delay in an equiripple sense. This procedure gives nearly symmetric impulse response of the resulting filtering system, as well as a longer duration. In the second part of the paper, two solutions for synthesising polynomial filter transfer functions are discussed: filter with monotonic amplitude characteristic (LSM) and filter using Chebyshev polynomial. For the purpose of comparison, the passband ripple factor of the Chebyshev filter is necessary to be adjusted so that both filters have the same stopband insertion loss, group delay and transient response. It is shown that Chebyshev filter is preferable since the passband magnitude distortions and sensitivity to the element deviation tolerance are significantly superior. [ABSTRACT FROM AUTHOR]

The grid-forming inverter (GFI) plays an indispensable role in the microgrid (MG). Thus, it is critical for a microgrid to control the GFI flexibly and accurately, because of its voltage-forming and frequency regulation capabilities. The conventional proportional integral (PI) control strategy is usually used to control the GFI. However, the conventional PI control strategy has a high output voltage total harmonic distortion (THD) and deteriorative performance under external disturbances, which results in several problems in system flexibility, reliability and stability. This paper proposed a novel adaptive sliding mode control (ASMC) based cascaded control of the GFI system, which involves an ASMC-based inner current loop and outer voltage loop, and shows some superior performances of low THD, fast dynamic tracking performance and good robustness. Both the MATLAB/SIMULINK-based simulation and StarSim Modelling Tech-based semi-physical experimental results were presented to validate a perspective: the control strategy proposed by this paper has a better performance than the conventional PI control strategy under transient and steady-state condition. [ABSTRACT FROM AUTHOR]

Comments concerning on inconsistencies in the analysis of alpha-particle scattering. Validity of the field concept; Relation between the laws of physics and relativity; Information on the theory of electromagnetic.

In this paper, the applicability of dual material stacked gate-oxide-Pocket doped-hetero-junction tunnel field effect transistor (DMSGO-PD-HTFET) for low power switching and radio frequency (RF) applications is investigated. In this context, gate workfunction engineering, the stacked-gate-oxide ($$Si{O_2}$$ Si O 2 + $$Hf{O_2}$$ Hf O 2 ) approach, and asymmetrical doping at the P+ source ($$S{i_{1 - X}}G{e_X}$$ S i 1 − X G e X ) and N+ drain regions are considered. N+ pocket at source-channel interface implements DMSGO-PD-HTFET and improves interband tunnelling rate. This research aims to improve the device's switching ratio ($${I_{ON}}$$ I ON / $${I_{OFF}}$$ I OFF ), average subthreshold swing ($$S{S_{Avg}}$$ S S Avg ), and radio frequency (RF) performance. For this, the control gate work function, mole fraction (X), pocket thickness, and doping concentration are optimised. Next, the DC, analog/RF and linearity figure of merits of the proposed device is analysed and the performance is compared with conventional all-silicon dual-material stack gate oxide tunnel field effect transistor (DMSGO-TFET) and dual-material stacked gate oxide-hetero-junction tunnel field effect transistor (DMSGO-HTFET) with $$S{i_{1 - X}}G{e_X}$$ S i 1 − X G e X source using technology computer-aided design (TCAD) device simulator. Based on the comparative analysis, the optimised design with $$S{i_{0.6}}G{e_{0.4}}$$ S i 0.6 G e 0.4 exhibits an average subthreshold swing ($$S{S_{Avg}}$$ S S Avg ) of 28.8 mV/decade, switching ratio ($${I_{ON}}$$ I ON / $${I_{OFF}}$$ I OFF ) of 2 × 1012, cut-off frequency ($${f_T}$$ f T ) of 216 (GHz), and other significant improvements in analog/RF and linearity performance parameters. The proposed device is therefore suitable for switching and RF applications. [ABSTRACT FROM AUTHOR]

A novel approach for the dielectric characterisation of 3D printed substrates in S-band applications of patch antennas with different infill percentages is presented in this paper. The meta-structure substrate design has been 3D printed with a fused deposition modelling technique using bio-sourced material poly-lactic acid (PLA). Combining different infill patterns changes the dielectric parameters, and hence, the RF(Radio-Frequency) performance of the design. To validate the usefulness of this approach, the Taguchi sampling technique is used, where nine samples of a meta-structure substrate were designed to determine the dielectric properties of the substrate. The ring resonator technique is used for measuring the dielectric constant and loss tangent of the fabricated substrates. All nine meta-structure substrate shows varying dielectric properties, which can be used for tuning of RF characteristics of the patch antenna. The measured permittivity of various substrate structures ranges between 2.39 and 2.71. The concept of propagation delay is chosen as the selective parameter for the fabrication of the antenna. The results of antenna simulation and fabrication were mapped closely. The proposed meta-structure design antenna resonates at 2.43 GHz with an S11 of −26.60 dB. Gain enhancement of 5% is seen in the selected meta-structure design compared with the simple (solid) structure. This meta-structure substrate design approach using different patterns is simple, scalable and can be realised in other 3D printed antenna applications. [ABSTRACT FROM AUTHOR]

Remarkable characteristics like simple structure, high starting torque, simple maintenance, good efficiency at all speeds and cost-effectiveness have made switched reluctance machines (SRMs) suitable candidates for electric cars, electric bicycles and variable speed applications (VSAs) such as wind turbines. In this paper, a three-phase Outer-Rotor SRM (ORSRM) with 6 stator poles and 10 rotor poles (6/10) for VSA has been investigated. Unlike conventional SRM structures such as 6/4 and 12/8, an SRM model with higher number of rotor poles can reduce torque ripple much more effective than conventional SRMs. First, the SRM design is done accurately, then, by changing some parameters, the sensitivity analysis is performed on torque ripple and average torque. Finally, the optimisation process on the geometry and structural dimensions of the SRM like rotor pole arc, stator pole arc, rotor yoke thickness, rotor pole height, rotor diameter and the number of turns per phase are executed to minimise the torque ripple and maximise the average torque via genetic algorithm (GA). The initial design, optimisation and performance of the proposed model are validated via a 2-D finite element method (FEM) technique by ANSYS-Maxwell. [ABSTRACT FROM AUTHOR]

In this paper, a high-efficiency class-F power amplifier with a harmonic control circuit is proposed. The harmonic control circuit is realised by loading microstrip branch lines to achieve a short-circuit state for the second harmonic. The double spiral defected ground units are loaded on the ground of the microstrip line of the drain bias circuit to produce a low-pass filtering and stopband suppression effect outside the passband, so as to suppress the third harmonic. Meanwhile, it would provide an open-circuit state for the third harmonic, and finally meet the harmonic impedance tuning demands of class-F power amplifier. Through theoretical analysis and simulation, a high-efficiency class-F power amplifier operating at 2.5 GHz ~2.7 GHz is designed. The measured results show that in the working frequency band, the drain efficiency is 66.3%~71.1%, the output power is 40.9 dBm ~42.1 dBm and the gain is 10.9 dB ~11.8 dB. [ABSTRACT FROM AUTHOR]

Aiming at the problem of unstable output voltage and rapid reduction of efficiency caused by coil misalignment in the wireless charging process of wireless chargers, a hybrid wireless power system with anti-misalignment and constant current (CC) output characteristics is proposed. The system uses a high-order compensation network and a four-coil bipolar (BP) coupler to implement high anti-misalignment and CC output characteristic that is decoupled from the load. By inserting a high-order compensation network, the two overlapping coils in the same side of the transmitter and receiver sides of the BP coupler can be effectively decoupled and the design methodology can be simplified. Moreover, by adjusting the inductance value of the transmitter compensation network, the BP coupler can be made available for the occasions with different equivalent mutual inductance (MI) fluctuation requirements. While the receiver coil is suddenly removed, the system has a self-protection function, which can effectively limit the current flowing through the inverter. The design ideas of the coupler and compensation network are also discussed in this paper. Ultimately, a 1-kW experimental prototype is built to validate the proposed scheme. [ABSTRACT FROM AUTHOR]

Wireless power transfer (WPT) has been developed as a suitable candidate for energy transfer in various applications, recently. Resonant tank is the main passive part of such systems and various topologies are introduced to improve WPT systems performance. Characteristics of these topologies definitely affect system overall performance. Therefore, each topology's specification and performance indexes should be evaluated and compared to choose a suitable one for a required application. In this paper, the characteristics and behaviour of voltage gain, input admittance and efficiency of well-known compensation topologies are thoroughly investigated for the first time. By calculating the voltage gain sensitivity, some analysis are performed on typical compensation including SS, SP, LCL-S, LCL-P, LCC-S, LCC-P and double-sided LCC under key parameter variations such as load resistance, switching frequency and coupling coefficient. In addition, by introducing a new formula for efficiency, the effect of resonant tank elements on efficiency is studied analytically which has not been performed before. In order to evaluate the theoretical analysis, the performance of all compensation topologies is investigated in MATLAB environment. By employing prototype SS and SP compensated inductive power transfer (IPT) test-bed system, some experimental verification are performed and the results confirm the analytical and numerical simulation findings. [ABSTRACT FROM AUTHOR]

In this paper a new non-isolated converter with ultra-high voltage gain is presented. The proposed converter utilises coupled inductors, lift circuits and interleaved technique to convert low-level DC voltages to high-level DC voltages without high turn ratios or large duty cycles. Winding-cross-coupled inductors are employed to raise the voltage ratio. The voltage and current stress of semiconductors are reduced, which causes low conduction losses and improves the efficiency. The way the clamp circuit is used limits not only the spike voltages but also effect on the conversion ratio of the proposed converter and make it larger. The main features of this converter are high voltage gain, low voltage stress of semiconductors, low reverse recovery of diodes, low input current ripple, low conduction loss and high efficiency. A prototype of the proposed circuit is constructed in laboratory at 100 W converting 20 V to 450 V. The experimental results are compared with theoretical analysis which verifies them. [ABSTRACT FROM AUTHOR]

This paper proposes a new generalised boost integrated multilevel inverter (MLI) with reduced components. The proposed MLI is developed by using a modified boost integrated switched capacitor unit, which provides four-level output from each cell. The operation of the proposed MLI for symmetrical 17-level operation with sinusoidal pulse width modulation & nearest level control and asymmetrical 31-level operation with NLC is explained and validated experimentally. The experimental results of static and dynamic load conditions are analysed and discussed in detail. In addition, the proposed topology is compared with recent boost MLI topologies in terms of component count, device stress, efficiency, capacitor size and cost. From the comparative study, it is evident that the proposed MLI provides features such as reduced component count, capacitors size, overall cost and improved voltage gain. [ABSTRACT FROM AUTHOR]

A differential ring CMOS voltage-controlled oscillator (VCO) with dual-delay path topology is proposed in this paper. In this work, the focus area is to improve the tuning range of VCO and phase noise performance of the VCO. The dual-delay path topology is used with P-MOS as load in series with negative-skewed delay transistors. This design gives the wider tuning range and this increases the phase noise performance of the VCO. After the post-layout simulation, frequency tuning range and power dissipation range are 730 MHz to 2.81 GHz and from 1.32 mW to 4.62 mW respectively. The phase noise for this VCO is −97.35 dBc/Hz at 1 MHz offset. The technology used in this work was taken from the library of SCL 180 nm technology. This design exhibits excellent phase noise performance. [ABSTRACT FROM AUTHOR]

This paper introduces a hybrid multilevel inverter (MLI) with reduced switch count, which can generate higher output voltage level with minimum number of DC input sources. The operation of this proposed MLI is carried out with unequal DC sources to achieve the desired output voltage level. The reduced MLI output voltage is set to minimal total harmonic distortion (THD) with the help of modified JAYA (MJAYA) algorithm. A JAYA algorithm with improved steps by adopting an accelerating parameter has been proposed in this research work to obtain a faster convergence of the objective function. The MJAYA algorithm has provided the suitable switching angles for the proposed three-phase 15-level MLI and reduced the output voltage THD to 2.23%, which satisfies the standard set by IEEE-519. To prove the efficiency of this proposed modified algorithm, the comparative analysis is carried out through MATLAB program and Simulink tool using common JAYA and modified particle swarm optimisation algorithms. The performance and productivity of the proposed MLI have been investigated through simulation and experimental setups. [ABSTRACT FROM AUTHOR]

This paper investigates the design and analog the behaviour of an L-Patterned Negative-Capacitance Dual Tunneling Vertical TFET (L-NC-DT-VTFET) device with the idea of corner tunnelling and vertical tunnelling. In this proposed structure, the tunnel junction can be used over a large region in a perpendicular alignment to the channel direction. Furthermore, the gate of an L-NC-DT-VTFET is positioned vertically in the L-shaped to boost ON current. Moreover, adding the p+ pocket in the channel helps reduce ambipolar current and improves the ON current. By adjusting the thicknesses of the ferroelectric layer and pocket, the device design is created deliberately to improve the on current to off current ratio $${{({I_{ON}}} \mathord{\left/ {\vphantom {{({I_{ON}}} {{I_{OFF}}}}} \right. \kern-\nulldelimiterspace} {{I_{OFF}}}})$$ (I O N / I O F F ). The tunnelling current generated by dual tunnelling and negative capacitance extricates the collected holes, minimising the kink effect. The characteristics of the proposed L-NC-DT-VTFET structure are examined to those of known TFET architectures, and the suggested design appears to be a better match for high-performance, low-power applications as the device design maximise vertical tunnelling over corner tunnelling. [ABSTRACT FROM AUTHOR]

In this paper, a type of variable step size LMS named weighted zero attracting variable step size (WZAVSSLMS) is equipped with the control algorithm for governing DSTATCOM. In WZAVSSLMS, the ability of zero attracting nature to a variable step size (VSSLMS) for improving convergence rate is observed. WZAVSSLMS algorithm-based fundamental extractor is developed to identify the fundamental quantity of the load current for a three-phase four-wire DSTATCOM with non-linear load in this work. This type of variable step size LMS has provided a concession for quick convergence rate and steady-state error. Precision and convergence of responses are accomplished by the learning rate control. As a result of these features over conventional LMS, the authors choose WZAVSSLMS based approach in well-known DSTATCOM system to compensate power quality issues. The fundamental extraction from the distorted load current constitutes the main divergences in the proposed study. Further, the Finite control set model predictive control (FCS MPC) of the distribution static compensator (DSTATCOM) using Weighted Aggregated Sum Product Assessment Solution (WASPAS) method is implemented. [ABSTRACT FROM AUTHOR]

Digital filters with variable bandwidth can be used for a variety of applications. Arbitrary change in the bandwidth of a digital Finite Impulse Response (FIR) filter can be acquired using sampling rate converters (SRCs). In this paper, a SRC is proposed which is generated from Pascal structure, a fractional delay filter having low hardware complexity and high modularity. A low-pass filter having a single bandwidth sandwiched between two SRCs can contribute multiple bandwidths in such a way that each bandwidth is an arbitrary variation of the original bandwidth. A two-stage frequency response masking (FRM) approach is used for the hardware efficient design of the original low-pass filter. A low complexity and high modularity novel design for a continuously varying bandwidth of a digital FIR filter is proposed in this paper using the proposed SRC. The modularity of the Pascal structure can be used to control both pass band ripple as well as stop band attenuation of the continuously variable bandwidth FIR filter design. Different communication standards in a software-defined radio (SDR) channelizer is realised using the proposed design of continuously variable bandwidth filter. [ABSTRACT FROM AUTHOR]

The Multiple-Input Multiple-Output (MIMO) scheme uses multiple antenna configurations to achieve high throughput data transmission in current communication systems. The new generation wireless communication system considers using generalised frequency division multiplexing (GFDM) due to its advantages such as lower out-of-band (OOB) emission and peak-to-average power ratio (PAPR), etc. However, inter-symbol interference (ISI) and inter-carrier interference (ICI) occur due to GFDM utilises the pulse shaping filter. This paper proposes a low-complexity joint minimum mean square error (MMSE) receiver to suppress ISI, ICI, and multi-user interference (MUI) for multi-user MIMO-GFDM (MU-MIMO-GFDM) system. The conventional approach is to design the equalisation and the GFDM demodulation separately. This paper jointly designs the equalisation and demodulation process that significantly reduces the complexity and enhances the error rate performance. This paper also analyzes the closed-form expression and two low-complexity methods for the proposed receiver. The simulations demonstrate the effectiveness of the proposed low-complexity multi-user MIMO-GFDM receivers. [ABSTRACT FROM AUTHOR]

For meeting the actual demand of constant current (CC) and constant voltage (CV) in lithium-ion battery-charging process and improve the flexibility and safety of charging, this paper proposes a family of hybrid inductive power transfer (IPT) topologies that can realise CC and CV output and are not limited by the parameters of coils. Starting from a single existing topology with configurable CC or CV output, which can achieve zero-voltage switching (ZVS), load-independent and approximately zero reactive power, and the missing configurable CC or CV output is obtained by circuit transformation through cascaded T-type network. Then, the cascaded T-type network is switched by mode switches, so as to derive a family of hybrid IPT topologies suitable for lithium-ion battery wireless charging. In order to reduce the number of devices in the compensation network, the T-type network can be integrated with the existing compensation networks. Hence, this paper also proposes some hybrid IPT battery chargers and their design ideas. The control logic of mode switches and the sensitivity of compensation parameters are also discussed. Ultimately, a hybrid IPT battery charger based on S-S and S-LCC compensation networks is developed to test the correctness of the proposed scheme. [ABSTRACT FROM AUTHOR]

This paper presents an implementation of inductorless and resistorless Chua's chaotic oscillator using voltage-differencing gain amplifier (VDGA). The chaotic oscillator circuit is implemented by designing a resistorless Chua's diode using a single VDGA and a VDGA-based tank oscillator with coupled network circuit. The proposed chaotic oscillator uses two VDGAs and three grounded capacitors only. Although resistors and inductors may also be fabricated, the use of no resistor and inductor makes the circuit suitable for fabrication in terms of cost and area. It offers the advantages of an increased frequency spectrum having a dominant operating frequency of 21.1 MHz. The Chua's circuit is simulated in Pspice using both macro models of IC MAX435 and 0.18 µm CMOS TSMC Technology parameters. As a result, chaotic waveforms (V1 and V2) and the various attractors (V1 versus V2) are found in the simulation. These results confirm the theoretical predictions of Chua's chaotic oscillator. Various aspects of the proposed implementation of Chua's oscillator are compared with the earlier implementations. Finally, the paper concludes with simple remarks on the proposed circuit. [ABSTRACT FROM AUTHOR]

Rapidly growing technology has increased the demand for digital signal processing applications that are fast and effective in real-time. One of the basic operations frequently required in these applications is the multiplication operation. There is a need to develop a multiplier with high speed, less area, and low power consumption to improve its performance. One of the fastest multiplier circuits is the Radix-4 Booth multiplier. Booth encoder reduces the number of partial products and hence the number of additions. The pipeline scheme is one of the most used designs to accelerate the multiplier performance. In this paper, two designs are presented. The first proposed design aims to reduce the delay of the multiplication operation of a 16 × 16 multiplier. This design uses a pipeline scheme differently by partitioning the input into two parts and overlapping their processing. The second proposed design reduces the multiplier area by applying enhancements in the modified booth encoder circuit. The proposed circuits are synthesized using XILINX ISE 14.7 and realized using ML605 Virtex 6 FPGA board. The first proposed design achieves higher speed, lower power consumption, and less area than the prior design. The second proposed design achieves more area and power consumption reduction. [ABSTRACT FROM AUTHOR]

This paper presents an area/power efficient design for the Arithmetic Logic Unit (ALU) utilising the FS-GDI approach. The presented ALU is designed in 45 nm, 65 nm and 130 nm node using Cadence Virtuoso simulator. Various ALUI/ALUII designs are presented with different data words. The result of ALUI proves its superiority compared with the traditional CMOS-based design in terms of power consumption, propagation delay and transistor count. The energy of the proposed 4-bit ALU reduced by 32% compared to CMOS based. Scalability of the proposed ALUI and ALUII designs are tested by extending length of the processed bits to 32-bits, through testing the performance of 8-bit, 16-bit, 32-bit ALUs based on the proposed ALUI and ALUII design. It is seen that the energy of the 4-bit ALU reduced by 21.2%, the power efficiency of the DSP and image processing circuits can be improved utilising the proposed designs of the ALUs. The experiment clears the superiority of the proposed ALU units and its suitability for long data words. [ABSTRACT FROM AUTHOR]

The rapid growth of the communication frequency band leads to the diversity of receiving frequency bands of smart devices. This paper proposes a reconfigurable wireless superheterodyne receiver for multi-standard communication systems. The receiver is designed through architecture design, chip selection, layout drawing, and physical measurement. The designed receiver consists of receiving module, local oscillator module, and control module. Unlike previous receivers, the proposed receiver selects the frequency channel, local oscillator frequency, and link gain through the control module in the current scene. The control module consists of a single-chip microcomputer and computer. The receiver can work in application scenarios including 2.4–2.5 GHz, 3.3–3.6 GHz, and 4.8–6.0 GHz. This paper discusses the design process of the proposed reconfigurable receiver in detail. Compared with the traditional receiver, the proposed receiver can change its working mode by software and has the characteristics of flexible reconfiguration. In addition, it has the advantages of a large link gain range and good demodulation performance. Moreover, the receiver is low in design cost and easy to manufacture. Therefore, it can be widely used in receiving modules of WLAN and 5G communication systems. [ABSTRACT FROM AUTHOR]

The paper presents the measurement study of a double channel pHEMT device. Its focus is on examining impacts of several parameters including probe pitch size, position and the applied pressure on the measurements. The impact of probe pitch size, position and applying suitable amount of pressure and more pressure than required on the measuring perspective of a double channel pHEMT was investigated. As noted from the collected data, these impacts are most likely related to the stability factor, current gain and maximum available gain of the studied microwave device. The measurement was done using two probes with pitch sizes of 200 µm and 150 µm, and the probes were placed in the middle of the device's contact pads while exerting appropriate pressure. For double channel pHEMT on wafer, the outcome can be deemed similar for both pitch sizes. On the other hand, the probe with pitch size of 200 µm is utilised for applying more pressure than required where the probe occupied the entire pads of the device and the findings are skewed. Finally, it was found that the RF measurement is frequently affected by these conditions while the DC measurements are unaffected or have a minor effect. [ABSTRACT FROM AUTHOR]

The presence of turning points (stationary points like maxima and minima) in the Parameter-versus-state map (PSM) curve of a memristor can be beneficial in several memristive uses like multi-level logic design, multi-bit memories, and chaos generation circuits. Surprisingly the memristors with these types of PSM curves exhibit multiple crossing points in the transient input v-i contours. In this paper, the memductance model has been derived for such non-linear memristors exhibiting multi-cross-over characteristics. In the presented framework, the coefficients-related condition for the multi-turning point PSM curve has been derived, a necessary condition for the multi-crossing v-i contour. The condition related to the memristor operating parameters has also been reported taking both input signal and initial states into consideration. To realise the derived memductance model corresponding to the three cross-over memristive behaviour, an OTA-based memristor emulator has been developed. Unlike some existing fractional order non-symmetric multi-crossing memristor emulators, the proposed emulator circuit realises an integer order memristor function operating at moderate frequencies. The realised emulator uses only four OTAs and three grounded passive circuit elements with no external multiplier. For the CMOS implementation of employed OTA, the simulation results are obtained to verify the three pinch-off behaviour. [ABSTRACT FROM AUTHOR]

This paper presents a novel low-voltage low power fully differential class AB current output stage with high linearity and unique current drive capability. The proposed circuit is based on a simple and efficient structure to obtain high linearity by minimising the channel length modulation effect and also avoids cascade structure to act best in low-voltage applications. Giving the complete analyses and equations of the circuit, its properties are verified by Cadence using TSMC 0.18 µm CMOS parameters. In order to study its performance at the presence of non-idealities, Pre-layout and Post-layout both plus Monte–Carlo simulations are also performed. Under±0.9 V supply and 35 µA output bias current, it can deliver the ever high output current of ±350 mA with THD of −49 dB and output impedance of 2.8 MΩ, which leads to a unique high current drive ratio (Ioutmax/Ibias) of 10,000 and low consumed power of 150 µw in pre-layout simulation. In post-layout plus Monte–Carlo simulation, the results will be as ±320 mA output current, −42 dB THD, 2.2 MΩ output impedance, 40 µA DC current of the output branch, 8000 current drive ratio and 160 µw consumed power. These remarkable results prove the proposed novel COS not only as the unique one in the world but Longley ahead of the yet second rank COS by some unbeatable ratios as 11300×,14×,4× and3× in FT, Ioutmax, (Ioutmax/power), and current drive, respectively, that promise to keep it as the lead one for many years in low-voltage/power ultra-high current applications. [ABSTRACT FROM AUTHOR]

In modern days, MLIs comprise a lot of concentrations in academia and industry. As they are altering interest in a feasible technology in supporting frequent applications of renewable energy conversion systems and drives, these huge power and medium/higher voltage applications and MLIs are extensively used as one of the sophisticated powers converter topography. The MLIs are divided into two types such as asymmetric and symmetric. MLIs of the asymmetric kind have more amount of output AC voltage stage with fewer DC input source voltage and switching components. In this research paper, asymmetric single-phase cascade full-bridge MLI is developed with carrier-based unipolar PWM techniques. This MLI can generate nine-stage of output AC voltage through eight switches and two input DC sources. It is tested through a variety of multicarrier unipolar PWM control combinations. The Phase Disposition (PD), Alternating Phase Opposition Disposition (APOD), Carrier Overlapping (COP) and Variable Frequency (VF) are all PWM control which included in support of preference of single-phase nine-stage ternary cascade multilevel inverters. With various modulation indices (ma), the harmonic substance of output AC voltage for each approach is observed and tabulated. The proposed design for generating nine-stage output AC voltage is demonstrated using MATLAB-SIMULINK and confirmed using a laboratory-based prototype model. The results show that the unipolar Alternating Phase Opposition Disposition PWM technique that provides a high-quality output voltage with less harmonic distortion. Besides, the performance of Carrier Overlapping PWM techniques is greater since it produces a superior fundamental RMS output AC voltage. [ABSTRACT FROM AUTHOR]

This paper presents a novel multiphase hybrid matrix converter topology dedicated to grid-connected five-phase wind generation. The proposed converter, named Five-phase Ultra-Sparse Series Z-source Matrix Converter (FUSSZMC), aims to facilitate the integration of the five-phase wind turbine generators. This is done by taking into account the improvement of the injected power quality and allowing the fixed output converter voltage level to that of the grid, thanks to the use of the series Z-source, under the variable voltage magnitude of the wind turbine generator, which depends on the wind speed. The proposed space vector modulation as a control strategy for FUSSZMC was detailed, where it was demonstrated that a suitable use of both large and small current vectors improves the input current waveforms. The global model of the proposed system was tested by simulation under Matlab/Simpowersys environment. The obtained results demonstrate clearly the advantages of using FUSSZMC and its modulation strategie. These benefits includea good input and output current waveforms, as reflected by the obtained total harmonic distortion (THD) values, that fall within the range prescribed by international standards. Additionally, FUSSZMC is capable of operating with unity input power factor, regulating input voltages and improving the quality of injected power into the grid. [ABSTRACT FROM AUTHOR]

This paper proposes a system with Non-linear Carrier (NLC) controller for a high-voltage gain Quadrupler Converter (QRC). The system is 400 V DC Micro Grid (DCMG) with Wind Energy Conversion System (WECS). The quadrupler converter is a non-isolated topology that achieves single-stage high voltage gain with a low duty ratio and reduced voltage stress of semiconductor devices. The proposed system assures robust dynamics against changing operating conditions, variations in circuit parameters, and external load conditions. The parameters, such as voltage gain, voltage ripple, current ripple, delay time, settling time and peak overshoot, are assessed to ensure the agility of the proposed system. The performance of the proposed system is analysed with various wind speeds using Matlab Simulink-based simulation studies. The results inferred that the proposed method provides a fast response for various input and load variations and high gain at low duty ratio. A 200 W wind-connected QRC system with an NLC controller prototype is developed to validate the simulation results. [ABSTRACT FROM AUTHOR]

Traditional central control system is unable to deal with the optimal control tasks of modern distribution networks due to its low reliability, high computation and communication burden and poor expansibility. Based on distributed collaboration principle, this paper presents a multiple-object distributed optimisation control strategy for distribution network utilising DG grouping method. Distributed control strategy for node voltage control group is developed by taking the capacity utilisation ratio (CUR) of DG as the consensus variable, to comply with the feature of high resistance/reactance ratio of distribution network feeder line. Distributed control strategies for exchanged power control groups, which respectively takes CUR and power factor as the consensus variable, are formulated according to the different conditions of exchanged power imbalance. The parameter tuning method for three kinds of distributed optimisation control strategies are presented. The correctness and effectiveness of the proposed method are verified by simulation examples in the IEEE 14-node system, and simulation results on the IEEE 33-node test system are presented to show the robustness of the method to the disturbances related with distributed generation. [ABSTRACT FROM AUTHOR]

This paper proposes a novel compact tri-band bandpass filter based on two coupled asymmetrical stub-loaded resonators (ASLR). The proposed filter can achieve three resonant frequencies by tuning uniform impedance line, short-circuit stub, and open-circuit stub, respectively. In addition, the asymmetrical stub can be loaded at any position of the main branch, which will facilitate the circuit design for no impedance of special ratio is needed, and the design bound can be alleviated. Meanwhile, thanks to its simple structure, the whole filter occupies an area of 0.021 λg2 based on RO4350B substrate, much smaller than other similar tri-band filters. Measurement results show that the filter achieves fractional bandwidths (FBW) of 7.5%, 6.4% and 4.2%, respectively for three bands. The proposed filter is small and can achieve a high-frequency selectivity at 2.45 GHz, 3.5 GHz and 5.25 GHz, corresponding to Bluetooth, World Interoperability for Microwave Access (WiMAX) and Wireless Local Area Network (WLAN), respectively. The proposed filter will find a wide application in wireless communications thanks to its attractive advantages. [ABSTRACT FROM AUTHOR]

Photovoltaic (PV) systems are widely recognised as one of the most essential renewable energy sources for meeting future energy demands. The use of various multi-input DC–DC converters (MICs) to interface PV systems for output voltage regulation has been reported in the literature. PVs have inherent limitations, such as being extremely sensitive to changes in atmospheric conditions and human design/installation errors. Therefore, output voltage regulation suffers because of wide input voltage variations which have been ignored. In this regard, a novel MIC topology is proposed in this paper and it can operate under wide input voltage variation in buck, boost, and buck-boost modes of operation to achieve desired output voltage. The proposed topology is capable to integrate multiple energy sources and it offers an individual or simultaneous operation of the connected energy sources. Further, it also has additional features including high voltage gain, modularity, and control flexibility. The steady-state and thermal analysis have been presented, as well as a comparison with the state-of-the-art literature to prove the suitability of the proposed topology for PV application. The proposed MIC topology has been validated experimentally with wide input voltage variation. [ABSTRACT FROM AUTHOR]

The Quantum-dot Cellular Automata (QCA), an emerging technology, is observed to be the most viable solution to current CMOS. It is capable of finding solutions to challenges, like high power consumptionand device density. The elementary logic primitives are the majority gate, inverter and wire. In QCA, two different event cell orientations for the realisation of the inverter are available, where the diagonally oriented structure (DOS) is mostly utilised in logic synthesis. However, considering the cell misalignment and displacement, the DOS prevails with a more stable polarised output. But the use of DOS increases cell count which increases the area of the circuit. So, it is desirable to minimise the inverter in a circuit due to the non-availability of the simple logic unit of the inverter. In this paper, two algorithms are proposed for the synthesis of cost-efficient QCA circuits from any boolean function to minimize logic primitives. The proposed role-based mechanism for boolean function synthesis results in the reduction of inverter gate, circuit size, QCA cost and power dissipation. The efficiency of the proposed algorithms has been verified with the realization of standard functions, adders and symmetric functions. A significant improvement in inverter reduction has been reported. [ABSTRACT FROM AUTHOR]

This paper proposes an interleaved multilevel converter (MLC)-based charger with power rating 2.8 kW to charge on-board battery of electric vehicle (EV). It comprises two stages: (1) an interleaved multilevel ac–dc converter; and (2) an LLC-resonant dc–dc converter. The interleaved approach efficiently maintains the optimum power level. The switching scheme implemented for MLC maintains the source current sinusoidal, supports unity power factor (UPF) and has the capability to balance the capacitor voltage. The MLC maintains UPF and balances capacitor voltage without any auxiliary circuit. In addition, MLC provides lower voltage stress and reduced total harmonic distortion (THD), therefore, making it a better choice for ac–dc conversion stage in battery charging application. The dc–dc converter furnishes regulated and wide output voltage range for on-board charging system. The principle of operation, modulation technique and control strategy for both the converters are analysed. Following theoretical analysis, laboratory experiments were conducted to validate the implemented approach. The results signify that for output voltage range of 24−72 V, UPF is maintained at input, lower stress across switches and capacitor voltage is balanced. The performance of MLC is satisfactory as it attains a peak efficiency of 97% with THD of 2.07%. [ABSTRACT FROM AUTHOR]

Power-domain NOMA can enlarge the spectrum efficiency and capacity via serving multiple users in the same time slot. Up to now, there are still some issues to be addressed in the NOMA system with multiple users: how many users the NOMA system can accommodate with limited power, how to mitigate the interference among the users, what's the achievable bound of capacity with limited power at the base station, and how to tackle with two or more users having similar distances to the base station. In the paper, the approximated CPM capacity in the NOMA system over Rayleigh channel is derived. Then, an adaptive user-clustering is proposed in downlink NOMA system, such that the achievable sum-rate will get high enough. Moreover, the optimal allocation of power for each user in each cluster is derived and evaluated. In the end, the performances such as outage probability, capacity, peak-to-average power ratio (PAPR), and bit error ratio (BER) are simulated as comparison. [ABSTRACT FROM AUTHOR]

This paper analyses the effect of temperature variations on the device performance of a ground plane junctionless tunnel field effect transistor (GP-JLTFET) with a high-K gate stack. Ground plane screens the electric field at the drain interface, which results in a higher effective channel length. This leads to highly suppressed ambipolarity and enhancement of the drive current. The junctionless device structure reduces the complexity of high-temperature doping processes as well. As high- κ gate oxide and metal gate are incorporated, this also aids in increasing the gate controllability and reduced leakage. As the tunnelling mechanism is temperature-dependent, hence, for investigating the feasibility of device application at elevated temperature, these temperature variation effects need to be analysed in depth. The primary goal of this investigation is to analyse the device dc performance parameters like drain current characteristics and subthreshold slope (SS), threshold voltage ( V T h ), I O N and I O N / I O F F ratio. Furthermore, the impact of temperature on analogue/RF figures of merit has also been analysed in detail here. [ABSTRACT FROM AUTHOR]