Simulation-based analysis of an L-patterned negative-capacitance dual tunnel VTFET.

This paper investigates the design and analog the behaviour of an L-Patterned Negative-Capacitance Dual Tunneling Vertical TFET (L-NC-DT-VTFET) device with the idea of corner tunnelling and vertical tunnelling. In this proposed structure, the tunnel junction can be used over a large region in a perpendicular alignment to the channel direction. Furthermore, the gate of an L-NC-DT-VTFET is positioned vertically in the L-shaped to boost ON current. Moreover, adding the p+ pocket in the channel helps reduce ambipolar current and improves the ON current. By adjusting the thicknesses of the ferroelectric layer and pocket, the device design is created deliberately to improve the on current to off current ratio $${{({I_{ON}}} \mathord{\left/ {\vphantom {{({I_{ON}}} {{I_{OFF}}}}} \right. \kern-\nulldelimiterspace} {{I_{OFF}}}})$$ (I O N / I O F F ). The tunnelling current generated by dual tunnelling and negative capacitance extricates the collected holes, minimising the kink effect. The characteristics of the proposed L-NC-DT-VTFET structure are examined to those of known TFET architectures, and the suggested design appears to be a better match for high-performance, low-power applications as the device design maximise vertical tunnelling over corner tunnelling. [ABSTRACT FROM AUTHOR]