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This paper proposes a La/ultrathin TiSi x metallic bilayer contact (MBC) on moderately doped n+-Si, which can simultaneously reduce contact resistivity ( $\rho _{c}$ ) and at the same time improve the contact thermal endurance. In such an MBC, the top La defines the work function (WF), whereas the ultrathin (~1 nm) TiSi x (WF-transparent) interlayer acts as a Si-diffusion barrier and improves the thermal endurance of the whole contact. Moreover, incorporation of oxygen (O) into MBC further improves the contact performance. On n+-Si with a donor concentration of $\textsf {1} \times \textsf {10}^{\textsf {19}}$ cm−3, an O-incorporated MBC can achieve an $18.3\times $ and $2.2\times $ reduction in $\rho _{c}$ as compared with Ti/n+-Si and La/n+-Si references, respectively.

This paper reports ultralow contact resistivities ( $\rho _{c})$ achieved on highly doped p-SiGe with two low-temperature contact formation methods. One method combines precontact amorphization implantation with ~500 °C rapid thermal processing (RTP)-based Ti germano-silicidation; $\rho _{c}$ achieved was $\sim 2.9\times 10^{-9}~\Omega \cdot $ cm2. The other method combines codeposited TiSi—Ti:Si =1:1—with ~450 °C RTP-based Ti silicidation; $\rho _{c}$ achieved was $\sim 1.7\times 10^{-9}~\Omega \cdot $ cm2. When $\rho _{c}$ reaches minimum, the TiSi(Ge) alloy is generally amorphous with embedded small crystallites, similar to the previous observations on pure Si substrates.

Epitaxial In x Ga1– x As is grown by metal organic vapor phase epitaxy as replacement of polycrystalline silicon (Si) channel for high-density 3-D NAND memory applications. The most challenging steps to integrate In x Ga1– x As are thoroughly discussed; their impact on the electrical performances are investigated and the tunnel oxide (TuOx) quality is assessed. In x Ga1– x As channels with a diameter down to ~45 nm and different In concentrations are obtained after using two alternative surface preparation routes: HCl and Cl2. Thanks to the lower thermal budget involved, Cl2 seems the most suitable route to preserve the thickness of the TuOx. In x Ga1– x As channels with In concentration, x, higher than 0.45 have superior conduction properties compared with poly-Si channel, showing higher $I_{\mathrm { {on}}}$ and transconductance.

In recent CMOS technology, extreme shrinking of contact area at source/drain regions raises serious concerns of high metal/semiconductor contact resistance. Confronting this problem, we introduce a precontact amorphization implantation plus Ti silicidation technique (PCAI + TiSi x ) and achieve ultralow contact resistivity ( $\rho _{c}$ ) of (1.3 – 1.5) $\times 10^{-9} ~\Omega \cdot \text {cm}^{2}$ on Si:P. This PCAI + TiSi x technique utilizes light amorphization (low-energy implantation), thin Ti and TiSi x film, and moderate thermal budget (500 °C –550 °C): these features are compatible with modern CMOS manufacturing. Moreover, the PCAI + TiSi x -induced $\rho _{c}$ reduction is proved universal on both n- and p-Si. With additional characterizations, we find that the silicidation-induced $\rho _{c}$ variation is not merely a Schottky barrier height tuning effect. The electrical and physical characterizations suggest that the low $\rho _{c}$ is strongly correlated with the formation of interfacial TiSi x crystallites between amorphous TiSi alloy and Si.

This work discusses the thermal stability of metal-insulator-semiconductor (MIS) contacts. A case study is performed on a typical low-Schottky barrier height ( $q\varphi _{b})$ MIS contact: Ti/TiO2/n-Si. By incorporating different levels of donor concentration in n-Si, we perform a systematic Ti/TiO2/n-Si thermal stability study under different electron conduction mechanisms. We find that both $q\varphi _{b}$ and contact resistivity ( $\rho _{c})$ of the Ti/TiO2/n-Si MIS contacts vary dramatically after mere 300 °C–500 °C 1-min rapid thermal treatments. The variations in $q\varphi _{b}$ and $\rho _{c}$ are related to the thermally driven TiO2 decomposition. This thermal stability study of Ti/TiO2/n-Si reveals a general concern for the MIS contact application: since the MIS contacts on n-type semiconductor generally utilize a reactive low-work function metal and an ultrathin insulator, it is difficult to maintain their interface quality considering the thermal budget in standard manufacturing of integrated circuits. Possible solutions to this MIS thermal stability issue are discussed.

In this paper, we compare the performances of FinFETs, lateral gate-all-around (GAA) FETs, and vertical GAAFETs (VFETs) at 7-nm node dimensions and beyond. Comparison is done at ring oscillator level accounting not only for front-end of line devices but also for interconnects. It is demonstrated that FinFETs fail to maintain the performance at scaled dimensions, while VFETs demonstrate good scalability and eventually outperform lateral devices both in speed and power consumption. Lateral GAAFETs show better scalability with respect to FinFETs but still consume 35% more energy per switch than VFETs if made under 5-nm node design rules.

As a result of CMOS scaling, the critical dimension (CD) of integrated circuits has been shrinking. At sub-45 nm nodes, in which FinFET is a viable device architecture, line-edge roughness (LER) in current Si-based technologies forms a significant fraction of the line CD. In such cases, analyzing the impact of LER on FinFET performance is vital for meeting various device specifications. The impact of LER on the matching performance of FinFETs is investigated through statistical device simulations, comparing the relative importance of fin- and gate-LER. Fin-LER is shown to significantly degrade FinFET matching performance under DC and transient operations. Combining our device simulation results with experimental data, it is shown that fin-LER will dominate the intra-bit-cell stochastic mismatch in FinFET static random access memories at the LSTP-32-nm node. The electrical performance of spacer-defined fin (SDF) and resist-defined fin (RDF) patterning technologies has been compared. It is shown that, with respect to RDF patterning, the spacer-defined process has the potential to improve FinFET matching performance by 90%.

The tunnel field-effect transistor (TFET) is a promising candidate to replace the metal-oxide-semiconductor field-effect transistor in advanced technology nodes, because of its potential to obtain sub-60 mV/dec subthreshold swings. However, it is challenging to reach sufficiently high on-currents in TFETs. Therefore, on-current boosters are actively being researched. In this paper, a p-n-i-n TFET, containing a vertical pocket at the source-channel junction, is studied with quantum mechanical simulations and compared with a line tunneling TFET, containing horizontal pockets in the source region. The comparison is carried out both for all-Si and all-Ge, while an extrapolation is made for smaller bandgap materials. The p-n-i-n TFET is found to perform better than a p-i-n configuration, thanks to the increased electric field at the source-pocket junction. Compared to the p-n-i-n TFET, the line TFET has an even higher on-current and lower subthreshold swing, attributed to the closer proximity of the tunnel junction to the gate. For the all-Ge case, the difference between the two configurations is found to decrease when direct transitions are taken into account semi-classically.

The optimized tunnel field-effect transistor with a gate electrode overlapping the source region exhibits a steeper subthreshold swing (SS) and a higher on-state tunneling current than the transistor with a gate on the channel only. In the presence of a counterdoped pocket in the source region underneath the gate electrode, the vertical tunneling component dominates over the unwanted lateral tunneling component, and the performance variability is reduced compared to its no-pocket configuration. The optimal pocket thickness, which is a tradeoff between realistic gate work function and the desired SS, is dependent on the bandgap, electron or hole effective mass, permittivity, and tunneling orientation of semiconductor materials, as analyzed in detail in this paper. A numerical procedure is provided to determine the optimal pocket thickness for arbitrary semiconductor materials.

A technique is presented to study the electrostatic degradation of key germanium metal-oxide-semiconductor field-effect transistor (MOSFET) performance metrics such as the subthreshold slope SS, the drive current, and the off-state current. This is calculated using the superposition of the contributions from individual trap profiles, arising from a piecewise approximation of any arbitrary interface-trap spectrum. A technology computer-aided design simulation using this approach has been directly applied to the electrical evaluation of various scaled Ge p-channel FETs with different passivation schemes. The relative SS degradation due to interface traps is shown to be independent of the gate length, even in scaled devices exhibiting short-channel effects. Additionally, a linear dependence of the relative degradation with an equivalent oxide thickness (EOT) is observed. As such, a transistor's subthreshold performance is less impacted by a given concentration of interface traps, as the EOT is further reduced. Finally, the MOSFET drive current is shown to be degraded due to interface traps, mainly through additional scattering in the channel, while the electrostatic effect is rather small.

A commercial technology computer-aided design device simulator was extended to allow electrical simulations of sub-100-nm germanium pMOSFETs. Parameters for generation/recombination mechanisms (Shockley-Read-Hall, trap-assisted tunneling, and band-to-band tunneling) and mobility models (impurity scattering and mobility reduction at high lateral and transversal field) are provided. The simulations were found to correspond well with the experimental I- V data on our Ge transistors at gate lengths down to 70 nm and various bias conditions. The effect of changes in halo dose and extension energies is discussed, illustrating that the set of models presented in this paper can prove useful to optimize and predict the performance of new Ge-based devices.

The continuous reduction of the dimensions of floating-gate-based nonvolatile memories brings the necessity of substituting the current dielectrics with materials of higher dielectric constant (high- k dielectrics). However, most of the high- k materials studied show a large number of electrically active defects, which mitigates their benefit. The study of these defects, or traps, is necessary in order to fully understand the electrical properties of high-k materials. In this paper, the recently introduced two-pulse capacitance-voltage characterization technique is used, together with a newly developed physics-based model, in order to extract the space and energy location of the traps throughout the high-k dielectrics in advanced memories. An accurate agreement between measurements and simulations is achieved. For the first time, it is shown that traps located in the top part of the bandgap of the high-k materials can be probed and their location in space and energy, as well as their density, can be accurately determined.

Three-dimensional ICs provide a promising option to build high-performance compact SoCs by stacking one or more chips vertically. Through silicon vias (TSVs) form an integral component of the 3-D IC technology by enabling vertical interconnections in 3-D ICs. TSV resistance, inductance, and capacitance need to be modeled to determine their impact on the performance of a 3-D circuit. In this paper, the RLC parameters of the TSV are modeled as a function of physical parameters and material characteristics. Models are validated with the numerical simulators like Raphael and Sdevice and with experimental measurements. The TSV RLC model is applied to predict the resistance, inductance, and capacitances of small-geometry TSV architectures. Finally, this paper also proposes a simplified lumped TSV model that can be used to simulate 3-D circuits.

This paper is the first to quantify drain extension leakage in a sub-100-nm gate-length bulk germanium technology. Leakage through the transistor's extension/halo junction is shown to be the dominant leakage component in a scaled transistor layout. Optimizing halo and extension implants to improve short-channel control further increases the extension leakage. As a consequence, drain-to-bulk leakage in Ge pFETs is likely 4 times 10-7 A/mum or higher for an LG = 70-nm pMOS technology with good short-channel control at a supply voltage of 1 V. The weak thermal sensitivity of the extension leakage points to a band-to-band tunneling (BTBT) mechanism, which leads to only 40%-50% increase of the extension leakage between 25degC and 100degC. As BTBT depends exponentially on the electric field across the junction, lowering the supply voltage below 0.7 V can lead to drain leakages below 1 times 10-7 A/mum.

We present a simulation study on the effect of the gate module on the channel stress in Si1-xGex and Si1-yCy S/D MOS transistors. Stiff gate materials, such as titanium nitride, lead to a decreased channel stress, while a replacement-gate scheme allows the increase of the effectiveness of the Si1-xGex and Si1-yCy S/D techniques significantly, independent of the gate material used. The drawback of using a replacement gate is that the channel stress becomes more sensitive to layout variations. In terms of effect on Si1-xGex/Si1-yCy S/D stress generation, using a thin metal gate capped by polysilicon is similar to a full metal gate if the thin metal gate thickness exceeds 10 nm. Even metal gates as thin as 1 nm have a clear influence on the stress generation by Si1-xGex/Si1-yCy S/D. Removing and redepositing the polysilicon layer while leaving the underlying metal gate unchanged increases the stress, although not to the same extent as for complete gate removal. A simple analytical model that estimates the stress in nested short-channel Si1-xGex and Si1-yCy S/D transistors is presented. This model includes the effect of germanium/carbon concentration, active-area length, as well as the effect of gate length and the Young's modulus of the gate. Good qualitative agreement with 2-D finite element modeling is demonstrated.

This paper presents an analysis of junction leakage in heavily doped p+/n germanium junctions, targeted for short-channel transistor fabrication. There exists an optimal p+/n junction condition, with a doping concentration of 1 times 1017-5 times 1017 cm-3, where the area-leakage-current density is minimal. Use of a halo-implant condition optimized for our 125-nm gate-length pMOS devices shows less than one decade higher area leakage than the optimal p+/n junction. For even higher doping levels, the leakage density increases strongly. Therefore, careful optimization of p+/n junctions is needed for decananometer germanium transistors. The junction leakage shows good agreement with electrical simulations, although for some implant conditions, more adequate implant models are required. Finally, it is shown that the area-junction static-power consumption for the best junctions remains below the power-density specifications for high-performance applications.

Among the novel methods for flatband voltage (Vfb) measurement, we demonstrate that a gate-leakage-based technique is the most suitable for measuring Vfb in floating-body MOSFETs with ultrathin gate dielectrics. Starting from carrier separation experiments on planar MOSFETs, we show the universality of the gate conduction mechanism dependence on band alignment for both n- and p-FETs. We demonstrate that metrics based on the gate leakage (either its valence-band electron-tunneling component or its first-order derivative) reflect this dependence and allow equivalent-oxide-thickness-independent Vfb quantification. This dependence is also valid for high-k and capped gate dielectrics, whereas their gate conduction mechanism is dominated by direct tunneling. To illustrate, we extract gate-leakage-derivative-based metrics and measure Vfb of TaN and TiN gate electrodes in multiple-fin FETs integrated on silicon-on-insulator.

When comparing the extracted carrier mobility of long- and short-channel transistors, special consideration must be given to the metallurgical gate length (Lmet), neglecting the impact of source and drain junction profiles. Lmet can be identified with nanometer precision by using RF split-C-V measurements, and physical and electrical analysis can demonstrate the accuracy of the method. Another important parameter, the external transistor resistance (Rsd), can be identified with linear current measurements of short-channel devices. However, it is important to quantify the mobility dependence from the gate length in order to obtain an accurate result. A method to estimate the electrical field (Eeff) of short-channel devices is proposed. The extracted short-channel mobility shows a universal behavior identical to the classical long-channel one.

Data retention loss mechanisms in nitride-based localized trapping memory devices are investigated with various electrical measurements and Medici simulations. First, the effect of program and erase cycles on device behavior is determined in terms of bottom oxide degradation and nitride charge profile evolution. Even if a strong degradation of the interface is observed, there is no important impact of this degradation on the cell behavior. However, the nitride charge profile evolves with cycling and leads to a three-pole electron-hole-electron profile over the channel region. Second, the interface trap annealing, the tunneling through the bottom oxide, and the lateral redistribution are studied in order to determine which mechanism plays the main role in the threshold voltage shift after cycling. The retention performance is dominated by a lateral redistribution of charges in the nitride layer.

This paper presents a study on the effectiveness of strained contact-etch-stop-layer (CESL) technologies in aggressively scaled dense structures. The focus is on nested transistors, which is a technologically very important structure that consists of a chain of gates on one active area. It will be shown that the two main channel stress components introduced by CESL, which are the vertical and parallel stresses, have a different sensitivity toward layout variations, which accordingly leads to different scaling guidelines to obtain a layout-insensitive strained CESL technology. Decreasing the CESL thickness is not enough for technology scaling; also, adapting the spacer dimensions is indispensable to scale a strained CESL technology from one technology node to the next.

A study on using a novel metal gate-the Ni fully GermanoSilicide (FUGESI)-in pMOSFETs is presented. Using HfSiON high-/spl kappa/ gate dielectrics and comparing to Ni fully Silicide (FUSI) devices, this paper demonstrates that the addition of Ge in poly-Si gate (with Ge/(Si+Ge)/spl sim/50%) results in: 1) an increase of the effective work function by /spl sim/ 210 mV due to Fermi-level unpinning effect; 2) an improved channel interface; 3) a reduced gate leakage; and 4) the superior negative bias temperature instability characteristics. Low-frequency noise measurement reveals a decreased 1/f and generation-recombination noise in FUGESI devices compared to FUSI devices, which is attributed to the reduced oxygen vacancies (V/sub o/)-related defects in the HfSiON dielectrics in FUGESI devices. The reduced V/sub o/-related defects stemming from Ge at FUGESI /HfSiON interface are correlated with the Fermi-level unpinning effect and the improved electrical characteristics observed in FUGESI devices.

The impact of different processing factors on the low-frequency (LF) noise of nMOSFETs fabricated in strained-silicon (SSi) substrates will be described. It is shown that the use of an SSi substrate can yield improved LF noise performance compared with standard Czochralski silicon material. This is demonstrated for both full-wafer and selective epitaxial SSi material. The lower 1/f noise points to an improved gate oxide quality, i.e., with a lower interface and bulk defect density, and is correlated with the low-field mobility or transconductance of the transistors. At the same time, it will be demonstrated that there exist defect-related LF noise mechanisms, which generally give rise to excess generation-recombination (GR) noise. Associated with this GR noise, a degradation of either the OFF-state leakage current or the mobility (transconductance) of the devices is observed. It is clear that noise is a sensitive parameter to local defectiveness and may be a useful tool for both materials' characterization and the analysis of processing-related device degradation mechanisms.

We discuss the inverted MOS structure with extremely thin oxides as a quasi-bound-state system. Its energy subbands can be regarded as resonances of a quantum mechanical system with a continuum of eigenstates. We derive an analytical calculation to extract the defining parameters of the Lorentzian peaks associated with the relative probability of localizing an electron in the confining potential region at the Si/dielectric interface and propose an algorithm that allows to estimate the energy levels and the lifetimes of these states, provided the solution of the approximate bound state system is known. This new method has the advantage of not being affected by computational errors, avoiding the time consuming scanning procedure usually employed in previously reported works. Furthermore, a comparison with semiclassical calculation of the lifetimes is performed and direct tunneling current is calculated, which allows it to fit experimental gate-leakage curves with high accuracy.

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).

The low-frequency noise of partially depleted silicon-on-insulator (SOI) MOSFETs is studied in the ohmic regime. In the frequency range 0.7 Hz /spl les/ f /spl les/ 50 Hz, a power spectral density is observed which follows a 1/f/sup n/ law, with n /spl sim/ 1.7 for a broad range of operation conditions. This noise is to be distinguished from the usual 1/f-like noise, occurring at higher frequency for devices with a length smaller than 1 /spl mu/m. From the dependence on the gate voltage and device length, it is concluded that the 1/f/sup 1.7/ noise is of the McWhorter type and, therefore, is generated by carrier exchange between the front channel and traps in the 2.5 nm NO gate oxide. This type of noise is absent in the back-channel or in the gate current. A model will be presented, from which it is derived that the responsible traps are most likely associated with the polysilicon gate/oxide interface and, furthermore, show a steep concentration profile over a small depth range. A similar noise behavior is observed in bulk devices with thin gate dielectrics.

The exact solution of the two-dimensional (2-D) Poisson's equation has been analytically derived for fully-depleted (FD) SOI MOSFETs with Halos or pockets. The approach uses a three-zone Green's function solution technique. Explicit equations for the 2-D electrical potential as well as for both front- and back-side threshold voltages have been derived. The accuracy of the equations has been verified by a 2-D numerical device simulator. From the presented results, it can be concluded that the analytically derived model for the electric potential and threshold voltages are in good agreement with 2-D numerical simulation data.

Off-state leakage currents have been investigated for sub-100 nm CMOS technology. The two leakage mechanisms investigated in this work include conventional off-state leakage due to short channel effects and gate leakage through ultrathin gate oxides. The conventional off-state leakage due to short channel effects exhibited the similar characteristics as previously published; however, gate leakage introduces two significant consequences with respect to off-state power consumption: (1) an increase in the number of transistors contributing to the total off-state power consumption of the chip and (2) an increase in the conventional off-state current due to gate leakage near the drain region of the device. Using experimentally measured data, it is estimated that gate leakage does not exceed the off-state specifications of the National Technology Roadmap for Semiconductors for gate oxides as thin as 1.4 to 1.5 nm for high performance CMOS. Low power and memory applications may be limited to an oxide thickness of 1.8 to 2.0 nm in order to minimize the off-state power consumption and maintain an acceptable level of charge retention. The analysis in this work suggests that reliability will probably limit silicon oxide scaling for high performance applications whereas gate leakage will limit gate oxide scaling for low power and memory applications.

In this paper, we report on the reverse short channel effect (RSCE) in vertical heterojunction MOSFET's, which use a source/channel heterojunction for reduction of the short channel effect (SCE) in deep submicron devices. The study shows that a typical RSCE will occur when the heterobarrier dominates the channel potential and when the barrier is strong enough to shift the potential maximum (pMOS) or minimum (nMOS) toward the source/channel interface. The particular channel potential for these devices will give rise to a current-voltage (I-V) behavior which deviates from the classical linear or saturation regime for homojunction devices. A distinctive "transition zone" needs to be taken into account.

Analytical modeling of the threshold voltage of a Si/sub 1-x/Ge/sub x//Si heterojunction pMOSFET has been performed using a quasi-two-dimensional (quasi-2-D) approach for the calculation of the potential. It is shown that the use of Si/sub 1-x/Ge/sub x/ in the source region leads to an improvement in the short-channel behavior of deep submicron pMOSFETs. The V/sub T/ roll-off can be substantially decreased by introducing a material dependent barrier between source and channel. Furthermore it will be proven that this advantage will become stronger when channel lengths are decreased toward the deep submicron regime.