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2. Lifetime measurements in Ti-52,Ti-54 to study shell evolution toward N=32

3. Lifetime measurements in Ti-52,Ti-54 to study shell evolution toward N=32

4. Lifetime measurements in Ti 52,54 to study shell evolution toward N=32

6. Biodiversité dans l'estuaire de la Loire, quels enjeux ?

7. Steatosis, Glycation and Liver Fibrosis in Patients with Diabetes

8. Life at cold seeps: a synthesis of biogeochemical and ecological data from Kazan mud volcano, eastern Mediterranean Sea

9. The CD metrology perspectives and future trends

10. Impact of UV light on photoresist pattern linewidth roughness during gate etch processes

11. Plasma etching processes for future electronic devices

12. Gate Stack Patterning: challenges of the future

13. Plasma impact on 193nm Photoresist LWR

14. Impact of Plasma etching Processes on193nm Photoresists: Etch resistance and Linewidth roughness

15. Seafloor geological studies of active gas chimneys offshore Egypt (central Nile Fan)

16. Plasma etching challenges involved in gate stack patterning for 45 nm technological nodes and beyond

17. The CD-AFM technique as a mean to accelerate advanced process developpement for the 45 nm Node and beyond

18. Towards a better understanding of the mechanisms involved in the HBr cure plasma treatments

19. Plasma impact on ArF resist line ege roughness

20. Full 8' printed wafer 3D resist characterizations by Critical Dimension Atomic Force Microscopy

21. Process for making a gate for a short channel CMOS transistor structure

22. Nanometer scale linewidth control during etching of polysilicon gates in high density plasmas

23. Challenges in plasma etching for Nanoelectronics applications

24. Chemical topography analysis of silicon gates etched in HBr/Cl2/O2 and HBr/Cl2/O2/CF4 high density plasmas

25. Nanometer scale linewidth control during etching of polysilicon gtes in high density plasmas

26. Gate patterning for ultimate CMOS devices

27. Gate patterning for ultimate CMOS device fabrication

28. Resist transformation under high density plasma exposure

29. Silicon gate notching for patterning features with dimensions smaller than the resolution of lithography

30. Plasma etching processes for sub 50 nm Ultra Large Scale Integration technology

31. Resist trimming and silicon gate notching for patterning features with dimensions smaller than the resolution of the lithography

32. Manufacturing viability of the 'notched gate' process for sub-0.1µm technologies

33. Silicon gate etching: critical dimension control, technology and strategy for future CMOS devices

34. Chemical topography analysis using XPS during plasma etching in Si processing

35. Plasma etching of nano-scale feature in Silicon : application to ultimate CMOS gates and quantum nanowires

36. Fundamental limitations in the design of front end and back end plasma etch processes

37. Mass spectrometry as tool for plasma etching charactérization

38. High density plasma etching of Low K Dielectric Materials

39. The mechanisms of anisotropy control in plasma etching processes

40. Gate engineering for sub 50 nm CMOS devices

41. Analysis of the sidewall passivation layer formation mechanisms during plasma etching by Mass Spectrometry and XPS diagnostics

42. Recent warming of deep sea sediments in the Eastern Mediterranean

43. Campagne Seapso 4: Etude morphostructurale de la ride de Valufa dans le bassin de Lau

44. Campagne Pop 1: Processus d'extension dans le bassin arriere arc d'Okinawa

46. Exploration of ultimate gate patterning technologies: lithography and plasma etching

48. Lifetime measurements in Ti 52 , 54 to study shell evolution toward N = 32

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