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The methodology of mobility extraction from the Y-function or from the transconductance peak is revisited in the context of silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs). Based on a simple two-channel model, we discuss the biasing conditions that enable the Y-function to be applied to both single-gate (SG) and double-gate (DG) modes. Systematic mobility measurements in thick and ultrathin SOI transistors are presented for the front channel, back channel, and in quasi-double-gate mode. In SG-mode, the mobility is overestimated as soon as the opposite channel is activated. In partially depleted or relatively thick, fully depleted MOSFETs, the two channels are separated; hence, the total apparent mobility in DG mode is the sum of the front and back channel mobilities. By contrast, the two-channel model fails in ultrathin transistors, where the two channels become strongly coupled and volume inversion occurs. Volume inversion is reflected in a remarkable increase of the apparent mobility in DG mode. [ABSTRACT FROM AUTHOR]

Presents a study that examined the electrical structure properties of structure fabricated on silicon-on-insulator material formed by deep oxygenation implantation. Background on carrier-transport properties; Analysis of oxygen-related donors; Investigation of interface properties.

Presents a study which determined the non-homogeneous distribution of the carrier transport properties in silicon-on-insulator thin films synthesized by oxygen implantation. Use of gate-controlled p-type Hall devices; Determination of transport profiles based on metal oxide semiconductor (MOS) field effect; Channel resistance variation with gate voltage; Vertical profile of the MOS-hall device.

Investigates the high-magnetic-field and low-temperature properties of separation by implantation of oxygen (SIMOX) transistors. Characteristics of the SIMOX metal-oxide-semiconductor field-effect transistors; Analysis of single-interface Shubnikov-de-Haas (SDH) oscillations and parasitic series resistance effects; Consequences of the interface coupling on SDH oscillations.

The band-modulation and sharp-switching mechanisms in Z 2 -FET device operated as a capacitorless 1T-DRAM memory are reviewed. The main parameters that govern the memory performance are discussed based on detailed experiments and simulations. This 1T-DRAM memory does not suffer from super-coupling effect and can be integrated in sub-10 nm thick SOI films. It offers low leakage current, high current margin, long retention, low operating voltage especially for programming, and high speed. The Z 2 -FET is suitable for embedded memory applications. [ABSTRACT FROM AUTHOR]

• A novel configuration of junctionless MOSFET is proposed showing superior performance. The core–shell structure brings fundamental advantages to junctionless (JL) MOSFETs. The addition of an undoped shell to a heavily doped core enables normally-off operation, high charge, excellent mobility, and very high current drive. The demerits of a classical JL transistor, such as poor mobility, negative threshold voltage and random dopant fluctuations (RDF), are eliminated while its attractive properties are maintained. [ABSTRACT FROM AUTHOR]

Abstract: Even in fully-depleted (FD) SOI MOSFETs, the floating-body potential variations may lead to strong transient effects on the current characteristics. A physics-based model, enabling the fast computing of the potential variation with time, is proposed in this paper. The model is validated, for a wide range of technological parameters and biases, by 2D numerical simulations. This model reproduces the experimental data and clarifies the physics mechanisms responsible for the transient variations of gate and drain currents. Relevant applications in the field of EEPROM and capacitorless floating-body DRAM memories are addressed. [Copyright &y& Elsevier]

Abstract: The gate-induced floating-body effect GIFBE) in triple-gate FETs is systematically investigated as a function of fin width and back-gate bias. GIFBE is due to body charging by the gate tunneling current and gives rise to a second peak in the transconductance. It occurs even in fully depleted (FD) devices, when the back-gate is driven from depletion to accumulation. It is found that the front-gate still maintains FD characteristics even though the GIFBE appears. GIFBE strongly decreases in narrow fins where the fringing field between the lateral gates prevents the back interface to reach accumulation. We show that GIFBE also depends on delay time and drain voltage. [Copyright &y& Elsevier]

Abstract: Scaling considerations of conventional DRAMs lead to recent developments of capacitor-less, single-transistor (1T) DRAM based on the floating-body effects in SOI transistors. Several options (Z-RAM and TTRAM) are reviewed and discussed in terms of operation mechanisms, performance and scaling. We also describe a new concept of 1T-DRAM (named MSDRAM) simple to fabricate, program and read. Its basic mechanism is the meta-stable dip (MSD) hysteresis effect which takes advantage of the coupling between front and back interfaces in SOI transistors. Systematic measurements show that MSDRAMs are suitable for low-power applications as they exhibit negligible off-state current, long retention time and scalability. [Copyright &y& Elsevier]

Abstract: A standard characterization method in fully depleted SOI devices consists in biasing the back interface in the accumulation regime, and measuring the front-channel properties. In ultra thin body device however, it is sometimes no longer possible to achieve such an accumulation regime at the back interface. This unusual effect is investigated by detailed simulations and analytical modelling of the potential and electron/hole concentrations. The enhancement of the interface coupling effect in ultra thin body devices, called super-coupling, can explain previously published experimental data [Pretet J, Ohata A, Dieudonne F, Allibert F, Bresson N, Matsumoto T, et al. Scaling issues for advanced SOI devices: gate oxide tunneling, thin buried oxide, and ultra-thin films. In: 7th International symposium silicon nitride and silicon dioxide thin insulating films, Paris, France, 2003. Electrochemical Society Proceedings, vol. 2003-02, Pennington (USA); 2003. p. 476–87], and reveals new challenges in the characterization of advanced SOI devices. [Copyright &y& Elsevier]

Abstract: The fully-depleted version of the SOI four-gate transistor (G4-FET) is introduced and its characteristics are systematically investigated. It is shown that the thinning-down of the silicon film promotes vertical coupling between the front and the back gates while mitigating the horizontal coupling between the lateral gates. As a consequence the direct influence of the lateral junction-gates on the body potential distribution is reduced. However, by biasing the back interface in inversion the junction-gates can indirectly modulate the body potential. This provides a very efficient control of the front-channel conduction parameters – such as threshold voltage, subthreshold swing and transconductance – by the junction-gates regardless the device width. The experimental results are clarified by 3-D device simulations and analytical modelling. [Copyright &y& Elsevier]

Abstract: This paper presents a detailed investigation of short-channel effects in advanced partially depleted SOI NMOSFETs. The influence of the back-gate voltage on the threshold voltage reveals the increase of the coupling effect with the channel length. The channel length impact is reversed by using pocket implants. Then SOI devices from the same wafer can behave as fully or partially depleted according to the channel length. This effective doping mechanism is amplified at low temperature operation. Systematic measurements show that long channel transistors become fully depleted before short channels, in particular when decreasing the temperature. The reduction of the channel length or the increase of the back-gate voltage and temperature attenuate the gate-induced floating body effect. [Copyright &y& Elsevier]

Abstract: The inter-gate coupling effects in multiple-gate SOI devices with Omega configuration, metal gate and HfO2 dielectric are investigated. Electrical measurements together with 3D numerical simulations show that the back-gate influence is reduced for narrow devices due to a strong lateral coupling between the two lateral sides of the main gate. In spite of the full depletion of the transistor body, the threshold voltage and the subthreshold slope are no longer dependent on the back gate bias. It is also shown that the conduction channels can be separated in wide ΩFETs using the back-gate coupling in accumulation mode. DIVSB (drain-induced virtual substrate biasing) can be drastically reduced when the lateral coupling screens the drain influence. Narrow devices are then virtually immune to substrate effects. [Copyright &y& Elsevier]

Abstract: We demonstrate that the transconductance and drain current of fully depleted MOSFETs can display an interesting time-dependent hysteresis. This new memory effect, called meta-stable dip (MSD), is mainly due to the long carrier generation lifetime in the silicon film. Our parametric analysis shows that the memory window can be adjusted in view of practical applications. Various measurement conditions and devices with different doping, front oxide and silicon film thicknesses are systematically explored. The MSD effect can be generalized to several fully depleted CMOS technologies. The MSD mechanism is discussed and validated by two-dimensional simulations results. [Copyright &y& Elsevier]

Abstract: SOI circuits exhibit excellent performance and scalability but suffer from self-heating. Systematical 2D simulations demonstrate that the thermal dissipation in SOI MOSFETs can be improved dramatically by replacing the buried oxide with high thermal conductance insulators. The self-heating can be reduced by as much as 50–100°C. Yet, these materials feature high-K dielectric constant, which also affects the electrical properties: more severe short-channel effects, parasitic capacitances and drain-to-body fringing fields. The conciliation between the thermal and electrical properties of advanced SOI MOSFETs (50nm long, 10nm thick) is examined by comparing different SOI materials (air, SiO2, diamond, AlN, Al2O3, SiC) and MOS architectures. We demonstrate the advantage of a ground plane (GP) located under the buried insulator (BOX). Diamond is excellent candidate for relatively thick BOX whereas Al2O3 and SiC are suitable for ultra-thin BOX. These novel structures can be fabricated by wafer bonding technology. [Copyright &y& Elsevier]

Abstract: The coupling effect between the front and back channels in thin SOI MOSFETs is investigated. Comparing the results in long channel and short channel, it was found that, in the short channel, series resistance affects the transconductance curve, impacts the coupling effect and complicates the distinction between the front and back channels. This fact was also confirmed by the device simulation. Furthermore, the difficulty to separate the two channels, on the electrical characteristic of multiple-gate structures, is discussed. [Copyright &y& Elsevier]

SOI circuits exhibit excellent performance and scalability but suffer from self-heating. This critical problem is systematically analyzed by using an equivalent thermal circuit and 2-D simulations. We demonstrate that the thermal dissipation and self-heating in SOI MOSFETs can dramatically be improved by modifying the generic SOI structure: replacement of the buried oxide with buried alumina. However, alumina is a high-K dielectric which also affects the electrical properties: the drain-to-substrate fringing fields are enhanced, leading to more severe short-channel effects. The trade-off between the thermal and electrical performance of very advanced SOI transistors (10–100 nm long, 5–100 nm thick) is examined by comparing various SOI materials and MOS architectures. The optimum solution consists of a ground plane located underneath a relatively thin buried alumina. [Copyright &y& Elsevier]

Novel Unibond wafers, with very thin film and buried oxide, are probed with the pseudo-MOSFET method. It is shown that the method is still efficient at high temperature and for ultra-thin (10 nm) films. The threshold and flat-band voltages increase in thinner films due to special effects that are revealed by numerical simulations. [Copyright &y& Elsevier]

The operation and degradation mechanisms in silicon on insulator LD-MOSFETs are governed by the series resistance which is back-gate bias dependent. The influence of the back-gate bias during degradation and subsequent testing is investigated and modeled. The damage formation and overall loss in LD-MOSFETs performance induced by irradiation, hot-carrier injection, or low temperature are complex and remarkably different from the more usual case of low-voltage CMOS transistors. The series resistance can change by a factor of 4 according to the back-gate bias and radiation dose. The degradation processes are clearly identified and the main parameters (oxide charges, traps at the front and back interfaces, series resistances) are extracted using a simple model of the LD-MOSFET, which accounts for the modification of the drift region resistance. [Copyright &y& Elsevier]

We tentatively present possible architectures of Silicon On Insulator (SOI) transistors for the final stages of the scaling of silicon microelectronics. The scaling trends for conventional partially depleted and fully depleted SOI MOSFETs are critically examined. A ground plane can considerably attenuate short-channel effects. The manufacturability of extremely thin MOSFETs is demonstrated. Based on quantum calculations, we discuss the merits of double-gate transistors with volume inversion. [ABSTRACT FROM AUTHOR]

Abstract: We experimentally demonstrate a field-effect transistor with a single front gate built on fully-depleted silicon-on-insulator substrate that possesses extremely steep switching slope (≪1mV/decade) and gate-controllable hysteresis. The mechanism for the sharp switching, confirmed by simulations, involves the positive feedback between the gate-modulated charge injection barriers and the electron and hole components of the source–drain current. The transistor is named Z2-FET as it features zero impact ionization (unlike thyristors) and zero subthreshold swing. [Copyright &y& Elsevier]

The magnetoresistance technique has been introduced recently as a means of determining experimentally the mobility in bulk metal-oxide-semiconductor transistor and silicon-on-insulator devices. This technique does not require a precise determination of the channel length, and it also has the advantage of allowing mobility extraction when the application of other methods is problematic, notably with weak inversion and short device length. The magnetoresistance mobility extracted in this way is related but not identical to the normal effective drift mobility. In this work we simulate electron transport in the presence of a magnetic field for different device structures. The simulations allow us to study the conditions under which magnetoresistance mobility and effective mobility coincide, and to measure the difference, where it exists. We find that at low temperatures the two quantities coincide, while at room temperature a difference of more than 20% may appear. We take this to be a consequence of the energy difference between subbands and the resulting distribution of electrons among them. We then explain the fact that the two mobility measures coincide at low temperatures when only the ground subband is occupied by analyzing the energy dependence of the momentum relaxation time. [ABSTRACT FROM AUTHOR]

Presents a study that investigated the electrical properties of buried oxide-silicon interface. Information on the separation by implanted oxygen and deep level transient spectroscopy techniques; Experimental details; Results and discussion.

Low-frequency noise (LFN) measurements are largely used for interface quality characterization in MOSFETs. In this work, a detailed investigation of LFN technique applied to pseudo-MOSFETs in bare silicon-on-insulator (SOI) substrates is provided. A physical model capable to describe the experimental results is proposed and validated using different die areas and inter-probe distances. The effective silicon area contributing to the noise signal, the impact of defects induced by probes and the possibility to extract interface trap density are addressed. [ABSTRACT FROM AUTHOR]

Presents information on a study which investigated the carrier trapping properties in silicon on insulator material synthesized in deep oxygen implantation by photoinduced current transient spectroscopy. Methodology of the study; Results of the study; Conclusions.

We evaluate the Electro-Static Discharge (ESD) protection capability of BIpolar MOS (BIMOS) transistors integrated in ultrathin silicon film for 28 nm Fully Depleted SOI (FD-SOI) Ultra Thin Body and BOX (UTBB) high- k metal gate technology. Using as a reference our measurements in hybrid bulk-SOI structures, we extend the BIMOS design towards the ultrathin silicon film. Detailed study and pragmatic evaluations are done based on 3D TCAD simulation with standard physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope AVS method). These preliminary 3D TACD results are very encouraging in terms of ESD protection efficiency in advanced FD-SOI CMOS. [ABSTRACT FROM AUTHOR]

This paper investigates the ability of second harmonic generation (SHG) to probe the passivation quality of atomic layer deposited Al2O3 on Si by estimating the induced interface electric field due to fixed charges in the oxide. Samples with various oxide charges (Qox) and interface state densities (Dit) were fabricated, using different deposition parameters. The samples were characterized by capacitance-voltage (C-V) and microwave photoconductance decay measurements in order to evaluate Qox and Dit, as well as the effective minority carrier lifetime τeff. The SHG results were consistent with Qox, Dit, and τeff values, proving the ability of the technique to monitor the interfacial quality in a contactless and non-destructive way. Optical simulations which use the electric field values obtained from the C-V measurements could reproduce the measured SHG signal. This demonstrates that SHG coupled with optical simulation can give access to the electric field magnitude and thus characterize the electrical properties of oxide/Si interfaces. [ABSTRACT FROM AUTHOR]

The junctionless EZ-FET is a simple FDSOI-like device that requires only two lithography levels and standard processing steps. With its simplified architecture and fabrication flow, and using undoped source and drain terminals, the device allows for a fast electrical evaluation of semiconductor films on insulators (SOI) and gate stacks. This paper describes an electrical model that reproduces the peculiar transfer characteristics of a junctionless EZ-FET. The model is then simplified to develop a pragmatic parameter extraction methodology. This methodology is experimentally validated and provides the electrical properties of SOI films (mobility, threshold voltage) for both electrons and holes. [ABSTRACT FROM AUTHOR]

Abstract: Local Deep-Amorphization (DA) and subsequent Solid-Phase Epitaxial Regrowth (SPER) are envisioned for the co-integration of devices with hybrid surface orientation. The impact of these processes on the electrical characteristics of p-channel MOSFETs with 20nm thick film and HfO2 gate insulator/metal gate along the 〈110〉 direction on a (110) substrate is studied. No deterioration of transconductance and subthreshold swing at the front or back channels was induced by DA/SPER. The transconductance enhancement for the front and back channels on (110) substrates reaches +200% and +230% gain, respectively. For these transistors, we also discuss the variation of the external resistance and their operation in double-gate mode. [Copyright &y& Elsevier]

Abstract: The low-frequency noise (LFN) characteristics of triple-gate MOSFET with various fin widths are shown to exhibit 1/f type dependence. We show that LFN is generated by two parallel mechanisms, involving (i) the carrier number fluctuations due to trapping/release phenomena on the near-interface traps and (ii) the carrier mobility fluctuations in the channel. The relative contribution of each mechanism to LFN depends on the biasing conditions and varies with the fin width. The region of dominance of model (i) can be used for extracting the effective trap density, N t, which decreases as the fin becomes thinner. That is attributed to the carrier confinement in the central part of the transistor body, due to the volume inversion. The volume inversion effect is confirmed by independent measurements of low-field mobility, shown to be enhanced with the reduction of the fin width. The model (ii) contributes to LFN, only at small current values as it exhibits a power spectral density dependence varying as 1/I d. Random telegraph noise is manifested in small volume devices. [Copyright &y& Elsevier]

Abstract: The difficult scaling of bulk Dynamic Random Access Memories (DRAMs) has led to various concepts of capacitor-less single-transistor (1T) architectures based on SOI transistor floating-body effects. Amongst them, the Meta-Stable Dip RAM (MSDRAM), which is a double-gate Fully Depleted SOI transistor, exhibits attractive performances. The Meta-Stable Dip effect results from the reduced junction leakage current and the long carrier generation lifetime in thin silicon film transistors. In this study, various devices with different gate lengths, widths and silicon film thicknesses have been systematically explored, revealing the impact of transistor dimensions on the MSD effect. These experimental results are discussed and validated by two-dimensional numerical simulations. It is found that MSD is maintained for small dimensions even in standard SOI MOSFETs, although specific optimizations are expected to enhance MSDRAM performances. [Copyright &y& Elsevier]

Abstract: A transistor with ON/OFF switching voltage much lower than the theoretical limit of conventional FETs is demonstrated. The basic concept is to use the gate-induced modulation of the longitudinal component of the electric field directly in the drain p–n + junction of a thin film SOI FET. This modulation enables the gate to remarkably control the avalanche-impact-ionization of electrons and holes in the junction. Experimental results and a theoretical model are presented. The strong dependence of avalanche-impact-ionization current on the electric field intensity results in an extremely low switching voltage (6mV/decade at 300K). [Copyright &y& Elsevier]

Abstract: We simulate the electron transport in the inversion layer of ultra-thin silicon-on-insulator devices in the presence of a perpendicular magnetic field. We compute and compare the Hall mobility, the magnetoresistance mobility and the low-field drift mobility. The Hall and magnetoresistance factors, which are essential in order to have precise information on the effective mobility from experimental Hall or magnetoresistance data, are computed for various ultrathin SOI structures and temperatures. The results show that Hall mobility and magnetoresistance mobility are modulated by the SOI size effects, in particular the subband splitting. Not only the Hall and magnetoresistance factors can be quite different from unity, but they also depend on the device geometry and operating conditions. [Copyright &y& Elsevier]

Abstract: The carrier mobility in ultrathin SOI MOSFETs with thin SiO2 gate oxide is investigated by comparing the front and back channels. The front-gate split CV method is used at large substrate voltages to determine the carrier density and mobility in the back channel. The implementation of the split CV technique in ultrathin SOI films is described. This method is also efficient for determining the threshold voltage of the back channel. The accuracy as well as the limitations of the technique are discussed. Systematic experiments are presented for advanced n-channel and p-channel SOI MOSFETs. The results confirm that the mobility in the front channel is smaller than that in the back channel. [Copyright &y& Elsevier]

Abstract: A tunneling transistor (CONTUNT) compatible with ultra-thin SOI technology is presented. The gate controls the long depletion region of the drain p–n+ junction when the longitudinal component of the electric field becomes large enough to enable interband tunneling. The drain tunnel current strongly depends on the gate voltage. Our analytical model shows that the transistor transconductance and frequency of operation can reach about 1(A/V)/mm and 1THz, respectively. [Copyright &y& Elsevier]

Low-frequency noise characteristics of the silicon-on-insulator four-gate transistor [G4-field-effect transistor] are reported. The noise power spectral density as a function of biasing conditions is presented and compared for surface and volume conduction modes. It is shown that, for the same drain current, the volume of the transistor generates less noise than its surface. The possible transition from carrier-number fluctuations to mobility fluctuations as the conducting channel is moved away from the surface toward the volume is also discussed. [ABSTRACT FROM AUTHOR]

The four-gate silicon-on-insulator transistor (G4 -FET) combines MOS and JFET actions in a single transistor to control the drain current. The various operation modes of the G4-FET are analyzed based on the measured current-voltage, transconductance and threshold characteristics. The main parameters (threshold voltage, swing, mobility) are extracted and shown to be optimized for particular combinations of gate biasing. Numerical simulations are used to clarify the role of volume or interface conduction mechanisms. Besides excellent performance (such as subthreshold swing and transconductance) and unchallenged flexibility, the new device has the unique feature to allow independent switching by its four separate gates, which inspires many innovative applications. [ABSTRACT FROM AUTHOR]

A new floating-body effect in advanced fully-depleted SOI MOSFETs is revealed. Gate tunneling current is responsible for the body charging and may lead to the onset of an abnormal peak in transconductance. This effect occurs even at low drain voltage, is gate area-dependent, and can be modulated by driving the back-gate from weak to strong accumulation. A qualitative analytical model is proposed to explain the experimental enhancement of the transconductance peak and practical implications. [Copyright &y& Elsevier]

Transconductance measurements are performed on advanced fully depleted SOI MOSFETs and reveal a new floating-body effect. Gate tunneling current is responsible for the body charging and may lead to the onset of a strong second peak in front-gate transconductance. This effect occurs at low drain voltage and can be modulated by the back gate bias. We have investigated the size and the temperature (down to 100 K) dependence of the peak magnitude. A qualitative analytical model describes the onset and experimental behavior of the second transconductance peak. [Copyright &y& Elsevier]

We describe the operation of the novel SOI four-gate transistor (G4-FET) in the subthreshold region. The subthreshold slope, which may be defined with respect to either the junction gates or MOS gates, is adjustable using the remaining gates. A comparison of conventional MOSFET swings and G4-FET swings shows improved subthreshold slope. Systematic experimental data and simulations show the bias conditions for optimized performance. [Copyright &y& Elsevier]

Double-gate devices are best candidates for the MOSFET scaling down to the deca-nanometer range. The motivation of this work is to investigate the coupling effects in FinFETs and to extract the carrier mobility in each of the four possible channels. The coupling of the lateral, front and back interfaces is analyzed based on experimental results in FinFETs with various geometries. The influence of the substrate bias on the front and lateral surface potentials is especially emphasized. The back-gate action is minimized in ultra-narrow fins. Finally, the transport properties at each interface are presented and compared. The electron and hole mobilities are significantly lower on the fin edges than at the top and bottom interfaces. [Copyright &y& Elsevier]

This paper presents a detailed investigation of the quasi-static capacitance-voltage (QSCV) technique in pseudo-metal-oxide-semiconductor field effect transistor (pseudo-MOSFET) configuration for evaluating the interface quality of bare silicon-on-insulator (SOI) wafers, without processing dedicated metal-oxide-semiconductor (MOS) test devices. A physical model is developed that is capable of explaining the experimental results. In addition, frequency effects are used to validate the equations by a systematic comparison between experimental and calculated characteristics, as well as by a direct comparison with the standard high-low frequency approach. An extraction procedure for interface trap density based solely on QSCV experimental results is proposed, and limits of the procedure are discussed. The proposed experimental and analytical procedure is demonstrated by characterizing SOI structures with different geometries and with different qualities of surface passivation of the top silicon film. [ABSTRACT FROM AUTHOR]

The structure of zero impact ionization, zero subthreshold swing field-effect transistor (Z2-FET) has been modified by stacking a half side of back-gate (BG) with a heavily doped silicon layer instead of full covered BG. Through the modification, the memory window and retention time are significantly improved. For the modified Z2-FET, the retention time of “0”-state increases from 800 μs to 800 ms by reducing the read voltage from 1.1 to 1.0 V compared to the conventional Z2-FET. The simulation results show that the half BG helps the potential barrier to sustain the “0”-state longer without the potential collapse. The modified devices have wider memory window and larger sense margin than the conventional Z2-FET with full covered BG. [ABSTRACT FROM AUTHOR]

Abstract: Low-frequency noise (LFN) is generated by interactions of the channel carriers with interface traps and oxide charges. Therefore, noise measurements on silicon on insulator (SOI) wafers can give important information about the state of the interfaces and their defect density. Here, noise measurements at wafer level were performed using the pseudo-MOSFET (Ψ-MOSFET) configuration. 1/f noise behavior in relatively thick and ultra-thin SOI layers is obtained. No probe pressure dependence of the noise is observed. The influence of wafer surface states is showed and further confirmed in passivated SOI samples. Origins of noise generation are discussed. [Copyright &y& Elsevier]

One of the main issues in the characterization of silicon on insulator (SOI) substrates is to determine the quality of the film-buried oxide interface. This interface quality is strongly connected to the carrier lifetime in the silicon film. In this paper, we extend the well-known pseudo-MOSFET characterization technique for SOI wafers to the extraction of carrier lifetime. The experiment consists in comparing the drain current measured under dark and under laser shining. A model is proposed to evaluate the surface recombination velocity in SOI. Experimental results are validated by numerical simulations. [ABSTRACT FROM AUTHOR]

We discuss the role of back-gate biasing on effective field (Eeff) and its impact on the mobility in advanced ultrathin semiconductor-on-insulator metal-oxide-semiconductor field-effect-transistors using the multibranch mobility analysis. This technique is enabled using the integral definition for Eeff, which is the accurate method to determine Eeff even in volume-conduction regime. For further clarification, the difference between Eeff estimated by this integral definition and by the conventional formula is examined for our target devices. From the multibranch mobility analysis, we show that in devices with thin-buried oxide and ground plane doping, the reduction in Eeff due to back-gate biasing is large, leading to a significant mobility enhancement for both N-channel and P-channel devices. Furthermore, we show that the mobility enhancement effect via back-gate biasing in P-channel devices is larger than that in N-channel devices. This enhancement is attributed to the increase in the mobility under the volume-conduction regime. The mobility dependence with respect to Eeff reveals that strong volume conduction is achieved in P-channel devices, leading to a reduction of the surface scattering events at both interfaces, thereby increasing the mobility. This advantage adds to the already reported increase in the population of the light-hole bands. [ABSTRACT FROM AUTHOR]

We present an interesting transient effect found in silicon-on-insulator (SOI) transistors, where the drain current responds slowly to a back-gate voltage (VBG) pulse. This transient mechanism is due to the deep-depletion region in the SOI substrate induced by the VBG pulse and has been validated by experimental and TCAD simulation results. The deep-depletion characteristic can be employed for photodetection in a fully depleted (FD)-SOI MOSFET device. We have measured the photoresponse of the FD-SOI MOSFET under various light illumination conditions and studied systematically the impact of the VBG pulse duty ratio, amplitude, and period on the responsivity and detection range. An optimized device structure, fabricated in an advanced ultrathin body and buried oxide (BOX) (UTBB) SOI technology, shows low operation voltage and extended detection range. [ABSTRACT FROM AUTHOR]

We present a model for the tunneling field-effect transistor (TFET) comprising a series connection of a metal-oxide-semiconductor FET (MOSFET) with a gate-controllable tunneling diode. Through the introduction of MOSFET in the model, both operational regimes of TFET are handled correctly, with the tunneling diode dominating at low interband tunneling current and the MOSFET component dominating at high tunneling current. The comparison between our model, TCAD simulations and experimental data on TFETs with different gate oxide and channel thicknesses over the full range of gate and drain bias confirms the model's reliability and accuracy. At low tunneling current, the model further simplifies to a compact analytical model. With minor modifications, our model can also be applied to multi-gate TFET architectures. [ABSTRACT FROM AUTHOR]

We report on the nature of electrical transport in silicon-on-insulator layers, investigated using several techniques: the standard single magnetic field Hall effect, mobility spectrum analysis of the magnetic field-dependent Hall effect, and the pseudo-metal-oxide-semiconductor-field-effecttransistor technique. For moderate and strong inversion, electrical transport in the temperature range 77–300 K is dominated by a lone electron species with a mobility of 500-1000 cm2/Vs. A good correlation is noted between these methods. [ABSTRACT FROM AUTHOR]