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For the 7-nm technology node, cell placement with a drain-to-drain abutment (DDA) requires additional filler cells, increasing the placement area. This is the first work to fully automatically synthesize a DDA-aware cell library with the optimized number of drains on cell boundary based on ASAP 7-nm PDK. We propose a DDA-aware dynamic programming-based transistor placement. Previous works ignore the use of the M0 layer in cell routing. We first propose an ILP-based M0 routing planning. With M0 routing, the congestion of M1 routing can be reduced and the pin accessibility (PA) can be improved due to the diminished use of M2 routing. We also present a quadratic-programming based-coupling-capacitance-aware initial routing to optimize cell delay, cell area, and M2 usage. To improve the routing resource utilization, we propose an implicitly adjustable grid map, making the maze routing able to explore more routing solutions. The experimental results show that block placement using the DDA-aware cell library requires fewer filler cells than that using the traditional cell library by 25.1%, which achieves a block area reduction rate of 0.97%. [ABSTRACT FROM AUTHOR]

Shallow trench isolation drain extended MOS (STI-DeMOS) devices, known for their superior gate oxide reliability under high drain voltages, are widely used for the integration of CMOS-compatible high-voltage devices. However, they offer moderate high-frequency performance that limits the use of these devices even in mid-band 5G applications. A novel island drain and a double-gate drain-extended MOS (IDDG DeMOS) device with improved high-frequency performance is proposed in this work. The proposed device has a core MOSFET and an STI-DeMOS with a self-aligned pocket well, both feature a shorter channel length than a typical STI-DeMOS device. The shorter gate length enhances the proposed device’s RF performance without degrading the breakdown voltage. We have performed simulations using a well-calibrated deck in the Sentaurus TCAD environment. We have shown an increase in the transit frequency from 25 GHz in STI-DeNMOS to 53 GHz in the proposed IDDG DeNMOS device, and from 11 to 31 GHz for a p-type device at a 65-nm technology node. This work also presents the well edge variation immunity of the proposed device. All these features are achieved in the mainstream SoC-compatible CMOS process flow without any additional fabrication mask or process complexity. [ABSTRACT FROM AUTHOR]

In this work, a novel one-transistor active pixel sensor (1T-APS) with adjustable self-adaptive sensitivity enabled by floating source/drain (S/D) is demonstrated on 22-nm fully depleted Si-on-insulator (FD-SOI) platform. Additional control gates (CGs) with floating S/Ds are incorporated into the sensor, which are parallel to the sensing gate (SG). For weak illumination, the CG channel keeps closed so that the photoresponse is only active for SG controlled region, resulting in high linear sensitivity, while the CG channel will automatically turn on when the illumination is strong enough. Correspondingly, the CG controlled region is connected with SG controlled region for photoresponse together, resulting in a relatively lower linear sensitivity. For very strong illumination, the 1T-APS will automatically switch to logarithmic response mode due to the activated virtual photodiode in the FD-SOI substrate. The sensitivity transition points in the linear–linear region and the linear–logarithmic region can be further adjusted by the bias of CG and back gate, respectively. The adjustable self-adaptive sensitivity indicates the great potential of the proposed 1T-APS for high-quality image sensing. [ABSTRACT FROM AUTHOR]

Wide-bandgap (WBG) power devices have better dynamic characteristics and higher working temperatures compared to traditional Si devices and are more suitable for high-frequency and high-voltage applications because of fast turn-on and turn-off speeds. The main obstacle for the use of WBG devices is the high-frequency oscillation (HF-Osc) in voltage and current during the switching process. In this article, a new method of predicting the SiC mosfet switching behavior (including HF-Osc and slow switching) is proposed. First, the models of nonlinear capacitances are improved and parasitic elements are taken into account for improving the RLC equivalent circuit of the mosfet switching transient. On this basis, the LC equivalent frequency is obtained. Then, a new method is proposed to obtain the SiC mosfet instantaneous frequency. The comparison between them in the time domain makes it possible to analyze the SiC mosfet switching behavior. The prediction method is verified using a CREE SiC mosfet via a double pulse test. Experimental and simulation results show that the prediction method is effective in describing the HF-Osc characteristics. The proposed method can be used to effectively improve the mosfet HF-Osc, which provides guidance for the application of SiC mosfets. [ABSTRACT FROM AUTHOR]

The potential for negative-capacitance field-effect transistors (NCFETs) to enhance the unity-current-gain cutoff frequency ${f}_{T}$ and ${g}_{m}{f}_{T}/{I}_{D}$ ratio through a technique that mitigates the impacts of extrinsic parasitic capacitances is investigated, where ${g}_{m}$ is the transconductance and ${I}_{D}$ is the dc drain current and where “extrinsic” refers to elements arising outside an “intrinsic” or core transistor structure. We explain the technique and show that NCFETs can provide significant gains in extrinsic ${f}_{T}$ and ${g}_{m}{f}_{T}/{I}_{D}$ from this mitigation effect. However, an inherent degradation of intrinsic ${f}_{T}$ needs to be addressed to maximize these benefits, and this degradation can be alleviated through channel-length scaling as well as supply- and threshold-voltage tuning. The relative influences of different extrinsic parasitic elements are also evaluated, and it is found that improvements to ${f}_{T}$ and ${g}_{m}{f}_{T}/{I}_{D}$ increase as extrinsic parasitic capacitance increases and decrease as extrinsic parasitic resistance increases. Overall, this work finds that NCFET structures are promising candidates to mitigate the impacts of extrinsic parasitics in aggressively scaled transistors for the next-generation RF applications. [ABSTRACT FROM AUTHOR]

Gate sidewall spacers, a pathway to the fringing fields, play a crucial role in the device design. In this article, using well-calibrated TCAD models, we have explored the impact of a sidewall ferroelectric (FE) spacer on a negative capacitance (NC) FinFET. In the proposed study, the FE layer is present beneath the gate electrode and at the spacer region that operates in the NC region. Through three novel FE–dielectric (FE–DE) spacer configurations, we found that proficient electrostatic control can be attained with the optimized stacked placement of the spacers. The fringing fields alter the FE polarization present at the spacer stack and modulates the channel charge, which is a prime objective of this work. Furthermore, we have varied the FE parameters, drain doping, and extension length to optimize the proposed FE–DE spacer configurations. We have done mixed-mode simulations to design an inverter and a three-stage ring oscillator to emphasize our results. The optimized spacer configuration shows~3.9% overshoot due to higher gate capacitance (${C}_{GG}$); however, the $I_{\mathrm{ON}} / I_{\mathrm{OFF}}$ ratio is approximately twic than that of the baseline counterpart. The results reveal that the optimized spacer configuration also mitigates the negative differential resistance (NDR), which allows the NC-based devices to be an efficient candidate for analog applications. [ABSTRACT FROM AUTHOR]

Using a full design-technology cooptimization (DTCO) framework, we benchmark gate-all-around (GAA) nanosheet (NS) FETs against FinFETs at 3-nm logic technology relevant dimensions. First, to understand the intrinsic gain from NS, both device architectures are simulated using fixed technology ground rules [contact poly pitch (CPP), metal pitch ${M}_{x}$ , and cell height] and process assumptions (PAs), including stress, doping, junctions, and oxide thickness. Full geometry optimization along the CPP direction (gate length ${L}_{\text {G}}$ , spacer thickness ${T}_{\text {SP}}$ , and contact length ${L}_{\text {CNT}}$) is done to self-consistently account for tradeoff between short-channel effects (SCE), intrinsic and extrinsic resistances, and capacitances (device and parasitic). This leads to independent optimum design specifications for each Fin and NS architectures. Impact of Fin tapering and NS width and stack number are further investigated, showing additional design flexibility of GAA NS devices at scaled dimensions. [ABSTRACT FROM AUTHOR]

A unified model for multigate negative capacitance transistors with self-heating effects (SHEs) is developed. With a metal–ferroelectric–insulator–semiconductor (MFIS) structure, thermal effects result in different temperature rises in the channel and ferroelectric layer. A gate control equation for the double-gate and gate-all-around MFIS structures is developed, on top of which both the current–voltage and charge–voltage characteristics are covered. The formulations describe dependences of ferroelectric layer thickness, with backward compatibility for MOSFETs. A unified thermal network is then proposed for SHE, capturing the essential physics of couplings between ferroelectric temperature and conduction current. The model has been verified with TCAD simulations and implemented for circuit simulations. [ABSTRACT FROM AUTHOR]

Gate-oxide degradation has been one of the critical reliability concerns of silicon carbide (SiC) metal–oxide–semiconductor-field-effect transistors (mosfets), which could be monitored through aging-sensitive parameters. In this article, an online gate-oxide degradation monitoring method for planar SiC mosfets is proposed by extracting gate charge time at a specific range of gate voltage. It is based on the findings that the input capacitances of planar SiC mosfets change significantly over gate-oxide degradation, which is theoretically analyzed and experimentally verified. The capacitance variations are converted into the gate charge time as the new aging-sensitive parameter. The new parameter measurement circuit is proposed and integrated into the gate driver module. The article results indicate that the new parameter varies noticeably with gate-oxide degradation and the difference of this parameter caused by junction temperature is much smaller than that caused by degradation. Besides, the parameter is immune to package degradation and load current. The condition monitoring method can be implemented online since the parameter is extracted during the off-state of SiC mosfet devices, which does not affect normal operation. The confirmatory experiment is carried out to verify the correctness of the proposed method. [ABSTRACT FROM AUTHOR]

In designing ultra-efficient noise immune nanoscale circuits and systems, Schmitt triggers (STs) are vital components influencing total functionality. This article proposes an ultracompact ST using ferroelectric carbon nanotube field-effect transistors (Fe-CNTFETs) and a robust ST latch. By using the unique electrical futures of the Fe-CNTFETs, the proposed ST has been designed in a particular way to only employ two transistors similar to a conventional binary inverter. Moreover, by utilizing the negative capacitance feature of the Fe-CNTFETs, the proposed ST can perform the backup and restore operation during a scheduled power gating or a sudden power outage without imposing any additional transistors, interconnects, and control signals. The proposed ST latch is hardened to soft errors occurring due to unwanted single-event upsets (SEUs). Our extensive simulations demonstrate that our proposed ST latch offers lower transistors counts (on average 34%) and more energy savings (on average 79%). On the other hand, our design has shown 5.6 times on average higher critical charge tolerance than the previous counterparts due to its soft error hardening circuity and the superior hysteresis behavior of the proposed Fe-CNTFET-based ST. Moreover, the auto-nonvolatility of the proposed ST makes the proposed latches immune to the sudden power outage, which was not devised in the previous ST latches. Our results show new pathways in designing ultracompact and efficient nonvolatile ST latches using the Fe-CNTFET technology. [ABSTRACT FROM AUTHOR]

This article reviews and provides physical insights into the anomalous capacitance behavior of laterally diffused MOS (LDMOS) transistors. It is shown that the modulation of channel/drift junction potential with ${V}_{G}$ , ${V}_{D}$ , and ${V}_{S}$ is primarily responsible for the capacitance peaks observed at different bias conditions. The ${V}_{\text {GS}}$ at which these capacitances peak and their magnitude depends on the channel doping gradient (CDG) and drift region parameters. Simple mathematical models valid across all bias regimes are proposed to explain the anomalous behavior. Different LDMOS device designs are also suggested to mitigate or delay the capacitance peaks. [ABSTRACT FROM AUTHOR]

In this article, for the first time, we explained a detailed physical insight for negative differential resistance (NDR) to positive differential resistance (PDR) transition in a ferroelectric (FE)-based negative capacitance (NC) FET and also its dependence on the device terminal voltages. Using extensive well-calibrated TCAD simulations, we have investigated this phenomenon on fully depleted silicon on insulator (FDSOI)-NCFET. The NDR-to-PDR transition occurs due to FE layer capacitance changes from a negative to positive state during channel pinchoff. This, in turn, results in a valley point in the output characteristic (${I}_{DS}$ – ${V}_{DS}$) at which the output resistance is infinite. We also found that we could alter the valley point location by modulating the vertical electric field through the FE layer in the channel pinchoff region using body bias (${V}_{BB}$). The interface oxide charges also impacted the NDR to PDR transition, and a positive interface charge results in faster NDR to PDR transition. Furthermore, we have utilized the modulation in the NDR-to-PDR transition due to ${V}_{BB}$ for designing a current mirror. Results show that the output current (${I}_{OUT}$) variation due to ${V}_{DS}$ reduces from ~8% to ~2% with ${V}_{BB}$. We have also designed a single-stage common source (CS) amplifier and provided design guidelines to achieve a higher gain in the NDR region. The results obtained using a small-signal model of the FDSOI-NCFET demonstrate that ~25% higher gain can be achieved with the discussed design guidelines in the NDR region compared to the transition region of ${I}_{DS}$ – ${V}_{DS}$. We have also explored the device scaling effect on the amplifier gain and found that ~ $2.23\times $ gain can be increased with smaller channel length and higher device width. [ABSTRACT FROM AUTHOR]

MoS2 negative-capacitance field-effect transistors (NCFETs) with a gate-stack of Hf1-xZrxO2/Al2O3 are fabricated, and the effects of the Zr content and the thickness of the stacked gate on electrical performance of the devices are investigated. It is found that a large improvement of device performance can be achieved by optimizing these parameters, e.g., using 6-nm Hf0.5Zr0.5O2 (Zr content of 50%) as a ferroelectric layer and 2-nm Al2O3 as a matching layer, the relevant MoS2 NCFET exhibits the excellent electrical characteristics: a low subthreshold swing (SS) of 31.4 mV/dec, a smaller counterclockwise hysteresis of ~75 mV, and a high ON/ OFF current ratio of $3.26\times10$ 6. The involved mechanisms lie in that: 1) an enhanced remnant polarization leads to low SS and 2) changing the thickness of the Hf $_{1-{x}}$ ZrxO2 and Al2O3 can adjust the magnitude of ferroelectric capacitance and MOS capacitance to realize a reasonable match between both. [ABSTRACT FROM AUTHOR]

In this letter, for the first time, we investigate the role of Ferroelectric (FE) spacer in a negative capacitance (NC) FinFET. Using well-calibrated TCAD models, we found that instead of placing a dielectric (DE) spacer, if we use an FE spacer, enhanced electric field due to FE polarization can be achieved, thereby producing a higher ON-current. The fringing fields polarize the FE spacer and result in voltage amplification, which lowers the effective barrier and increases the current driving capability. ON-current of the proposed configuration, i.e., FE spacer at the source (S) side and DE spacer at the drain (D) side, is ~30% higher than the baseline FinFET. In this work, we have also proposed four different spacer placement configurations to realize better performances in terms of higher ON-current, mitigation of negative differential resistance (NDR) and better subthreshold slope (SS), and so on. We found that the optimized performance can be attained by placing an FE and DE spacer at the S and D end, respectively. We also evaluated a design space window for a good capacitance match to achieve NC effect for optimized device design. [ABSTRACT FROM AUTHOR]

The drain to gate capacitance (Miller capacitance) of SiC MOSFETs leads to the Miller effect during switching transients. The Miller capacitance in a phase-leg configuration causes the crosstalk, the interaction between the two complementary switches, and the Miller plateau during the switching transient. The Miller effect reduces the switching speed, reduces reliability, and increases electromagnetic interference. In this article, by injecting a mirror cancellation current, the effects of Miller capacitance are canceled. The proposed technique includes a two-stage sensing and injection network to compensate for the nonlinearity of the Miller capacitance. The proposed technique can suppress both positive and negative gate voltage spikes induced by the crosstalk and reduce the switching power loss with the increased switching speed. Because no external control signals are required in the proposed technique, it can work with almost all commercial gate drivers. The detailed design for this proposed technique is presented in this article. The proposed technique was validated with both simulations and experiments. [ABSTRACT FROM AUTHOR]

Design technology co-optimization (DTCO) has been a workhorse in optimizing logic technology innovations for a few generations now. With increased complexity associated with each new node and the growing number of technological innovations, it is time to expand the conventional DTCO flows. In this article, we present a novel materials to systems co-optimization (MSCO) platform, expanding the boundaries of traditional DTCO to encompass materials modeling to all the way to system design. To demonstrate the application of our MSCO platform, we discuss various front-end-of-line (FEOL) and middle-of-line (MOL)/back-end-of-line (BEOL) technologies and show their impact on device and circuit performance. [ABSTRACT FROM AUTHOR]

We propose a parallel negative-capacitance field-effect transistor (P-NCFET) structure, in which a ferroelectric operating in its negative-capacitance region is placed in parallel with the gate and source terminals of a MOSFET. The P-NCFET is stabilized by combining careful matching of the ferroelectric with the gate capacitance along with simple feedback realized using current mirrors. The novel stabilization approach opens the possibility for a variety of new applications that exploit the negative capacitance of ferroelectrics to cancel capacitance in integrated circuits. As an example, we show the P-NCFET structure has a significantly higher unity-current-gain frequency ${f}_{T}$ compared to a conventional MOSFET. [ABSTRACT FROM AUTHOR]

The gate–bulk/body voltage ${V}_{\text {gb}}$ -dependent effect of the source or drain–bulk/body junction capacitance ${C}_{j}$ that is originated from the variation in the gate-edge sidewall junction area due to the modulation of the channel depletion depth in the OFF-state region of bulk/PD-SOI MOSFETs is physically revealed. This ${V}_{\text {gb}}$ -dependent ${C}_{j}$ is accurately extracted from the measured S-parameters and newly modeled in the wide off-bias range. The geometry-dependent model and parameter extraction method are proposed to make the new ${C}_{j}$ model applicable in SPICE. [ABSTRACT FROM AUTHOR]

Temperature sensitive electrical parameter (TSEP) approaches are widely employed in the junction temperature ($T_{j}$) detection and prediction of power devices, especially the switching parameter. In this article, the voltage-rise time and its loss during the turn-off process are used as the TSEP index for the detection of junction temperature because of the coupling relationship with the maximum junction temperature. In addition, the effect of junction temperature on the current-fall time and its loss is compared. The theoretical analysis is verified by SABER simulation and H-bridge inverter circuit platform. It is established that the model based on voltage-rise time ($t_{\mathrm {rv}}$) and voltage-rise loss ($E_{\mathrm {rv}}$) is a viable model with good linearity, fixed sensitivity, and offers nondestructive insulated gate bipolar translator (IGBT) junction temperature extraction. [ABSTRACT FROM AUTHOR]

In this work, the influence of JFET region width on device’s performance and avalanche reliability is studied on 1200 V planar-gate silicon carbide (SiC) MOSFETs fabricated on a 4-in SiC wafer. Unclamped inductive switching (UIS) test is conducted to compare the devices under tests (DUTs) avalanche capability at both ${V}_{\text {GS}} ={0}$ V and ${V}_{\text {GS}} = -5$ V. At ${V}_{\text {GS}} ={0}$ V, the best avalanche reliability is achieved with a JFET region width of ${4}~\mu \text{m}$. Through mix-mode TCAD simulation, channel conduction is found to contribute to the failure at ${V}_{\text {GS}} ={0}$ V. While at ${V}_{\text {GS}} =-5$ V, the best avalanche reliability is achieved with a JFET region width ranging from 2 to ${3}~\mu \text{m}$. Hole injection is observed in the test and recognized in simulation, which critically influences the DUTs’ avalanche reliability at ${V}_{\text {GS}} = -5$ V. [ABSTRACT FROM AUTHOR]

A dynamic current model for the double gate negative capacitance field-effect transistor (NCFET) of the metal–ferroelectric–insulator–semiconductor (MFIS) structure is presented in this work. With a damping parameter ρ in the Landau–Khalatnikov (LK) theory for general ferroelectric (FE) materials, the gate control equation of NCFET is intrinsically dynamic which is solved directly as a basis of NCFET modeling. With the time-dependent charge densities at the source and drain sides, a dynamic current model is formulated analytically for the first time, considering the dynamic terms in a self-consistent way. The model has been verified with numerical TCAD simulations. It accurately reproduces the static negative capacitance (NC) effect in enhancing the driving current, as well as the dynamic NC effect, in the conduction delay and hysteresis for a wide range of NCFET parameters. The dynamic model after implementations is successfully applied to circuit simulations such as ring oscillators without convergence issues. [ABSTRACT FROM AUTHOR]

A multivalued logic (MVL) device can achieve greater data density with a smaller footprint than a traditional binary logic device. In this study, a ternary logic inverter based on negative capacitance FETs (NCFETs) without additional footprints has been realized. By enhancing the amplification in surface potential owing to the utilization of the negative capacitance, the third intermediate state can be successfully obtained at VDD/2 in the conventional binary CMOS inverter. The third intermediate state arises due to no-saturation effect of drain current, and the noise margin of the third intermediate state (NMM) can be optimized by changing ferroelectric thickness or annealing temperature of ferroelectric material. The influence of remnant polarization (Pr) and coercive electric (EC) variation on the ternary logic inverter was investigated based on experimental data. Moreover, a ternary logic 8T SRAM with transmission gate logic (TGL) was proposed, and the results show that the proposed 8T SRAM cell exhibits nondestructive read and reliable write operations for all three states. [ABSTRACT FROM AUTHOR]

In this work, a quasi-antiferroelectric (QAFE) model to precisely evaluate the electrical characteristics of negative capacitance Fin field-effect transistor (NC-FinFET) integrated with a QAFE gate insulator is proposed. A comparative study of the performance of transistors with ferroelectric (FE) and QAFE of different component ratios is carried out by combining the QAFE model and the BSIM-CMG model. The results demonstrate that the introduction of the QAFE gives rise to performance improvements than those of conventional FinFETs, which is ascribed to QAFE’s negative slope segment of polarization (P) versus voltage (V) around P = 0 for the QAFE NC-FinFETs. Because of the induced negative gate charges due to fringing electric field (E) coupling in the short channel of 3-D FinFET, subthreshold swing (SS) is just slightly lower than the tyrant limit of 60 mV/decade but a significant on-state current enhancement is found in the QAFE NC-FinFETs. The charge range, where the NC effect exists, shows a significant impact on the performance of the device due to the small remnant polarization of the QAFE layer. With the designed component ratio, a superior current enhancement can be obtained compared with the control device. This work provides a design guideline for the development of future high-speed and low-power NC-FinFET with QAFE material. [ABSTRACT FROM AUTHOR]

A novel RF small-signal model in the form of a physics-based equivalent circuit for advanced bulk FinFETs is proposed. Based on the unique multifin structure, parallel resistance–capacitance branches are introduced to account for the gate–source and gate–drain admittances. The deembedding is carefully performed after its effectiveness is verified by accurately modeling the pad and interconnect parasitics. An analytical method is developed to directly extract the model parameters from measurements. The model is validated in 7 and 14 nm bulk FinFET technologies, and the modeled results show an excellent agreement with the measured data up to 50 GHz (~ ƒT/4). The dependencies of FinFET RF performances on the layout dimensions are investigated, and they are compared between the two advanced FinFET technologies. [ABSTRACT FROM AUTHOR]

As superjunction devices are scaled down to smaller dimensions, the gate ringing becomes more prominent in dynamic switching. The exact origin of superjunction MOSFET's gate ringing has not been so far identified as the conventional three-terminal measurement method cannot capture the dynamic behavior of the device, in particular the redistribution of charge between the different internal capacitive components in the superjunction structure. In this article, it is found that the gate ringing is highly related to the input capacitance. Specifically, by employing a TCAD model with a split gate method, the gate-to-source (CGS) and gate-to-drain (CGD) current are investigated during the dynamic transitions. The gate ringing is highly dependent on sum of the input capacitances (CGS + CGD) for the turn-on. In the case of the turn-off, however, the gate ringing is affected by the ratio of the input capacitances (CGD/CGS) and a lower CGS is desirable for a low gate oscillation. [ABSTRACT FROM AUTHOR]

In this work, we analyze the impact of self-heating effects (SHEs) on 14-nm negative capacitance (NC)-FinFET performance from device to the circuit level. The 3-D thermal TCAD simulations, after careful calibration with measurements, are performed to analyze the impact of SHE in a broad range of frequency. Furthermore, we use the TCAD calibrated BSIM-CMG model to analyze the impact of SHE in NC-FinFET at the circuit level, after including a physics-based model to capture the NC effect. For the first time, we analyze the impact of a nonuniform distribution of temperature dissipated from the channel region to gate-stack in NC-FinFETs. On account of the thermal insulating properties of the gate-stack, the ferroelectric (FE) layer is found to be cooler than the channel region under the impact of SHE. We demonstrate that neglecting that and, hence, using the channel temperature to evaluate the temperature-dependent parameter α (in the Landau–Khalatanikov model of NC effect) of the FE layer result in a significant overestimation of SHE-induced degradations, such as in the NC voltage gain. Based on our TCAD analysis, we propose a relation between gate-stack temperature and the channel temperature and use this to accurately model the α parameter and, hence, SHE in NC-FinFETs. The SHE is found to dominate for both FinFET and NC-FinFET in the gigahertz range, which eventually degrades the performance at the circuit level, which is further confirmed using ring oscillator (RO) simulations. [ABSTRACT FROM AUTHOR]

This article presents switching performance analysis of a normally-off 3.5 kV β-Ga2O3 power FinFET using Silvaco TCAD simulation platform. The simulated electric field and OFF-state capacitances at a drain voltage (VD) of 3.5 kV were compared for FinFETs with two different structures: (i) 30-nm-thick Al2O3 in the planar regions and partially-filled (PF) inter-fin areas and (ii) 130-nm-thick Al2O3 in the planar regions and fully-filled (FF) inter-fin areas. The FF FinFET showed a smaller OFF-state CGS and CGD and the thicker Al2O3 significantly reduced peak electric field at the corner of the fin. Therefore, via TCAD device-circuit-integrated model, the impact of electron mobility in the MOS channel, bulk fin and drift region, and the substrate thickness on the device switching performances were investigated on a single-fin FF FinFET structure. The device with 100-μm-thick substrate and ideal drift region and fin mobilities of 180 cm2/Vs showed 82.6% improvement in the total switching time and 82.2% lower switching losses compared with the device which had thicker substrate thickness (600 μm) and lower electron mobilities in the drift region (130 cm2/Vs), bulk fin (30 cm2/Vs), and MOS channel (2 cm2/Vs). Moreover, the switching performance of multifin FF FinFETs with different fin width/pitch ratio was studied. At a given pitch size of 700 nm, the total power loss of the input power at a frequency of 200 kHz was reduced from 0.83% to 0.61% as pitch ratio reduced from 57.1% to 14.3%. These findings provide helpful insights for design and fabrication of Ga2O3 FinFETs with enhanced switching performance for low-waste power conversion applications. [ABSTRACT FROM AUTHOR]

Quantification of interface traps for double-gate fully depleted silicon-on-insulator transistors is needed for accurate device modeling and technology development. The trap density can be estimated as a function of the activation energy from the subthreshold current using the methodology developed in this work. It combines the earlier proposed gm/ID method with a revised form of the k-sweep method. The method is verified using TCAD simulated data and applied on engineering samples produced in 22FDX (R) technology, yielding a typical trap density of 2 · 1011 cm−2 eV−1. Association of the traps to the front or back interface is nontrivial; a trap allocation error of at least 20% is reported. [ABSTRACT FROM AUTHOR]

A Ka-band CMOS cascode power amplifier (PA) linearized with a cold-FET-based interstage matching network is presented, which is designed in a 65-nm CMOS process. Since it is difficult to make a cascode PA matched to the optimum output and input impedances at high frequencies, a matching network has to be introduced at the node between the common-source (CS) and common-gate (CG) stages. The cold-FET-based matching network improves the linearity and the input and output impedance matchings, which is analyzed and optimized with its simple model. It makes the PA have gain expansion and phase lag with the power, which allows the PA to have less amplitude-to-amplitude (AM–AM) and amplitude-to-phase (AM–PM) distortions. In addition, it improves the return losses of the PA by making the impedances for power matching and conjugate matching located closely. The implemented PA achieves the peak power-added efficiency (PAE) of 38.2% and the saturated output power ($P_{\mathrm {sat}}$) of 17.1 dBm at 31 GHz while occupying the chip area of 0.16 mm2. It is also shown that the OP1 dB is improved by 1.7 dB, and the AM–PM distortion is reduced to only 1.1° due to the linearization technique. It is tested with 64-quadrature amplitude modulation (QAM) signals, which has a 400-MHz channel bandwidth (BW) and a 9.7-dB peak-to-average power ratio (PAPR). It achieves average output powers of 9.6/7.7 dBm with error vector magnitudes (EVMs) of −25/−30 dB for 64-QAM OFDM signals, efficiencies of 17.7%/12%, and the adjacent channel leakage ratio (ACLR) of −28.2/−32.8 dBc, respectively. [ABSTRACT FROM AUTHOR]

We report an improved air spacer (AS) integration scheme to overcome problems with the conventional AS process. The new scheme is fully compatible with other emerging CMOS technology elements such as self-aligned contact (SAC) and contact over active gate (COAG). Using a fan-out3 (FO3) ring oscillator (RO) on a 10-nm FinFET platform, we experimentally demonstrate that the new AS provides 15% reduction in the effective capacitance (Ceff). Such a Ceff reduction translates to 21% performance gain at the constant power (iso-power) or 36% power reduction at the constant performance (iso-speed). The benefits provided by AS exceed the benefits of a full CMOS node scaling from 7 to 5 nm. Clearly, AS is a viable technological element for continuing CMOS scaling. [ABSTRACT FROM AUTHOR]

Previous methods of making metal-oxide electric-double-layer transistors (EDLTs) usually require a combination of different vacuum- or solution-based deposition techniques. Recent work has shown that sputtering offers another possibility to prepare oxide proton-conducting dielectrics for metal-oxide EDLTs. In this work, aluminum oxide proton-conducting dielectric is deposited by the dc reactive sputtering method, which helps the fabrication of fully metal-oxide EDLTs only with the sputtering technique. Humidity dependence of the obtained metal-oxide EDLTs is studied. It is found that humidity is a critical factor influencing the electrical characteristics. The underlying mechanism of humidity dependence is analyzed. Encapsulation of the device with polymer is demonstrated to provide basic isolation from humidity variation and stabilize the device. [ABSTRACT FROM AUTHOR]

Due to their fast switching capabilities, silicon carbide (SiC) MOSFETs are increasingly used in high-voltage pulsed-power circuits where fast and flexible high-voltage pulses are required (e.g. for plasma-processing applications), such as in our solid-state Impedance-matched Marx generator. The turn-on time of SiC MOSFETs mainly depends on the gate-driving technique and its implementation. Therefore, many studies focus on SiC MOSFET gate-driving methods. In this article, a gate-boosting driving method that was previously proposed for IGBTs is optimized for SiC MOSFETs and applied to a very fast MOSFET to reduce turn-on time as much as possible. A prototype of the optimized gate-boosting driver was built and tested to assess its performance. The test results validate the effectiveness of the optimized gate-driving method and showed that a MOSFET turn-on time of below 2 ns is achievable at a high operating voltage and moderate current and below 3 ns for a wider range of load-current and operating-voltage conditions. Furthermore, current rise rates of 38.7 kA/ $\mu \text{s}$ at 356-A load current are possible. All these results are considerably faster than ever demonstrated before. [ABSTRACT FROM AUTHOR]

Independent back bias in the ultrathin body and Box (UTBB) fully depleted silicon-on-insulator (FDSOI) serves as the critical knob for exploiting the performance and power tradeoffs and process/aging compensation. The effectiveness of back bias is one of the major metrics in the stages of circuit design and runtime feedback. In this article, new closed-form expressions accounting for the interface traps and short channel effects-dependent back gate capability in the UTBB FDSOI device are proposed. The developed model allows the accurate assessment of body factor (γ) with the dependence of front/back interface trap density in the ultrascaled FDSOI device, taking the impact of gate area scaling as well as quantum effects into account. It also facilitates the evaluation of back bias effectiveness variability induced by interface traps and benefits the dynamic threshold voltage strategy in terms of adaptive back-biasing for performance optimization, which is consistent with 3-D device simulations and measurements. Moreover, the results confirm that γ variability follows Pelgrom’s rule. [ABSTRACT FROM AUTHOR]

A new differential method for accurate extraction of electrical parameters of high-electron mobility transistor (HEMT) devices for gallium nitride (GaN) technology is proposed. This method, presented here for the first time, is used to study the mobility degradation with gate length, allowing an analysis of the contribution of the gate edge region to the total metal–insulator semiconductor (MIS)-HEMT device conductance. First, an analytical model is proposed to account for the relative conduction of the edges and the main flat part of the channel HEMTs. Second, the differential method allows the split-CV mobility extraction of each part, allowing a precise analysis of the resistive contribution of each region of the HEMT devices. This study has been performed over a large range of channel lengths for two normally OFF HEMT GaN wafers having different recess depths. [ABSTRACT FROM AUTHOR]

Side-channel attacks have empowered bypassing of cryptographic components in circuits. Power side-channel (PSC) attacks have received particular traction, owing to their noninvasiveness and proven effectiveness. Aside from prior art focused on conventional technologies, this is the first work to investigate the emerging negative capacitance transistor (NCFET) technology in the context of PSC attacks. We implement a CAD flow for the PSC evaluation at design time. It leverages industry-standard design tools, while also employing the widely accepted correlation power analysis (CPA) attack. Using standard-cell libraries based on the 7-nm FinFET technology for NCFET and its counterpart CMOS setup, our evaluation reveals that NCFET-based circuits are more resilient to the classical CPA attack, due to the considerable effect of negative capacitance on the switching power. We also demonstrate that the thicker the ferroelectric layer, the higher the resiliency of the NCFET-based circuit, which opens new doors for optimization and tradeoffs. [ABSTRACT FROM AUTHOR]

Nanosheet gate-all-around transistors are analyzed for RF applications using calibrated TCAD simulations. The effects of stack spacing and number of stacks on device performance are studied and a substack design for improved RF performance is proposed. The novel substack design can improve cut-off frequency (Ft) by ~10% and minimum number of substacks and minimum substack spacing should be used. [ABSTRACT FROM AUTHOR]

We have analyzed the program disturbance immunity mechanism of a vertical assist-select gate lateral coupling (VA-SGLC) cell. Comparing different operation methods of unit cells fabricated with the same process, we verified the array structure and operation mode dependence of the program disturbance. As an embedded nonvolatile memory, the VA-SGLC cell offers advantages of no additional masks and process steps as well as fast program speed and program/erase cycling performance exceeding 10 k. Furthermore, it exhibited abnormally strong disturbance immunity. Using worst-case disturbance measurements and potential difference comparisons, we verified the mechanism of the abnormally strong disturbance immunity of the VA-SGLC cell. The strong program disturbance immunity of VA-SGLC cell is due to the varying coupling ratio caused by coupling dividing operation methods. These features arise from the distinctive array structures and operation methods of the VA-SGLC cell. [ABSTRACT FROM AUTHOR]

The anomalous RF inductive effect in which S21- and S22-parameters rotate clockwise in the lower and upper half-circles, respectively, with increasing the frequency at the high VDS region has been investigated in body contact (BCT) high-resistivity (HR) partially depleted (PD) silicon-on-insulator (SOI) nMOSFETs with a very high aspect ratio of gate finger. The negative output capacitance generated from a substrate current-induced body effect (SCBE) is physically identified for the first time as the origin of the RF inductive effect by deriving the output admittance equation of a body transconductance source in RF equivalent circuit model considering SCBE. The bias-dependent frequency effect that the drain–source conductance and negative capacitance converted from measured S-parameters are largely reduced by higher pole frequency with increasing VDS is clearly explained by admittance equations derived from the SCBE output equivalent circuit. The bias-dependencies of inductive effect parameters related to SCBE are accurately extracted using small-signal equivalent circuit modeling of BCT PD-SOI nMOSFETs. Based on this result, the bias-dependence of S21- and S22-parameters is analyzed in detail. [ABSTRACT FROM AUTHOR]

A comprehensive time-domain modeling and a generalized design methodology for input and output waveform engineered Class-F power amplifiers (PAs) are presented in this article. A closed-form relationship between input nonlinearity and second harmonic source impedance ($Z_{\mathrm {2S}}$) termination is presented from which efficiency and output power performance are predicted for Class-F PAs. The maximum, minimum, and safe $Z_{\mathrm {2S}}$ design space for a Class-F PA are identified. Moreover, the derived design equations show that the typical fundamental load of a Class-F PA operation must be re-engineered in the presence of input nonlinearity in order to achieve optimum efficiency performance. The theoretical analyses are first validated with pulsed vector load–pull (VLP) measurements with a gallium nitride (GaN) 2 mm device. Then, high-power (210 W) GaN 24-mm devices with in-package $Z_{\mathrm {2S}}$ terminations are implemented. Measurement results with the new source and load design space show efficiency improvement of 4.4% compared to the nominal Class-F PA. [ABSTRACT FROM AUTHOR]

This article presents a 60-GHz CMOS power amplifier (PA) with an adaptive impedance-compensation linearizer in the 65-nm CMOS process. The proposed linearizer adaptively provides resistance and capacitance that vary appropriately with input power, enabling amplitude-to-amplitude modulation (AM-AM) and amplitude-to-phase modulation (AM-PM) distortions to be compensated simultaneously. The fabricated PA with linearizer on achieves a $P_{\mathrm {1\,dB}}$ of 12.3 dBm and a peak power-added efficiency (PAE) of 15.6% at such $P_{\mathrm {1\,dB}}$ , which demonstrate improvements of 2.8 dB and 6.8%, respectively, compared with the PA with linearizer off. The PA also achieves the peak gain of 31.0 dB, peak saturated power ($P_{\mathrm {SAT}}$) of 15.0 dBm, and peak PAEmax of 22.7%. In addition, the AM-AM distortion at 6-dB output back-off (OBO) is less than 0.1 dB, and the AM-PM distortion at $P_{\mathrm {1\,dB}}$ is less than 1.5° in the overall 3-dB frequency band. The improvements in both the AM-AM and AM-PM signals lead to a 1.7-dB improvement in OBO at third-order intermodulated distortion of −25 dBc without adding to power consumption. [ABSTRACT FROM AUTHOR]

This article presents a cascaded distributed power amplifier (DPA) topology with greater than 4.5-THz gain–bandwidth (GBW) product. The DPA uses stacking with multi-drive inter-stack coupling to compensate for the stacked gain cells and input transmission-line (TL) losses. The techniques improve the gain and output power without compromising the bandwidth (BW). The cascaded DPA employs eight-shaped TLs to allow inter-stack coupling in a compact area and for field confinement. A 33-dB gain, 101.5 GHz BW DPA is realized in the 45-nm RFSOI GlobalFoundries process. The amplifier maintains $P_{1\,dB}$ and $P_{SAT} > 18.7$ and 21 dBm, respectively, up to 60 GHz, with over 60 GHz $P_{SAT}~3$ -dB BW, while demonstrating >14 dBm of average $P_{OUT}$ for a 30-Gb/s 64-QAM modulated signal, with an error vector magnitude (EVM) <5%. The DPA is also able to provide a 72-Gb/s 64-QAM signal with 13.6 dBm average $P_{OUT}$ from a 13 GHz carrier frequency. To the best of our knowledge, the cascaded multi-drive DPA achieves the highest reported GBW, continuous-wave (CW) $P_{SAT}$ , and average $P_{OUT}$ for 64-QAM 30-Gb/s modulated signal, in a compact core area compared to published silicon-based DPAs with comparable power levels. [ABSTRACT FROM AUTHOR]

Accurate delay analysis with distributed RC delay can be computationally expensive, and can contribute the majority of the total runtime for gate sizers. Recent works have shown that Lagrangian relaxation (LR)-based gate sizers have produced designs with the lowest power on average. But they are also very slow due to a large number of expensive timing updates spread across several tens of iterations. In this paper, we develop an LR-based discrete gate sizer for fast timing and power reduction. Our gate sizer is multithreaded and is equipped with parallelization enabling techniques, namely mutual exclusion edge (MEE) assignment and directed acyclic graph (DAG)-based netlist traversal (DNT). MEEs are dummy edges assigned to improve load sharing among different threads. DNT facilitates simultaneous resizing of gates belonging to different topological levels. Our Lagrange multiplier update strategy enables rapid convergence of our timing and power recovery algorithms. To reduce the runtime of timing updates, we propose a simple and fast-to-compute effective capacitance model. We further propose mechanisms to calibrate timing models to improve their accuracy. By calibrating the internal timing models only twice, our proposed gate sizing flow facilitates extremely fast design optimization. We benchmark our gate sizer using the ISPD 2012 and 2013 gate sizing contest benchmark suites. Compared to the state-of-the-art gate sizer, our proposed gate sizer is on average $15\times $ faster and the optimized designs have 2.5% higher leakage power. Since we tradeoff timing accuracy for larger runtime speedup, our optimized designs have small timing violations. [ABSTRACT FROM AUTHOR]

This article presents the design, experimental results, and modeling of an inversion-mode CMOS varactor integrated in the STMicroelectronics 55-nm BiCMOS technology. The device was characterized from 1 to 325 GHz, demonstrating high-quality factor at millimeter-waves. For instance, a quality factor of 7 at around 190 GHz for a tuning ratio (Cmax/Cmin) greater than 4 was measured. This performance overpasses that of accumulation-mode varactors usually provided in CMOS technologies design kits, for frequencies beyond about 100 GHz. In addition, a small-signal electrical model is provided from 100 to 250 GHz. [ABSTRACT FROM AUTHOR]

The dV/dt in superjunction metal–oxide–semiconductor field-effect transistors (MOSFETs) during the turn-off transient has been shown to be higher than during the turn-on, which can be attributed to a shorter Miller plateau. In this article, we will show that these asymmetrical turn-on and turn-off characteristics are indirectly detected by the hysteresis of the dynamic gate-to-drain capacitance, CGD. Moreover, this article reveals the mechanisms behind the asymmetrical switching and the origin of the hysteresis, which have been shown to be caused by the difference in the CGD displacement current paths for the turn-off and the turn-on. [ABSTRACT FROM AUTHOR]

As the dimensions of the power metal-semiconductor field-effect transistor (MOSFET) are scaling down, and the output capacitance is considerably reduced, the fast dV/dt becomes an issue and can trigger severe oscillations during hard switching. To understand the origin of the dV/dt and the induced gate oscillations, the intricate link between the device operation and the circuit conditions is required. In this article, the dynamic gate-to-drain capacitance, CGD, is extracted by employing a five-terminal method. Through the use of simulations, the relationship between CGD and the induced gate oscillations is explored. In addition to this, the 2-D depletion behavior in a superjunction system, which affects the dynamic CGD, is investigated. [ABSTRACT FROM AUTHOR]

In this article, structure optimization of high-k interfacial layer (IL), deposited between the gate and the gate sidewall spacer, was performed in a 5-nm node nanosheet field-effect transistor (NSFET). High-k IL can be formed during the high-k gate dielectric and metal gate (HKMG) with gate-last process. By optimizing the structure of thickness of high-k IL (Thk) with gate length (LG), spacer length (Lext), and source/drain (S/D) length (LS/D), improved electrical performances were obtained. By optimizing Thk with properly adjusted LG, Lext, and LS/D, highly saturated ON-/OFF-current ratio (ION/IOFF) was obtained with appropriate drain-induced barrier lowering (DIBL). Besides, reduced intrinsic gate delay (Cgg) properties and OFF-state leakage current were identified. In addition, the reason of increased OFF-state leakage, which can be shown when Lext shrinks with extending Thk, was also investigated. Finally, the optimized electrical characteristics were obtained when Thk is adjusted with LG and LS/D. The power was reduced about 27% with the same performance and 18% enhanced performance was obtained when Thk is optimized through LG. On the contrary, reduced OFF-state leakage current and DIBL were confirmed in the case of optimization point with LS/D, which result in lower static power. Based on this comparison, optimization method and guideline for high-k IL was proposed. [ABSTRACT FROM AUTHOR]

Printed electronics can benefit from the deployment of electrolytes as gate insulators, which enables a high gate capacitance per unit area (1– 10 μF cm−2) due to the formation of electrical double layers (EDLs). Consequently, electrolyte-gated field-effect transistors (EGFETs) attain high-charge carrier densities already in the subvoltage regime, allowing for low-voltage operation of circuits and systems. This article presents a systematic study of lumped terminal capacitances of printed electrolyte-gated transistors under various dc bias conditions. We perform voltage-dependent impedance measurements and separate extrinsic components from the lumped terminal capacitance. The proposed Meyer-like capacitance model, which also accounts for the nonquasi-static (NQS) effect, agrees well with experimental data. Finally, to verify the model, we implement it in Verilog-A and simulate the transient response of an inverter and a ring oscillator circuit. Simulation results are in good agreement with the measurement data of fabricated devices. [ABSTRACT FROM AUTHOR]

The gate architecture of a 1.2-kV SiC planar MOSFET is engineered to obtain the improved high-frequency figure of merit (HF-FOM) over the split-gate (SG) and planar-gate topology. In this article, we propose a device using the split dummy gate (SDG), which is in short with the source contact at zero potential. The device has a lower reverse transfer/feedback capacitance (Crss or Cgd) due to the formation of depletion width under SDG and lower gate-to-drain charge (Qgd) due to reduced overlap with the substrate leading to excellent HF-FOM (Ron,sp × Cgd and Ron,sp × Qgd). The essential electrical characteristics (such as Ron,sp, breakdown voltage (BV), and Vth) remain almost similar compared to the device without the dummy gate. The obtained HF-FOM (Ron,sp × Qgd) is 28.7 × and 186 × lower compared to the device with SG and planar-gate topology, respectively. Using calibrated Sentaurus TCAD simulations, the proposed SDG MOSFET has shown negligible Miller plateau (Qgd), reduced crowding of the electric field at the SG corner, and improved turn-on/off characteristics with a reduction in switching energies. [ABSTRACT FROM AUTHOR]

This article presents PSPHV, a surface-potential-based compact model for laterally diffused MOS (LDMOS) transistors. PSPHV includes a new drain voltage scaling technique that enables accurate modeling of saturation in transistors with nonuniform lateral doping; gate bias-dependent interface charge, which models the gradual channel turn- ON seen in devices with halo doping; internal drain bias clamping, which eliminates the capacitance spikes seen in most existing LDMOS models; and a new avalanche current model for the drift region that accounts for the Kirk effect. PSPHV models the drain expansion effect and diode reverse recovery and is verified against experimental data. [ABSTRACT FROM AUTHOR]

The flipped-voltage-follower-based low-dropout regulator (LDO) has drawn attention for its fast response and reduced complexity, while super source follower can be combined to push the pole at the gate of the pass device to high frequency. But the maximum load current and minimum load capacitance of this topology are limited, especially when the poles and zero from the SSF are omitted in previous designs. This paper proposes a solution to extend the ranges of the load current and load capacitance, by implementing a small feed-forward capacitor ($C_{F}$) and a damping factor control circuitry. In addition, a slew rate enhancement circuit is applied to reduce the voltage undershoot. The proposed LDO is verified in a 65-nm CMOS process with 0.008 mm2 active area. The measured voltage undershoot is 80 mV with a load steps from 100 μA to 50 mA with 2-ns edge times, with no external capacitor. And the maximum load capacitance can be extended to 2 nF. A figure-of-merit of 0.8 mV is achieved. [ABSTRACT FROM AUTHOR]