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The Model 770 hybrid in-circuit tester is a newly released device from Factron, Latham. Designed to test fully loaded pc boards containing a combination of analog and digital components, the device uses software that samples analog output and predicts the eventual steady-state response. The 128-pin version costs $185,000. A photograph is included.

Because of the complexity of VLSI transistor counts and circuit functions new computer-aided-design (CAD) and testing (CAT) techniques are needed. Besides redundancy, future chips will have a design-for-testability or a built-in-test capability. Structural design methods will make it easier for users to develop test programs with an application-oriented approach. Many computer-aided-testing tools are available to generate and evaluate test sequences for a component and tester by using logic and fault-logic modeling techniques. There are a number of techniques to verify the integrity of test software using discrete implementation or software simulation. Design-for-test is the process of making a deliberate design effort to ensure that VLSI circuits can be tested. Current design-for-test techniques include serial scan, level-sensitive scan detection, signature analysis, unstructured design-for-test, and addressable register. Tables list typical CAT tools, requirements for CAT systems, and problems with CAT. Diagrams show the CAD-CAT merge, a typical test system, and design-for-test techniques.

As VLSI circuits become more complex, VLSI testers are developing with handling of up to 300-pin channels, complex levels of functional testing, and interfaces for computer-aided-design and test equipment. The Viking 200 tester from Cybernetics Technology has a high-speed computer architecture for VLSI 100-MHz test operand speed. Tektronix's S-3295 20- or 40-MHz VLSI test system supports up to 256 pins and handles a diversity of logic types. Independent resources are provided behind each pin in the Mega One from Megatest Corp. Fairchild's Sentry 50 tester is managed by a VAX-11-730 and has a 64-K-word inter leaved main memory and a 1-K-word high-speed subroutine memory. The GR-18 from GenRad is built around a DEC PD-11-44 with an RSZ-11M operating system. A table lists supplies and characteristics of VLSI testers and several designs are shown in diagrams.

The expense of 'bed-of-nails' fixtures for testing bare printed- circuit boards is causing low-volume printed-circuit (pc) board manufacturers to look for alternative methods. Cirdyne will introduce a computerized tester within a few months which utilizes two parallel bars which move around the board. The system, which is designed to be easy to learn, tests for correct continuity and voltage leakage. A photograph of one of the tester's parallel bars is included.

A technique is described that allows expansion of ATE parametric-tester pin count for approximately $500 in parts cost. This could be a reasonable alternative to either buying a new tester or decreasing your pin count. Rather than using traditional relays, this technique uses fast-settling programmable voltage sources that provide more input channels to the DUT. The circuit also uses an 8-Bit D-A convertor to supply a 10.2V FS output voltage source, and two MM74C373 CMOS latches to drive the convertor and hold a value while the processor is performing other functions. A schematic diagram is included.

A simple piece of test equipment can be made of DIP switches soldered between a wire wrap socket and a DIP solder socket. This device can then be plugged directly into a circuit board, and the DIP component and the circuit can be tested with various pins being turned off or on. This device can save time and trouble in designing, debugging, and troubleshooting circuitry using ICs.