A Merger of CAD and CAT Is Breaking the VLSI Test Bottleneck

Because of the complexity of VLSI transistor counts and circuit functions new computer-aided-design (CAD) and testing (CAT) techniques are needed. Besides redundancy, future chips will have a design-for-testability or a built-in-test capability. Structural design methods will make it easier for users to develop test programs with an application-oriented approach. Many computer-aided-testing tools are available to generate and evaluate test sequences for a component and tester by using logic and fault-logic modeling techniques. There are a number of techniques to verify the integrity of test software using discrete implementation or software simulation. Design-for-test is the process of making a deliberate design effort to ensure that VLSI circuits can be tested. Current design-for-test techniques include serial scan, level-sensitive scan detection, signature analysis, unstructured design-for-test, and addressable register. Tables list typical CAT tools, requirements for CAT systems, and problems with CAT. Diagrams show the CAD-CAT merge, a typical test system, and design-for-test techniques.