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Hybrid transform and scalar quantization is a key component in ITU-T H.264, and mathematic analysis and decomposition are elaborately made for its hardware implementation, the calculation process is simplified, all time-consuming and hardware expensive multiplication and division are avoided effectively. A new block parallel VLSI architecture mainly containing a 2D direct hybrid transform engine and a full wiring 52-level scalar quantizer is proposed. It is very suitable for pipeline acceleration, and the block throughput rate can reach 156 M/s with one register row inserted, which can satisfy 4096times2304@150 Hz digital video coding in real-time easily, even all macroblocks are predicted with intra_16times16 mode.

Nowadays, since most information is transmitted by public medias, the security of information is very important, especially of confidential information. The information security system has its particular processing method. The use of cryptographic machine is one of the effective solutions. The hidden trouble of cryptographic machine mainly comes from information processing kernel program and key chip. And in China, information security is being menaced, for most of the key chip involving the information security devices come from abroad. Developing the key chip-set for information security system is a hard and chief task for China. A research on system-level architecture of single-chip cryptographic data processing is presented. The architecture involves microprocessor core architecture, data interface, user ID interface, special component for cryptographic data processing and cryptographic algorithms RSA and CHES VLSI implementation IP module and the true random number generator. All of the functions are necessary for the system on a single cryptographic data processing chip. The architecture, including microprocessor core architecture, is incompatible with any other system, and has a special function to accelerate cryptographic data processing, so it is a very effective way to implement information security chip.

The digital comparator is a widely used circuit block. The typical versions using static CMOS logic have been well known. In this paper we present a new efficient design-MCP, which employs Manchester chain to fulfil the compare operation. Compared with the static implementations, MCP's highest operating frequency (125 MHz) is much higher. At the same operating frequency, MCP's power dissipation is 15%-22% lower than static version's. The layout area of MCP is only 87.6% of the static's and it is very convenient for implementing parallel or pipeline structure that is important for high performance VLSI design. By a series of optimizations the MCP gained a good noise immunity, though it is sensitive to noise glitches for its dynamic structure. MCP is a high quality function block and suitable for high performance VLSI design.

Accumulator, as the key element in NCO, can be designed in pipelined structure to increase clock frequency. But regular pipelined structure brings about the logger latency. In this paper a novel design is presented, that uses carry-save addition and carry-feed unit in an accumulator and as a result the latency has been improved considerably.

An numerically controlled oscillator chip, using a pipelined structure, has been developed in standard 2 /spl mu/m P-well CMOS technology. The typical maximum input clock rate is 6.5 MHz. By analysis, the speed limiting factors improved are the delay of the accumulator and the data acquiring rate of the ROM. Through the use of an improved pipelined structure and N-well CMOS technology, an NCO device with a clock rate in excess of 10 MHz is indeed possible.

A novel control circuit is proposed to suppress the jitter caused by high frequency noise, which spectrum is beyond the loop bandwidth of the PLL used as clock generator in an USB2.0 application. Hspice simulates the circuits with BSIM3V3 model, and the cycle-to-cycle jitter is 1.68 ps when the VDD noise is 200 mv, 10 MHz square wave.

With the rapid progress of information technology, security becomes one of the key factors in information storage, communication and processing. For the reason of speed and security, the requirement for VLSI chips or modules that support data encryption and decryption increases rapidly. The design and implementation of a data ciphering processor (DCP) chip adopting block cipher algorithm is demonstrated in this paper. The cipher algorithm is qualified for commercial use. The plaintext, ciphertext and key are all 64-bit long. A top-down design flow is used in the implementation. Several methods are employed to enhance the security of the chip. A standard-cell library is also developed in the design. All the design and implementation of this DCP are performed in China. A 0.9um double-layer-metal CMOS technology is adopted for manufacture. The chip achieves the required result in the first time implementation. The encryption/decryption processing speed reaches 40MBit/s.

With analyzing features of the accumulator in numerically controlled oscillator (NCO), it is pointed out that design based on pipeline for NCO is feasible. The schematic and results of logic simulation are given in this paper. The pipeline based NCO has evidently more advantages: higher speed (about twice) and fewer components (about 2/3) than usual. >