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A novel low jitter PLL clock generator with supply noise insensitive design.

Authors :
Lin Yijing
Sheng Shimin
Source :
2001 4th International Conference on ASIC Proceedings ASICON 2001 (Cat. No.01TH8549); 2001, p259-261, 3p
Publication Year :
2001

Details

Language :
English
ISBNs :
9780780366770
Database :
Complementary Index
Journal :
2001 4th International Conference on ASIC Proceedings ASICON 2001 (Cat. No.01TH8549)
Publication Type :
Conference
Accession number :
81113843
Full Text :
https://doi.org/10.1109/ICASIC.2001.982547