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The technology transfer of terahertz wireless communication from research laboratories to commercial applications is a global strategic achievement currently pursued to match the ever-increasing demand for high-speed communication. The use of commercial integrated electronics for the detection of THz waves is an intriguing challenge which has enticed great interest in the scientific research community. Rapid progress in this field has led to the exploitation of THz direct detection using standard CMOS technology based on the so-called self-mixing effect. Our research, stemming out of a collaboration between Sapienza University of Rome and STMicroelectronics company, is focused on the complete design process of a THz rectifier, realized using 50 nm ST B55 CMOS technology. In this paper, we report the optimization process of a case-study receiver, aimed to demonstrate the feasibility of direct demodulation of the transmitted OOK signal. A relatively limited bandwidth extension is considered since the device will be included in a system adopting a radiation source with a limited band. The design refers to a specific technology, the 60 nm MOS in B55X ST; nevertheless, the proposed optimization procedure can be applied in principle to any MOS device. Several aspects of the rectification process and of the receiver design are investigated by combining different numerical simulation methodologies. The direct representation of the rectification effect through the equivalent circuit of the detector is provided, which allows for the investigation of the detector–amplifier coupling, and the computation of output noise equivalent power. Numerical results are presented and used as the basis for the optimization of the receiver parameters. [ABSTRACT FROM AUTHOR]

The semiconductor industry is the core industry of the information age. As a key link in the semiconductor industry, wafer fabrication plays a key role in its development. In the testing stage of the wafer, each die of the wafer is detected and marked, and a wafer map with a certain spatial pattern can be formed. The analysis and classification of these spatial patterns can identify the cause of wafer defects, thereby improving production yield. However, as wafer size increases, line widths become smaller, etc., the probability of a mixed defect mode wafer pattern increases. Moreover, the mixed defect mode wafer map is more difficult to identify and classify than the single defect mode wafer map. Therefore, this paper proposes an improved deep convolutional neural network (DCNN) structure model for the recognition and classification of mixed defect pattern wafer maps. From the perspective of increasing the width of the DCNN, the improved network structure can avoid problems such as over-fitting and limited extraction of features due to the continuous deepening of the DCNN. The network is called Multi-Path DCNN (MP-DCNN) structure. The experimental results show that the proposed Multi-Path DCNN structure has better performance and higher classification accuracy than existing methods. [ABSTRACT FROM AUTHOR]

This paper proposes a novel method for Virtual Metrology (VM) in plasma etch processes based on analysis of all time and wavelength samples of Optical Emission Spectroscopy (OES) signals. The new method flattens each OES signal into a single vector, after which Singular Value Decomposition (SVD) is performed on the matrix formed by vectors of flattened OES signals in the training dataset. Low rank SVD projections of flattened and standardized OES recordings served as inputs for Ridge Regression, Artificial Neural Network, and Random Forest based VM models. A VM study is then conducted on a dataset gathered from a major 300 mm wafer fabrication facility, showing that the use of newly proposed SVD-based OES features consistently outperformed benchmark VM model features. Additional analysis of feature importance performed based on the analytically tractable Ridge Regression VM model form demonstrated distinct time-frequency patterns of OES signal portions that were highly informative for prediction of relevant Critical Dimensions, clearly justifying the need to use the entire OES signals for VM. [ABSTRACT FROM AUTHOR]

Chemical mechanical planarization (CMP) is vital for ensuring chip fabrication uniformity at nanometer scales. The emergence of a series of phenomenological CMP process models (Stine et al., 1997; Gbondo-Tugbawa, 2002; Xie, 2007; Vasilev, 2011) suggests that the existing model upgrade approach is largely based on a change in phenomenological model assumptions, demanding deep insights into complex process mechanisms and protracted period for accuracy improvements. To tackle this issue, this paper proposes a decoupling regression strategy for model upgrades. This strategy employs a data-driven approach to enhance the coupling relationships within the model, facilitating continuous improvement of simulation accuracy based on the existing model. It is capable of achieving improvements in model accuracy even in scenarios where modelers lack insight into complex process mechanisms. We validate our method by upgrading the Density Step Height (DSH) model to the Extend-DSH model to address poor erosion predictions at the 28nm node. Comparing model predictions with silicon data reveals that the Extend-DSH model aligns better with the measured data, reducing the root mean square error from 159.31Å to 6.89Å and increasing the coefficient of determination from -0.83561 to 0.6058, showcasing the effectiveness of the proposed chip-level CMP model upgrade method grounded in the decoupling regression strategy. [ABSTRACT FROM AUTHOR]

Industrial semiconductor electrodeposition plating cells require recirculation of process chemicals with consistent flow and minimal contaminants to prevent defects from developing during film deposition. This manuscript investigates how recirculation nozzle quality and nozzle machining can affect bath chemical uniformity. Computational fluid dynamics simulations are utilized to visualize bath chemical velocities based on variable nozzle conditions in four case studies. Results show that strict quality control of inlet nozzles, in conjunction with proper mounting angles, induce laminar bath flow. Greater fluid uniformity and laminar flow translate to a reduction of in-line defects and increased wafer yield. [ABSTRACT FROM AUTHOR]

Detecting wafer map anomalies is crucial for preventing yield loss in semiconductor fabrication, although intricate patterns and resource-intensive labeled data prerequisites hinder precise deep-learning segmentation. This paper presents an innovative, unsupervised method for detecting pixel-level anomalies in wafer maps. It utilizes an efficient dual attention module with a knowledge distillation network to learn defect distributions without anomalies. Knowledge transfer is achieved by distilling information from a pre-trained teacher into a student network with similar architecture, except an efficient dual attention module is incorporated atop the teacher network’s feature pyramid hierarchies, which enhances feature representation and segmentation across pyramid hierarchies that selectively emphasize relevant and discard irrelevant features by capturing contextual associations in positional and channel dimensions. Furthermore, it enables student networks to acquire an improved knowledge of hierarchical features to identify anomalies across different scales accurately. The dissimilarity in feature pyramids acts as a discriminatory function, predicting the likelihood of an abnormality, resulting in highly accurate pixel-level anomaly detection. Consequently, our proposed method excelled on the WM-811K and MixedWM38 datasets, achieving AUROC, AUPR, AUPRO, and F1-Scores of (99.65%, 99.35%), (97.31%, 92.13%), (90.76%, 84.66%) respectively, alongside an inference speed of 3.204 FPS, showcasing its high precision and efficiency. [ABSTRACT FROM AUTHOR]

It is known that the determination of the good-dice-in-bad-neighborhoods (GDBNs) has been regarded as an effective technique to reduce the value of the defect parts per million (DPPM) by identifying and rejecting the suspicious dice even though they are good in testing. Instead of examining eight immediate neighbors in a small-sized $3\times 3$ window or exploiting simple linear regression, a large-sized window can be used to recognize the broad-sighted neighborhoods and accurately infer the suspiciousness level for any given die. In this paper, the artificial neural networks (ANN)-based method can be proposed to solve the GDBN identification. Furthermore, two enhanced techniques can be further presented to improve the inference accuracy of the original ANN-based method by considering the variation of the time-dependent wafer patterns and the wafer-to-wafer relationship between two adjacent wafers. After applying the two enhanced techniques, the business profits can be improved in the new ANN-based method. Various experiments on two datasets clearly reveal the superiority of the proposed ANN-based method over the other existing methods. In addition to the reduction of the DPPM value, the new ANN-based method can achieve the 1.5X–2X better reduction in the cost of the return merchandise authorization (RMA). On the other hand, the experimental results show that the similar result can also be obtained in the other lower-yield products. By using the new ANN-based method, the relationships on bad dice cross wafers can be captured and the highly-accurate inference results can be simultaneously maintained. [ABSTRACT FROM AUTHOR]

Semantic segmentation for automated measurement in semiconductor manufacturing, specifically with wafer transmission electron microscopy (TEM) images, poses significant challenges because of the difficulty of acquisition, prevalent noise, and ambiguous object boundaries. However, prior studies focused on broadening the application of semantic segmentation for automated measurement without considering the specific intricacies of TEM images. In this study, we propose a wafer TEM images-specific semantic segmentation and transfer learning (WTEM-SST) framework to address these issues. The proposed WTEM-SST involves a pre-training stage, wafer TEM-specific data augmentation methods, and a boundary-focused loss function. The pre-training stage addresses the difficulty of collecting and annotating wafer TEM images, followed by fine-tuning for process-specific segmentation models. Our data augmentation techniques mitigate challenges related to limited training samples, lots of noise, and unclear boundaries. The boundary-focused loss makes the model more precise in boundary recognition during fine-tuning. We demonstrate that WTEM-SST outperforms conventional segmentation models, with our studies highlighting the effectiveness of the three components in WTEM-SST. [ABSTRACT FROM AUTHOR]

A compact MOSFET-C floating/grounded meminductor emulator (MIE) model is presented for high operating frequency and low power operation. The proposed MIE uses only 22 MOSFETs and two capacitors. Its performance is theoretically analyzed and rigorously verified using the Cadence Virtuoso software and hardware prototypes. The proposed MIE operates appropriately for a wide range of frequencies up to 5 MHz with $590 \mu \text{W}$ power consumption at a 180nm CMOS technology node and manifests important signature properties. The MIE layout area in 180 nm CMOS technology is $13107.5 \mu \text{m}^{2}$. To analyze the effects of statistical variations in MIE elements, extensive Monte Carlo simulations have been performed to demonstrate the robustness of the proposed MIE. For experimental validation, hardware prototypes have been developed and tested successfully. An MIE-based adaptive learning neuromorphic circuit is presented to show that it can mimic the behavioral responses of amoeba under varying environments such as temperature. [ABSTRACT FROM AUTHOR]

Statistical simulation is a necessary step in integrated circuit design since it provides a realistic picture of the circuit's behavior in the presence of manufacturing process variations. When some of the circuit components lack an accurate analytical model, as is often the case for emerging semiconductor devices or ones working at cryogenic temperatures, an approximation model is necessary. Such models are usually based on a lookup table or artificial neural network individually fitted to measurement data. If the number of devices available for measurement is limited, so is the number of approximation model instances, which renders impossible a reliable statistical circuit simulation. Approximation models using the device's physical parameters as inputs have been reported in the literature but are only useful if the end user knows the statistical distributions of those parameters, which is not always the case. The solution proposed in this work uses a type of artificial neural network called the variational autoencoder that, when exposed to a small sample of I-V curves under process variations, captures their essential features and subsequently generates an arbitrary number of similarly disturbed curves. No knowledge of the underlying physical sources of these variations is required. The proposed generative model trained on as few as 20 instances of a MOSFET is shown to precisely reproduce the period and power consumption distributions of a ring oscillator built with these MOSFETs. [ABSTRACT FROM AUTHOR]

Chemical mechanical polishing/planarization (CMP) combines physical grinding and chemical reactions to planarize the wafer surface. The complex mechanism of CMP brings great challenges to the mechanism-based modeling process. The data-driven CMP modeling process is limited by insufficient datasets. At the same time, these two types of models generally have high computational complexity. In this paper, we introduce the group method of data handling (GMDH)-type polynomial network to build the CMP model to address the above challenges. We designed and manufactured the test chip using a 28nm process. The measurement data from the test chip shows that compared with the mechanism-based CMP model, the trained CMP model based on GMDH-type polynomial network has higher accuracy and lower computational complexity, with the average simulation speed being 115x faster. Experiments based on silicon data show that this modeling method has a small demand for data, and 20 randomly selected sets of data can meet the needs for modeling the current CMP process. [ABSTRACT FROM AUTHOR]

Metal–oxide–semiconductor field-effect transistors (MOSFETs) have proven to be effective devices for rectifying electromagnetic radiation at extremely high frequencies, approximately 1 THz. This paper presents a new interpretation of the THz rectification process in the structure of an MOS transistor. The rectification depends on the nonlinear effect of the carrier dynamics. The paper shows that the so-called self-mixing effect occurs within the interface region between the source and the channel. The basic tool used numerical TCAD simulations, which offer a direct interpretation of different aspects of this interaction. The complex, 2D effect is examined in terms of its basic aspects by comparing the MOS structure with a simplified case study structure. We demonstrate that a contribution to the output-rectified voltage detectable at the drain arises from the charging of the drain well capacitance due to the diffusion of excess electrons from the self-mixing interaction occurring at the source barrier. In addition, the paper provides a quantitative description of the rectification process through the definition of the output equivalent circuit, offering a new perspective for the design of detection systems. [ABSTRACT FROM AUTHOR]

To ensure post OPC data quality, examination based on estimated resist contours at resist bottom alone is insufficient, reliable prediction of lithography performance within process window must rely on complete information of on-wafer resist 3D structures. In this regard, resist 3D structure model, in particular, the through focus resist 3D structure model, with full chip capability will be the ultimate model in demand. To develop machine learning resist 3D structure models,we have proposed the physics-based information encoding scheme, together with carefully chosen deep convolution neural network and model training strategies. Our proposed through focus resist 3D structure model is based on conditional U-net structure with first five eigen images as model’s main inputs and the focus setting as the conditional input. The average normalized cross correlation (NCC) or mean structure similarity index between ground truth and model predicted resist 3D structures can reach 0.92. With single GPU (Tesla M60), it takes 6.1ms for the model to produce resist 3D structure covering area of 1.8umx1.8 $\mu {\mathrm{ m}}$. The model is fast enough and can be engineered for full chip implementation. The model can extend the capability of detecting lithography process window aware resist loss related hotspots. [ABSTRACT FROM AUTHOR]

This paper proposes a linear regression model for scalar-valued responses and two-way functional (bivariate) predictors. Our motivation stems from the quality evaluation of products based on optical emission spectroscopy data from virtual metrology of semiconductor manufacturing. We focus on multivariate cases where the smoothness and shapes of the data vary significantly across variables. We propose a two-step solution to this problem, consisting of decomposition and prediction. First, we decompose the two-way functional data into pairs of component functions using functional singular value decomposition. Next, we build functional linear models for the decomposed functional variables and obtain the final predictor by averaging the models. Results from numerical studies, including simulation studies and real data analysis, demonstrate the promising empirical properties of the proposed approach, especially when the number of predictors is large. [ABSTRACT FROM AUTHOR]

Doing high throughput high accuracy metrology in small geometries is challenging. One approach is to build easily measurable proxy targets onto dies and make a predictive model based on those signals. We use optical Pattern Shift Response (PSR) proxy targets to build predictive models of the electrical characteristics of devices in the Back End Of Line (BEOL). Given the wide choice of PSR targets, we explore how to select combinations of them to maximise the utility of the features for building an accurate Machine Learning (ML) model; we call this approach Multiplexed Optical Metrology. We also explore the trade-off between chip area dedicated to targets and achievable accuracy. We run ML experiments using different selections of targets measured at different stages of BEOL processing: post-lithography and post-Chemical-Mechanical-Planarisation (CMP). Our results show that a) reasonable predictive performance can be achieved for a reasonable area budget; b) ML model performance across target families varies significantly, thus justifying the need for careful selection of targets; c) longitudinal measurements of targets increases accuracy for no extra area penalty; d) increasing the number of targets gives some improvement in accuracy for a dataset of this size, but relatively small compared to the increase in area budget needed. Ultimately we aim to do die-level yield prediction using these techniques. We discuss how collecting a larger dataset with appropriate yield information is the logical next step to achieving this. [ABSTRACT FROM AUTHOR]

Since the invention of transistors and integrated circuits, the development of semiconductor processes has advanced rapidly. Current microchips contain hundreds of millions of transistors. The remarkable development of semiconductors thus far has also led to difficulties in designing tightly packed lithography patterns without unwanted defects called hotspots in the manufacturing process. Therefore, research areas focusing on these problems have received much attention. In particular, predicting hotspots during the design stage is essential for high productivity in the semiconductor industry. In this study, we developed a deep learning-based SEM image generation model to predict hotspots from layout patterns at the design stage. Our model combines a segmentation network and an image-to-image translation network based on a conditional generative adversarial network in parallel. Our proposed model can predict and display potential hotspots in scanning electron microscopy images generated from given layouts. Additionally, the model leverages prior knowledge of the optical diameter to predict patterns that are prone to hotspots. Our model shows improved performance over baseline models when evaluated on real-world industrial data. [ABSTRACT FROM AUTHOR]

This paper addresses the quality control of the photolithography process in the semiconductor industry. Overlay errors in the process seriously affect the wafer yield, and cause the wafer to be forced to rework and affect the production efficiency of the equipment. We examine the current state of its process control, develop a novel overlay predict model, and verify the prediction results. This study proposes a Global Attention Generative Adversarial Networks (GAGAN) model to precisely predict the overlay error for the feed-forward data of the front layer, which is used as the important information and process parameters for the advanced process control of the current layer. Experiment results on a semiconductor shop-floor confirms that our proposed method achieves high predictive performance while maintaining extensibility and visual quality. [ABSTRACT FROM AUTHOR]

Semiconductor manufacturing demands a fast delivery of multiple gases to the tool. Hence this document provides formulas for the fluid-mechanical timescales of this delivery. This is done with a simple but realistic model of a gas-supply system, together with theory and computational-fluid-dynamic (CFD) simulations, and for representative but not comprehensive conditions relevant to etch. This timescale analysis shows that the rate-limiting process is (i) convection in the MFC-manifold tubing or (ii) convection in the tube between the flow splitter and the process chamber. This depends on (a) the lowest MFC sccm in the gas-supply system and (b) the total gas-supply-system sccm. Therefore, speeding up the gas delivery requires enhancing (i) and (ii). Moreover, (i) would become more important in view of a current trend towards smaller MFC sccms in etch. Examples on how to speed up the gas delivery and enhance the mixing are provided. The present analysis can be adapted to other conditions and manufacturing processes. [ABSTRACT FROM AUTHOR]

Elpasolites are expected to be promising photovoltaic semiconductor alternatives to lead-based perovskite semiconductors. Concern over the stability and toxicity of lead halide perovskites has led to an increase in interest in the environmental friendly elpasolite Cs2BiAgI6 (Cesium Bismuth Silver Iodide). An extensive numerical analysis of the Cs2BiAgI6 based elpasolite solar cell (ESC) model with the standard n-i-p nanostructured planar architecture ITO/TiO2/Cs2BiAgI6/CIGS/NiO/Au is presented in this article. Numerous device parameters, such as temperature, series resistance, thickness and the defect density of the dual-graded light absorber layers, electron transport layer (ETL), and hole transport layer (HTL), have all been thoroughly studied. The device numerical modeling and simulation is carried out using the well-known SCAPS-1D simulation tools (version 3.3.10). Under AM1.5G illumination, achieved a Voc of 1.2277 V, Jsc of 34.342 mA/cm2, and fill factor of 86.25% with power conversion efficiency of 36.36% through parameter optimization, which is much higher than the highest reported values found in the literature.

In this work, for the first time, a machine learning behavioral modeling methodology based on gate recurrent unit (GRU) is developed and used to model and then analyze the kink effects (KEs) in the output reflection coefficient $(S_{22})$ and the short-circuit current gain $(h_{21})$ of an advanced microwave transistor. The device under test (DUT) is a 0.25- $\mu \text{m}$ gallium nitride (GaN) high electron mobility transistor (HEMT) on silicon carbide (SiC) substrate, which has a large gate periphery of 1.5 mm. The scattering (S-) parameters of the DUT are measured at a frequency up to 65 GHz and at an ambient temperature up to 200°C. The proposed model can accurately reproduce the KEs in $S_{22}$ and in $h_{21}$ , enabling an effective analysis of their dependence on the operating conditions, bias point and ambient temperature. It is worth noticing that the proposed transistor model shows also good performance in both interpolation and extrapolation test.

Circuit design requires fast and scalable models which are compatible to modern electronic design automation tools. For this task typically analytical compact models are preferred. However, for emerging device concepts with altered conduction mechanisms like reconfigurable FETs, tunnel FETs or feedback FETs compact models are often not yet ready for circuit simulation environments. Table models help to bridge this gap, as they only require biasing values in form of current- and capacitance tables, which are then interpolated during circuit simulation. However, the conventional approach of generating the data set through DC ramps in physical simulation typically results in a large number of TCAD simulations and many redundant data points. To simplify model building, cut turnaround time and omit redundant data, this work proposes to restrict to a single transient TCAD simulation, where all required bias points for a fully functional predictive table model are provided by nesting harmonic functions. The mathematical reasoning for the selection of appropriate parameters such as frequencies and sampling rate are presented and their influence on the quality of the obtained table model is exposed. This work further presents implementation of the modeling method including validation and post-processing of the transient simulation result. The target device is an emerging reconfigurable FET (RFET) with planar structure. Finally, the performance of the obtained predictive table model of the RFET is demonstrated with circuit simulation of logic cells.

The carry-over effect is a common phenomenon in the semiconductor manufacturing process, giving the process a dynamic nature. Dynamic models are more accurate but with a consequent increase in uncertainty. Therefore, it is very important to eliminate the uncertainty and disturbance at the same time. To this end, a run-to-run (RtR) control scheme based on discrete active disturbance rejection control (DADRC) is proposed in this work. The process recipe is calculated using the state error feedback law, relying on the extended state observer (ESO) to effectively suppress the total disturbance synthesized by model uncertainty and external disturbance. Considering that tool aging often leads to drift disturbances in semiconductor manufacturing processes, a model-assisted ESO with two extended states is designed to estimate process states and total disturbance. Then an optimal observer gain is derived to minimize the estimation error. Finally, the numerical and industrial cases provide compelling evidence of the effectiveness of the proposed control scheme in suppressing tool-aging drift disturbance and a remarkable degree of tolerance towards uncertainties in the system model’s order and parameters. [ABSTRACT FROM AUTHOR]

In the semiconductor manufacturing, the manufacturing equipment is managed via the quality control (QC) in which the shape of the processed feature is checked whether it meets the specification. If the shape is out of the specification, some recipe parameters are modified so that the shape meets the specification. The calculation method of the recipe parameters depends on the know-how of the individual fab engineers, which cause difficulties in the QC. To overcome this problem, we have developed an automatic calculation method of the optimal recipe parameters with Advanced Process Control (APC) system with the stacking model method in order to solve these problems. In the development process, we have also performed comparison of two gap scoring methods. In the on-site demonstration of this system, we have further optimized the exploration method of the recipe parameters. [ABSTRACT FROM AUTHOR]

In the field of semiconductor defect inspection, detecting defects with high accuracy is possible owing to the object detection model (defect detector) composed of the deep learning model. On the other hand, the performance of the deep learning model depends highly on training data. Therefore, during the operational phase at the customer site, we need to frequently evaluate the model’s performance to deal with shifts in appearance for defects. However, frequently executing general evaluation methods is difficult at the customer site. Hence, we need a method to automatically evaluate performance. In this study, for the purpose of automatically evaluating the performance of the defect detector, we propose Positive/Negative Decision via Outlier Detection (PNDOD). The PNDOD decides on the positive of negative for each detection result based on comparing features corresponding to the detected result with statistics computed from training data. Using this method, we can calculate the estimated precision from the ratio of the estimated number of positive detections to the number of total detections, and we can evaluate the performance automatically based on it. Through experiments, we confirm the PNDOD can decide on the positive or negative with high accuracy, and we can precisely evaluate the model’s performance. [ABSTRACT FROM AUTHOR]

We propose a new formulation of the Wigner transport equation (WTE) with infinite correlation length. Since the maximum correlation length is not limited to a finite value, there is no uncertainty in the simulation results owing to the finite integral range of the nonlocal potential term. For general and efficient simulation, the proposed WTE formulation is solved self-consistently with the Poisson equation through the finite volume method and the fully coupled Newton–Raphson scheme. Through this, we implemented a quantum transport steady state and transient simulator with excellent convergence. [ABSTRACT FROM AUTHOR]

Quality monitoring is an essential element of defect detection in semiconductor manufacturing processes, but semiconductor companies use virtual metrology (VM) in addition to actual metrology to prevent productivity degradation due to the time and costs required to obtain measurements. Past VM studies aimed to predict average wafer measurement values via equipment sensor data and focused on achieving improved predictive performance by selecting or extracting important variables among high-dimensional variables such as equipment sensor data. However, the management of wafer chip quality requires not only average measurement values but also measurement value predictions for chips located at the edges, which are vulnerable to defects. In this paper, we therefore propose a graph attention (GAT) network-based VM model that predicts the measurement values of chips located at wafer edges by constructing graph data with measurement data (i.e., the measurement location information in wafers and the measurement values). To verify the performance of the proposed model, we conduct a comparative experiment with conventional machine learning methods. The experimental results show that the proposed VM model contributes to a predictive performance improvement in terms of the measurement values of chips located at wafer edges. [ABSTRACT FROM AUTHOR]

The memory module is a semiconductor product fabricated by mounting several memory chips on a printed circuit board. In the module test, which is the final step in the memory module manufacturing process, the memory module is tested if it properly functions in the end-user system environment. Then, the chips in the memory module are individually checked for defects to guarantee that the quality matches consumers’ expectations. In this study, we propose a framework to predict which chips are defective in module tests using wafer and package test data. However, several challenges must be overcome. First, two different data modalities (i.e., tabular and image data) exist, which influence defect prediction differently for different chips. Second, the module test results are highly imbalanced, with a very low defect rate. To address these challenges, we use a multimodal fusion model that integrates the two different modalities by dynamically evaluating the informativeness of each modality. In addition, we adopt a technique to modify the loss function to be Fisher consistent to minimize the balanced error rate. We demonstrate that the proposed framework can effectively predict chip-level defects in module tests using a real dataset collected from a global semiconductor manufacturing company. [ABSTRACT FROM AUTHOR]

Wafer warpage affects the resolution of photolithography, process alignment, and wafer bonding, which leads to the degradation of the device’s yield, performance, and reliability. With the development of devices, the increase of metal layers in the stack direction will worsen the warpage problem. We investigate the Wafer-to-Wafer (W2W) bonding process-induced warpage issue with experiments and a full wafer simulation. A concave wafer warpage of $70~\mu \text{m}$ is observed for a single wafer with a $7.8~\mu \text{m}$ thickness DRAM layer due to the shrinkage of the DRAM layer. In both experiments and simulation, we reveal that the W2W bonding process induces warpage 3 times the single wafer warpage value, as the deformation restriction of the DRAM layers by the thinned Si layer is weak. Furthermore, good agreement is observed between the simulated results and the measured data, which validates the simulation mode. We estimate the wafer warpage of the multi-stack wafer bonding with the validated model. As an example, the warpage of a 4-stack wafer is revealed to be 7 times the single wafer warpage value. This study provides useful information on wafer warpage in the W2W bonding process and reveals the severe warpage issue with increasing the stacked metal layers. [ABSTRACT FROM AUTHOR]

Data quality plays an important role during the training stage of machine/deep learning models. The annotation hinges on the experiences of domain experts. To acquire the expert’s knowledge in the context of machine learning, manual data labeling, a tedious and time-consuming task in supervised learning, should be given a top priority. However, the domain experts in the line of plentiful manual annotation may easily get distracted or fatigued after long-time work, causing judgment errors, mislabeling, etc. The pattern recognition of wafer defect map is investigated in this paper, the primary goal of which is to train the convolutional neural network (CNN) model through a very limited number of manually labeled data so that the trained model is capable of performing pseudo labeling. Subsequently, a self-assured adaptive ensemble learner in terms of a series of shallow neural networks is proposed to filter wafer map samples with untrusted pseudo-labels. In the result, the amount of human annotations is significantly reduced by 61% for training a highly accurate classifier. A minimum number of manually labeled data is suggested while the equally high classification performance of wafer defect pattern is maintained. For the evaluation purpose, the proposed self-assured learning is compared with the confidence learning. [ABSTRACT FROM AUTHOR]

Owing to global competition, integrated circuit (IC) design houses are facing challenges in the optimal use of capacity and resources to fulfill customer demands and maximize profit. A hybrid make-to-stock (MTS) and make-to-order (MTO) model is generally used. Wafer procurement is made according to customers’ long-term demand forecast based on MTS. Limited wafer fab resources and back-end capacity are first allocated to on-hand orders and then to forecast demand. In production planning, several factors need to be considered to determine the production quantity and inventory level, such as the material, capacity, substitute, technical constraint, and order tardiness. This study considers a typical multi-stage supply chain network of semiconductor back-end production with turnkey service for IC design houses. The objective is to maximize the total profit with the constraints of equipment capacity, the flexibility of substitutes, and the usage of the turnkey mode. The problem is formulated with a mixed-integer programming model and solved using two novel heuristic algorithms: a product-based decomposition (PD_SCP) with profit-based criteria and a Lagrangian decomposition combined with the product-based decomposition (LD-SCP) method. Using the LD-SCP algorithm takes a long time but results in a great solution. Sensitivity analysis is conducted to investigate the impact of different parameters on production cost and total profit. [ABSTRACT FROM AUTHOR]

Defect patterns exhibited in wafer bin maps (WBMs) can provide essential clues about critical process failures to field engineers. In modern manufacturing processes, the automatic WBM defect pattern classification is critical for yield improvement. Although it is difficult to collect sufficient labels while a lot of unlabeled data is given, most existing studies have mainly used only labeled WBM data. Moreover, the unlabeled out-of-distribution (OOD) WBMs are inevitably collected. It degrades the performance of semi-supervised models. To this end, we propose a method for safe wafer bin map classification with self-supervised contrastive learning (SWaCo) to effectively exploit the unlabeled data with OOD. We propose a loss function to utilize label information in the pre-training step to learn more suitable representations for the downstream WBM classification task. The negative labeled examples of the same class as the anchor are used for additional positive examples. Moreover, we investigate proper data augmentation for WBM self-supervised contrastive learning. To evaluate the performance and the applicability of the proposed method, experiments are conducted on a public benchmark WBM dataset, WM-811K. The results demonstrate that the proposed method achieves better classification accuracy than existing methods, especially when only a small amount of class information is given. [ABSTRACT FROM AUTHOR]

Cycle time, which is of order of ten weeks for most products in semiconductor wafer fabrication facilities (wafer fabs), must be explicitly considered in production planning models. Cycle times depend nonlinearly on the resource workload in a wafer fab. Different data-driven (DD) production planning formulations are studied in this paper. Such formulations are based on a set of system states representing the congestion behavior of a wafer fab with work in process (WIP) and resulting output levels. Different WIP-output relations in the DD formulations are investigated. In addition, different methods are proposed to gather representative sets of system states. The DD formulations are compared with the Allocated Clearing Function (ACF) formulation with respect to profit and cost values using simulation models of a scaled-down and a large-sized multi-product wafer fab, respectively. The simulation results show that some DD variants are able to outperform the ACF formulation under several experimental conditions. [ABSTRACT FROM AUTHOR]

There are mainly two types of wafer map failure pattern recognition, i.e., traditional classification based and deep learning based approaches. Traditional classification usually needs feature engineering, and deep learning requires lower human intervention and feature engineering. The joint requirement is noise filtering and identical input dimension size. Feature engineering and dimension resizing are artificial work and vary from study to study. In our study, we proposed an image hashing based wafer map resizing and pattern information retrieval framework. Traditional classification methods and CNN are employed for the wafer map failure pattern recognition. The experiments show that the image hashing based framework is the more appropriate method when compared to feature extraction and image resizing methods. We also found that proper input data manipulation can result in acceptable performance whether the used method is traditional classification algorithms or CNN. [ABSTRACT FROM AUTHOR]

This paper presents an improved multi-level simulation framework for 2D material-based nanoelectronics, which expands from device simulation, physics-based compact modeling, and circuit benchmarking, using the germanane (GeH) metal-oxide-semiconductor field-effect transistors (MOSFETs) as an example. The device simulation employs the non-equilibrium Green's function method to obtain the characteristics of 2D GeH MOSFETs for both n-type MOSFETs and p-type MOSFETs. A compact model based on the MIT virtual source model is then revised to capture the unique behaviors of 2D-material-based MOSFETs, including voltage dependency of virtual source velocity and drain-induced barrier lowering, as well as the effect of quantum capacitance. HSPICE circuit simulations are performed to analyze and optimize CMOS digital benchmark circuits. The case study demonstrates that 2D material-based transistors favor a different range of supply voltage and threshold voltage than their silicon counterpart, to achieve the optimal energy-delay product. The impact of contact resistance is also analyzed using the proposed framework. This study offers a seamless multi-level simulation approach to bridge the gap between nanoelectronics and circuit behavior, thereby advancing the understanding of materials, devices, and circuits comprehensively. The framework tailored for GeH MOSFETs provides accurate device-circuit co-optimization which can be easily extended to devices based on other 2D materials. [ABSTRACT FROM AUTHOR]

This article proposes a novel dopingless ternary FET (DLT-FET) composed of the longitudinal metal-source/InAs-channel/InAs-drain structure for compact implementation of the ternary inverter. A single DLT-FET mixes two types of carrier transport mechanisms: 1) according to the concept of charge plasma, the Band-to-Band tunneling (BTBT) can occur at channel/drain interface by metal work function engineering; 2) Schottky Barrier tunneling (SBT) at the source/channel interface. The mechanism of the DLT-FET is verified with the help of TCAD tools. The simulation results revealed that both N/P-type DLT-FETs have a flat drain current characteristic around VG = 0.5VDD, where the VG-independent IBTBT dominates the drain current. The stable third output voltage can be obtained through the voltage dividing, while both the ISBT and IBTBT generate the other voltage levels of 0 V and 1.0VDD. Furthermore, the effects of a series of key device parameters on DLT-FETs and ternary inverter performance are evaluated. The ternary inverter can be implemented by simply replacing two transistors with N/P-type DLT-FETs in a conventional binary inverter and selecting appropriate device parameters for exhibiting comparable transfer characteristics. [ABSTRACT FROM AUTHOR]

A thermally agitated device model of spin-transfer torque magnetic tunnel junction (STT-MTJ) based on the Fokker-Planck equation is proposed which is implemented into HSPICE by using Verilog-A. We compared different techniques of finite difference method (FDM) and analyzed the impact of the solvers on computational efficiency and accuracy. A framework is proposed which traces dynamics of a particular STT-MTJ's angle between the magnetic moments of the free and the pinned layers and makes the model applicable to a wide range of circuits. The model was applied to the 4T2MTJ memory cell array and a leaky integrate-and-fire (LIF) neuron circuit to validate the stochastic switching characteristic and the angle prediction function. In the memory array simulations, the CPU time consumption for this model is 1/30 of the model which is based on the stochastic Landau-Lifshitz-Gilbert-Slonczewski equation. [ABSTRACT FROM AUTHOR]

Cryogenic semiconductor device models are essential in designing control systems for quantum devices and in benchmarking the benefits of cryogenic cooling for high-performance computing. In particular, the saturation of subthreshold swing due to band tails is an important phenomenon to include in low-temperature analytical MOSFET models as it predicts theoretical lower bounds on the leakage power and supply voltage in tailored cryogenic CMOS technologies with tuned threshold voltages. Previous physics-based modeling required to evaluate functions with no closed-form solutions, defeating the purpose of fast and efficient model evaluation. Thus far, only the empirically proposed expressions are in closed form. This article bridges this gap by deriving a physics-based and closed-form model for the full saturating trend of the subthreshold swing from room down to low temperature. The proposed model is compared against experimental data taken on some long and short devices from a commercial 28-nm bulk CMOS technology down to 4.2 K. [ABSTRACT FROM AUTHOR]

A leap towards deriving a robust-compact model for ferroelectric-FET (FeFET) oscillator based spiking neurons has been developed. The compact model can capture and emulate neurons that exhibit both excitatory and inhibitory coupled dynamical behaviour, native to cortical neurons. The proposed model can reliably mimic neuronal dynamics for a broad-spectrum of FeFETs when, factored with appropriate validation of numerical simulations and physics-based models. The emulation of neuronal attributes based on FDSOI FeFET having qualitative agreement with previously reported data. The robustness of this analytical model has been investigated by tuning with ferro-dielectric (Fe) materials i.e., zirconium-doped HfO2 (HZO) and silicon-doped HfO2 (HSO) for mimicking the neurons. In continuance, the model is examined for emulating the cortical neurons by altering the inhibition (high-VGF) and excitation (low-VGF) inputs with a suitable frequency of operation for spiking neurons. [ABSTRACT FROM AUTHOR]

In the processor-memory separated von-Neumann computation paradigm, the “memory-wall” effect becomes critical due to large access latency and tremendous amount of data movement. In this work, we pursue cryogenic temperature based memory design and focus on spin-transfer-torque magnetoresistive random access memory (STT-MRAM) at 77-Kelvin (achieved with low-cost liquid nitrogen). Cryogenic compact model and its related cryogenic bit-cell are investigated, based on 77 K experiment data of magnetic tunnel junction (MTJ) and CMOS transistor. Compared with the simulated room temperature results, 70% reduction of sensing latency can be obtained at 0.7 V supply voltage, whereas writing latency and yield performance are significantly degraded. In order to overcome the above drawbacks, a novel joint trimming system is proposed including a build-in-self-test (BIST) block and a string of multi-stage level shifters (LS). A case study is executed with in-MRAM computing (IMC). Results show that cryogenic IMC with write trimming provides performance improvements of 33% on average, and concurrently reduces memory energy consumption by 70% on average. The proposed 77 K cryogenic design method can be further applied to other energy constrained applications. [ABSTRACT FROM AUTHOR]

In this study, we use NEGF quantum transport simulations to study the fundamental detection limit of ultra-scaled Si nanowire FET (NWT) biosensors. A N-doped NWT is found to be more sensitive for negatively charged analytes as explained by the nature of the detection mechanism. Our results predict threshold voltage shifts due to a single-charge analyte of tens to hundreds of mV in air or low-ionic solutions. However, with typical ionic solutions and SAM conditions, the sensitivity rapidly drops to the mV/q range. Our results are then extended to the detection of a single 20-base-long DNA molecule in solution. The impact of front- and/or back-gate biasing on the sensitivity and limit of detection is studied and a signal-to-noise ratio of 10 is predicted. Opportunities and challenges to reach down to single-analyte detection in such systems are also discussed, including the ionic and oxide-solution interface-charge screening and ways to recover unscreened sensitivities. [ABSTRACT FROM AUTHOR]

We notice that the compact resist model can be mapped to a simple CNN (convolutional neural network): convolutional layer corresponds to convolutions between input images and resist kernels, and a fully connected layer can model the formation of weighted sum of convolutions followed by the comparison to threshold to determine the development. Resist kernels correspond to convolution filters, so they can be obtained through CNN training, which is a key motivation. A number of challenges are identified and solutions are proposed: (1) We demonstrate a CNN structure that can be mapped to a resist model. (2) Convolution filters are large images and cannot be trained with standard methods. Adaptive learning rate and gradient clipping are applied. (3) Convolution filters may easily be overfitted if training data is not enough. We apply gradient descent for fast initialization of filters. (4) CNN is trained with printability of image pixels rather than CD values. Extraction of pixels and their sampling are addressed. The number of kernels and the number of convolutions can greatly be reduced through the proposed method: 22 standard kernel functions are reduced to only 4 optimized ones, which contributes to 44% faster lithography simulation yet accuracy is improved by 10%. [ABSTRACT FROM AUTHOR]

With the downscaling of semiconductor feature size, single wafer wet etching has shown better within-wafer and wafer-to-wafer uniformity. According to previous research and analysis, liquid film thickness has a close relationship with etch loss, and numerical simulations have been applied to calculate liquid film thickness with fixed nozzle dispensing. This study investigated liquid film thickness with scanning nozzle processing and a modeled aqueous tetramethylammonium hydroxide (TMAH) poly etching method. A modified shallow water equation was used to calculate the liquid film thickness under nozzle scanning conditions. Additionally, the liquid film thickness and liquid velocity were coupled with a chemical reaction kinetic model to calculate the TMAH poly etching reaction rate on the wafer surface. Scan dispensing etch loss was calculated by integrating the reaction rate. Both the experimental and simulation results showed that the scan speed can affect within-wafer etch loss profile and that a fast scan speed could increase etch loss in wafer donut area. The simulation model could be a predictive tool for improving within-wafer etching profile. [ABSTRACT FROM AUTHOR]

During the semiconductor manufacturing process, predicting the yield of the semiconductor is an important problem. Early detection of defective product production in the manufacturing process can save huge production cost. The data generated from the semiconductor manufacturing process have characteristics of non-normal distributions, random missing patterns and high missing rate, which complicate the prediction of the yield. We propose the Dirichlet Process - Naive Bayes model (DPNB) that can simultaneously impute missing values and address classification problems. Since the DPNB is based on the infinite Gaussian mixture model, it can estimate complex data distributions and make predictions for missing datasets with some missing patterns due to nice properties of the Gaussian distribution. The DPNB also performs well for high missing rates since it uses all information of observed components. Experiments on various real datasets including semiconductor manufacturing data show that the DPNB has better performance than state-of-the-art methods in terms of predicting missing values and target variables as percentage of missing values increases. [ABSTRACT FROM AUTHOR]

In current semiconductor manufacturing, limited raw trace data pertaining to defective wafers make fault detection (FD) assignments extremely difficult due to the data imbalance in wafer classification. To mitigate, this paper proposes using a variational autoencoder (VAE) as a data augmentation strategy for resolving data imbalance of temporal raw trace data. A VAE with few defective samples is first trained. By means of extracting the latent variables that characterize the distribution of the defective samples, we make use of the statistical randomness of the latent variables to generate synthesized defective samples via the decoder scheme in the trained VAE. Two data representations and VAE modeling strategies, concatenation of multiple and individual raw trace data as the input of the VAE during the training stage, are investigated. A real-data plasma enhanced chemical vapor deposition (PECVD) process having only few defective samples is used to illustrate the performance enhancement to wafer classification arising from the proposed data augmentation framework. Based on the computational comparisons between noted classification models, the proposed generative VAE model via the individual strategy enables the adaptive boosting (AdaBoost) classifier to achieve perfect performances in every metrics if the 80% and 100% over-sampling ratios are adopted. [ABSTRACT FROM AUTHOR]

In this paper, we present a detailed experimental investigation of high-temperature data retention in 3D floating-gate NAND Flash memory arrays. Data reveal that charge detrapping from the cell tunnel oxide and depassivation of traps in the string polysilicon channel are the physical mechanisms resulting in the most relevant long-term reliability issues for the memory array. On one hand, the two mechanisms give rise to threshold-voltage $(\mathbf {V_{T}})$ instabilities with similar activation energy and comparable magnitude on fresh devices. On the other hand, polysilicon trap depassivation displays a negligible strengthening with cycling and a more marked dependence on the cell $\mathbf {V_{T}}$ level during data retention with respect to charge detrapping. Results must be carefully considered in the reliability assessment of all state-of-the-art and future 3D NAND Flash technology nodes.

Scalable small signal and noise modeling for 90nm InP high electron mobility transistor (HEMT) is proposed in this paper. Analytical expressions for the noise parameters of the intrinsic part are derived from an accurate small signal and noise equivalent circuit model. The experimental and theoretical results show that at the same bias condition, good scaling can be achieved between the HEMTs with different gate widths. Model verification is carried out by comparison of measured and simulated S-parameters up to 325 GHz and noise parameters up to 40GHz. Good agreement is obtained for 90 nm gate-length devices of gate widths including $2\times 15\,\,\mu \text{m}$ , $2\times 20\,\,\mu \text{m}$ and $2\times 25\,\,\mu \text{m}$ gate width (number of gate fingers $\times $ unit gate width $\times $ cells). The proposed model can be used to predict the S-parameters and noise performance of HEMTs with different geometry accurately.

Differential inverters develop the PWM of internal DC-DC modules by correlating fundamental frequency of load with high switching frequency to maintain inherent characteristic operation and achieve pure higher/lower AC output voltage with smaller size. However, no generalized design method applicable for many DC-DC modules topologies has been demonstrated up till now, to realize efficient differential inverter with accurate power loss prediction. Consequently, a generic design process utilizing one parameter (modulation index gain) as well as new power losses modeling for all elements, such as switching devices, inductors, capacitors, and extra, are proposed in this paper. Novel decoupling between both operational frequencies through a two-stage calculation algorithm is the main attractive feature where, all losses are calculated based on the switching frequency of DC-DC modules then all losses are averaged accordingly over fundamental frequency. Doing this obtains RMS currents in terms of actual duty cycle and other parameters without adding complex mathematics at various PWM schemes, such as SVMS, CMS and DMS. The proposed work is simultaneously employed for many DC-DC modules topologies and verified in simulation and experiments using 0.7kW 50kHz isolated SEPIC-based DC-DC modules, as a case study. The error into actual duty cycle is decreased from $\mathrm {5.19\% }$ to $\mathrm {2.47\% }$ in the case of CMS at different power ratings. Further, it is reduced to $\mathrm {2.64\% }$ and $\mathrm {1.86\% }$ for SVMS and DMS, respectively. Finally, smart foretelling of power loss in each element of differential inverter is considered crucial for future efficiency improvement.

THz detection in a silicon structure can be an effective instrument not only for image detection, and material and gas sensing, but also for communications. Next-generation 6G communications assume the possibility of achieving a large-band transmission, using free space propagation with THz carriers. This possibility relies on the availability of an effective, low-cost detector technology. THz detection by self-mixing can provide an effective amplitude demodulation of the incoming carrier, with antennas directly fabricated on the chip. In this case, the speed of the detectors represents a crucial point in the definition of the bandwidth whereby several GHz are indeed required by the communication systems. The self-mixing process is intrinsically very fast, since it depends on the non-linear interaction of the radiation with the majority carriers inside the semiconductor structure. In this paper, we evaluate analytically the time dependence of the onset of the rectified voltage. A potential propagation along the detector channel follows the self-mixing rectification, accompanied by the charging of the parasitic capacitances of the structure. A numerical simulator can easily evaluate the delay due to this propagation along the structure, but the transient of the true origin of the signal, i.e., the establishment of the self-mixing voltage, at the current time, can be only inferred by analytical approach. In this work, we use the model developed for the THz rectification in the depletion region of an MOS capacitance to develop a transient model of the formation of the characteristic self-mixing charge dipole, and of the generation of the rectified potential. Subsequently, we show by TCAD simulations the propagation of the effect on the semiconductor structure, which surrounds the rectifying barrier, and evaluate the overall time response of a detector. [ABSTRACT FROM AUTHOR]

This article investigates a look-ahead transport dispatching algorithm for the Automated Material Handling System (AMHS) of a semiconductor manufacturing facility. We consider two types of information: the estimated arrival time of upcoming transports of lots and the time required for an occupied vehicle to become idle. A Mixed Integer Linear programming model has been proposed to minimize the assignment (waiting) time of transport missions. Due to the complexity of the problem, three heuristics have been developed and tested on industrial data. The experiment simulation has been conducted by using a simulation model of a real semiconductor factory. The tests have shown the relevance and the effectiveness of the look-ahead dispatching algorithm. [ABSTRACT FROM AUTHOR]

The high thermal budget of three-dimensional NAND Flash (3D NAND Flash) is the key issue limiting the increase in vertical integration. The main purpose of this article is to design a local and high temperature annealing function to reduce the thermal budget and gain a high activation rate without diffusion at a target depth to improve the performance of 3D NAND Flash devices by laser annealing with green wavelength. The method of nanosecond pulse laser annealing (ns-PLA) for amorphous silicon (a-Si) crystallization and activation has been proven, and this method has the benefits of a low thermal budget and controllable heating. According to previous experiments, one of the important results is that ns-PLA with high energy can provide a high temperature that reaches the melting point of a-Si and obtain a deep and monocrystal-like silicon channel through liquid phase crystallization in 3D NAND applications and obtain a higher activation rate. These results cast emerging light on low thermal budget processes based on ns-PLA in 3D NAND flash for future architecture such as Xtacking architecture, and have significant ramifications for impurity activation rates and reducing channel leakages. [ABSTRACT FROM AUTHOR]