Search

We specialize the Control Volume Finite Element Method (CVFEM) for the solution of the Poisson-Boltzmann and Poisson-Nernst-Planck (also known as Poisson-drift-diffusion) system of equations on unstructured 3D meshes describing nanoelectronic biosensors operated in the DC and AC small signal regimes. We provide the exact analytical expressions for volume and surface integrals derived by means of a linear coordinate transformation and show that they are both accurate and efficient, especially on coarse grids. Being of great importance for the chosen application, the conservation property is investigated and we show that, for the CVFEM to be conservative, the calculations on the boundary have to be performed with special care. CVFEM is carefully compared to the Galerkin Finite Element Method (GFEM) from the point of view of the underlying theory, implementation and solution calculation. The simulation tool is used to evaluate the response of a real nanoelectrode-based biosensor array to the introduction of small nanoparticles. [ABSTRACT FROM AUTHOR]

Highlights: [•] DC and AC solver for biomolecules immersed in an electrolyte between electrodes. [•] 1D analytical model describing the electrolyte response to AC signals. [•] At high frequencies, the change in the nanoelectrode capacitance tends to a constant. [•] This constant is independent of the salt concentration. [•] This constant is weakly affected by the nanoparticle charge or position. [ABSTRACT FROM AUTHOR]

This paper reports the experimental evidence of anomalous electrical characteristics of large test structures for the characterization of both silicon-oxide-nitride-oxide-silicon (SONOS) and MOS gate stacks featuring nitride caps. The anomaly has been studied on devices featuring different layouts and it has been attributed to the property of silicon nitride layers to block the diffusion of hydrogen used for the passivation of the Si/SiO2 interface dangling bonds. Since the hydrogen passivation can occur only from the lateral sides of the device, our findings imply restrictions on the dimensions and on the layout of the test structures used to study the electrical properties of the gate stacks in SONOS or in large MOS devices featuring protective nitride caps. [ABSTRACT FROM AUTHOR]

This paper presents a novel non-volatile memory cell architecture (BipFlash), which improves remarkably injection efficiency over that obtained with conventional channel hot-electron programming. The cell concept is validated by means of numerical device simulations including accurate Monte Carlo analysis of hot carrier transport and injection in the floating gate. Design strategies to achieve optimum device performance and possible solutions for cell layout and array organization are also discussed. We show that the superior performance of BipFlash in terms of injection efficiency can be traded to achieve either very low voltage, low power or high-speed operation. [Copyright &y& Elsevier]

Presents a study which analyzed the metal-oxide semiconductor field-effect transistors (MOSFET) in the so-called channel initiated secondary electron injection (CHISEL) regime. Development and validation of a Monte Carlo model of the phenomenon; Channel length dependence of CHISEL gate currents; Impact of the basic device parameters on the channel length dependence of CHISEL injection efficiency.

Neuron and neural network studies are remarkably fostered by novel stimulation and recording systems, which often make use of biochips fabricated with advanced electronic technologies and, notably, micro- and nanoscale complementary metal-oxide semiconductor (CMOS). Models of the transduction mechanisms involved in the sensor and recording of the neuron activity are useful to optimize the sensing device architecture and its coupling to the readout circuits, as well as to interpret the measured data. Starting with an overview of recently published integrated active and passive micro/nanoelectrode sensing devices for in vitro studies fabricated with modern (CMOS-based) micro-nano technology, this paper presents a mixed-mode device-circuit numerical-analytical multiscale and multiphysics simulation methodology to describe the neuron-sensor coupling, suitable to derive useful design guidelines. A few representative structures and coupling conditions are analysed in more detail in terms of the most relevant electrical figures of merit including signal-to-noise ratio. This article is part of the theme issue 'Advanced neurotechnologies: translating innovation for health and well-being'. [ABSTRACT FROM AUTHOR]

Focuses on the issues of low-voltage hot carriers and soft-programming lifetime determination in metal-oxide semiconductor field-effect transistors (MOSFET) and flash memory cells. Gate and substrate current of devices; Experiments and Monte Carlo simulations on the devices; Conclusion.

Analyzes the phenomenon of gate current enhancement upon application of a substrate voltage. Techniques for substrate separation; Device technology and experimental details; Application of substrate enhanced electron injection.

Analyzes the physical mechanisms that leads to proportionality between gate and substrate in substrate enhanced electron injection (SEEI). Physical considerations; Monte Carlo simulations performed; Proximities of secondary generated hot electron injection.

Addresses the problem of hot-carrier degradation and lifetime monitoring in silicon-on-insulator (SOI) metal oxide semiconductor field-effect transistors (MOSFET). Devices fabrication and experimental setup; Emission characteristics; Correlation between emission and degradation; Conclusions.

Investigates the use of hot carrier luminescence (HCL) measurements as a mean for the verification of carrier energy distribution functions in submicron silicon devices. Device fabrication and measurements; Analysis of the experimental results; Description of the luminescence model and comparison of the results of the simulations with experiments; Conclusions.

Carrier trapping/detrapping from/to the gate into dielectric traps is often neglected when modeling noise in MOSFETs and, to the best of our knowledge, no systematic study of its impacts on scaled devices is available. In this article, we show that this trapping mechanism cannot be neglected in nowadays aggressively scaled gate dielectric thicknesses without causing errors up to several orders of magnitude in the estimation of the drain current noise. The noise generation mechanism is modeled analytically and then analyzed through the use of 2-D and 3-D TCAD simulations of scaled MOSFETs with different architectures and channel/gate-stack materials. The results provide new insights for technology and device designers, highlight the relevance of the choice of the gate metal work function (WF) and the role of valence band electron trapping at high gate voltages. [ABSTRACT FROM AUTHOR]

In this article, we separately investigate the role of electric field and device self-heating (SHE) in enhancing the charge emission process from Fe-related buffer traps (0.52 eV from Ec) in AlGaN/GaN high electron mobility transistors (HEMTs). The experimental analysis was performed by means of drain current transient (DCT) measurements for either: 1) different dissipated power (PD,steady) at constant drain-to-source bias (VDS,steady) or 2) constant PD,steady at different VDS,steady’s. We found that: 1) an increase in PD,steady yields an acceleration in the thermally activated emission process, consistently with the temperature rise induced by SHE and 2) on the other hand, the field-effect turned out to be negligible within the investigated voltage range, indicating the absence of the Poole–Frenkel effect (PFE). A qualitative analysis based on the electric field values obtained by numerical simulations is then presented to support the interpretation and conclusions. [ABSTRACT FROM AUTHOR]

The six papers in this special section are extended papers from the 2011 International Conference on Microelectronic Test Structures, held in Amsterdam, The Netherlands. The papers cover new advances in variation and stress characterization for complementary metal-oxide-semiconductor technology, improved parameter extraction techniques, and new test structures for process, doping, and temperature characterization. [ABSTRACT FROM AUTHOR]

• The 1/f noise formula used to extract trap densities in MOSFETs is critically re-examined. • The formula agrees with NMP models for thick dielectric devices at room temperature. • The NBT is underestimated when extracting traps from thin ILs. • The NBT extracted from thin-dielectric devices has errors up to 100×. • Neglecting gate trapping and the electrostatic scaling factor causes these errors. Noise spectroscopy is a powerful non-destructive technique to characterize the quality of gate dielectrics in MOSFETs. Trap densities are routinely extracted by fitting the 1/f part of the drain current noise spectrum with a widely known analytical expression containing several approximations within. This paper compares this 1/f noise analytical expression with microscopic simulations, evaluates its accuracy under different scenarios, and highlights when the main assumptions fall short. It is found that the expression agrees well with non-radiative multi-phonon (NMP) models at room temperature for devices featuring a thick dielectric. However, the formula fails to correctly predict the noise of nowadays aggressively scaled devices, because it neglects trapping/de-trapping with the gate electrode and the electrostatic charge scaling of the traps due to their distance from the channel. [ABSTRACT FROM AUTHOR]

This paper investigates by simulation the response of a nanoelectrode capacitive biosensor to single and double strands of DNA/PNA and up to frequencies well above the electrolyte dielectric relaxation limit. The expected change in capacitance both for an idealized two electrodes system with 2D cylindrical symmetry and a complex nanoelectrode array, where the biomolecule is represented by a dielectric and charged rod, is calculated for different positions and orientations of the strand. DNA and PNA hybridization is also considered. The results provide indications on optimum detection conditions for admittance based DNA biosensors. [ABSTRACT FROM AUTHOR]

A large number of technology applications still remain where Artificial Intelligence techniques, carefully tailored to the specific application needs, could provide performance benefits to hardware technologies. One such area is biosensing with innovative complementary-metal–oxide–semiconductor nanocapacitor arrays. These sensors operate as powerful imaging platforms but, despite the advancements in the field, the knowledge necessary for precise and robust interpretation of their response to analytes is still largely lacking. In this work, we leverage the ability of Machine Learning methods for computer vision to construct precise and robust models in different operation scenarios. By recognizing the similarity between multifrequency capacitance maps and multispectral images, we identified optimal Machine Learning algorithms to accurately estimate the size of analytes measured by the nanoelectrode array biosensor. As a relevant case study, we focus on measurements of the radius of dielectric spherical nano-particles dispersed in deionized water and phosphate buffer saline. The performance of large, established image-processing neural networks is compared to that of less complex, purposely developed ones. Sizable training data sets are generated by accurate finite element simulations of the sensor response combined with measured data. An excellent accuracy, comparable to traditional sizing technology, is achieved for the task of providing a quantitative measure of the nano-particle radius when the latter is comparable to the pitch of the pixels in the array. We report a size median error below 15% in all scenarios when a few percent of measured data samples is added to the simulation-based training data set. [ABSTRACT FROM AUTHOR]

We derive a complete set of expressions for the MOSFET gate and drain power spectral densities due to elastic and inelastic trapping/detrapping of channel carriers into the gate dielectric. Our calculations explain trapping/detrapping noise (TDN) in various FET operating regions and highlight trap’s position-dependent terms, often neglected in the literature, which are instead important for devices with thin gate dielectrics. Furthermore, we show that TDN has a contribution to the gate current noise, correlated with the drain current fluctuations and we highlight the role of the transfer function between channel charge fluctuations and drain current on the noise characteristics. The model expressions are carefully validated by comparison with 2-D and 3-D TCAD simulations of scaled MOSFETs with different architectures (bulk, fully depleted-silicon-on-insulator (FD-SOI), FinFET), channel, and gate materials. Besides shedding new light on TDN, the results could enable trap density extraction from experimental samples with improved accuracy and pave the way to complete and accurate compact models for TDN in MOSFETs. [ABSTRACT FROM AUTHOR]

The aim of this paper is to establish a well-defined theoretical background in which the kT-layer concept and the empirical expression of the backscattering coefficient introduced by Lundstrom and co-workers to describe the role of scattering in nanoscale devices under high-field conditions and quasi-ballistic transport regime are derived analytically. To this purpose, one-dimensional (1-D) Boltzmann transport equation is solved in the framework of a ‘relaxation length’ approximation, leading to a set of drift-diffusion like transport equations. This set of equations is then solved in a template 1-D structure (with a linear potential-energy profile), leading to an analytical expression for the back-scattering coefficient, which is equal, in the limit of low- and high-electric fields, to the formulas proposed by Lundstrom et al. This approach allows us to identify the exact assumptions and qualitative validity limits of these formulas. [ABSTRACT FROM AUTHOR]

In this paper, we have extensively investigated the silicon thickness dependence of the low field electron mobility in ultrathin silicon-on-insulator (UT-SOI) MOSFETs operated both in single- and in double-gate mode. A physically based model including all the scattering mechanisms that are known to be most relevant in bulk MOSFETs has been extended and applied to SOI structures. A systematic comparison with the measurements shows that the experimental mobility dependence on the silicon thickness (T[subSI]) cannot be quantitatively explained within the transport picture that seems adequate for bulk transistors. In an attempt to improve the agreement with the experiments, we have critically rediscussed our model for the phonon scattering and developed a model for the scattering induced by the T[subSI] fluctuations. Our results suggest that the importance of the surface optical (SO) phonons could be significantly enhanced in UT-SOI MOSFETs with respect to bulk transistors. Furthermore, both the SO phonon and the T[subSI] fluctuation scattering are remarkably enhanced with reducing T[subSI], so that they could help explain the experimental mobility behavior. [ABSTRACT FROM AUTHOR]

A novel concept and a fabrication technique of strained SiGe-on-insulator (SGOI) pMOSFET are proposed and demonstrated. This device has an ultrathin strained SiGe channel layer, which is directly sandwiched by gate oxide and buried oxide layers. The mobility enhancement of 2.3 times higher than the universal mobility of conventional universal Si pMOSFETs was obtained for a pMOSFET with 19-nm-thick Si[sub 0.58]Ge[sub 0.42] channel layer, which is formed by high-temperature oxidation of a Si[sub 0.9]Ge[sub 0.1] layer grown on a Si-on-insulator (SOI) substrate. A fully depleted SGOI MOSFET with this simple single-layer body structure is promising for scaled SOI p-MOSFET with high current drive. [ABSTRACT FROM AUTHOR]

Presents a critical analysis on the origin of majority and minority carrier substrate currents in tunneling metal-oxide semiconductor (MOS) capacitors. Simulation procedure and model description; Model verification; Emission spectra in MOS capacitors; Conclusions.

Analyzes metal oxide semiconductor field-effect transistor (MOSFET) degradation in the regime of hot carrier injection enhanced by substrate bias substrate-enhanced gate current. Details of substrate-enhanced gate currents; Degradation induced by Channel-Initiated Secondary Electron and channel hot electron in n-MOSFET; Illustration of charge-pumping current curves of a virgin and stressed n-MOSFET.

Part I. Analyzes in detail the generation of interface states and stress-induced leakage current (SILC) during channel hot electron stress experiments in the context of a possible hydrogen/deuterium isotope effect. Device technology and experimental techniques; Possible correlation between interface states and SILC generation; Assessment of the mechanisms responsible for thin oxide degradation.

Part II. Estimates a reasonable boundary for the efficiency of a possible hydrogen release (HR) mechanism. Measurements of stress-induced leakage current (SILC) produced by Fowler-Nordheim stress measurements; SILC generation efficiency; Direct measurements of a hole current; Post-stress trapped charge characterization.

This paper presents a new model for the surface roughness (SR) limited mobility in MOS transistors. The model is suitable for bulk and thin body devices and explicitly takes into account the non linear relation between the displacement Δ of the interface position and the SR scattering matrix elements, which is found to significantly influence the r.m.s value (Δrms) of the interface roughness that is necessary to reproduce SR-limited mobility measurements. In particular, comparison with experimental mobility for bulk Si MOSFETs shows that with the new SR scattering model a good agreement with measured mobility can be obtained with Δrms values of about 0.2 nm, which is in good agreement with several AFM and TEM measurements. For thin body III-V MOSFETs, the proposed model predicts a weaker mobility degradation at small well thicknesses (Tw), compared to the Tw6 behavior observed in Si extremely thin body devices. [ABSTRACT FROM AUTHOR]

This work demonstrates that when inelastic tunneling between oxide traps and semiconductor bands is considered, the traps with energy aligned to the semiconductor bandgap play a significant role in the frequency dispersion of the capacitance–voltage (C–V) and conductance–voltage (G–V) characteristics of metal–oxide–semiconductor (MOS) systems. The work also highlights that a nonlocal model for tunneling into interface states is mandatory to reproduce experiments when carrier quantization in the inversion layer is accounted for. A model, including these ingredients, is used to evaluate the energy and depth distribution of oxide traps in a n-In0.53Ga0.47As/Al2O3 MOS system and is able to accurately fit the C–V frequency dispersion from depletion to weak inversion. The oxide trap distribution determined from the C–V response predicts the corresponding G–V dispersion with frequency. [ABSTRACT FROM AUTHOR]

Dielectric defects play a crucial role in the reliability of MOSFETs. In this study, we aim to gain a deeper understanding of dielectrics' degradation by correlating the effective interface (N 2 D) and bulk (N B T) trap densities extracted by different characterization techniques (I-V, charge pumping, and 1/f noise) under different electrical stress conditions. Additionally, we establish an empirical relation between the increase of N B T (estimated via 1/f noise measurements) and N 2 D , e f f (estimated through the monitoring of threshold voltage shift) after stress. This relation is useful to calculate the expected increase in 1/f noise from the V T degradation models typically made available by the foundries to circuit designers. • Comparison of electrical techniques to extract trap densities under diverse stress conditions. • 1/f noise increases with stress only in the carrier number fluctuation regime (i.e., at low gate voltage overdrives). • We derive an empirical relationship between the stress-induced increase of 1/f noise and threshold voltage shift. [ABSTRACT FROM AUTHOR]

The contact-end-resistance (CER) method is applied to transfer length method structures to characterize in-depth the graphene--metal contact and its dependence on the back-gate bias. Parameters describing the graphene--metal stack resistance are extracted through the widely used transmission line model. The results show inconsistencies which highlight application limits of the model underlying the extraction method. These limits are attributed to the additional resistance associated with the p-p+ junction located at the contact edge, that is not part of the conventional transmission line model. Useful guidelines for a correct application of the extraction technique are provided, identifying the bias range in which this additional resistance is negligible. Finally, the CER method and the transmission line model are exploited to characterize the graphene--metal contacts featuring different metals. [ABSTRACT FROM AUTHOR]

In this paper, the analog/mixed-signal performance is evaluated at device and circuit levels for a III-V nanowire tunnel field effect transistor (TFET) technology platform and compared against the predictive model for FinFETs at the 10-nm technology node. The advantages and limits of TFETs over their FinFET counterparts are discussed in detail, considering the main analog figures of merits, as well as the implementation of low-voltage track-and-hold (T/H) and comparator circuits. It is found that the higher output resistance offered by TFET-based designs allows achieving significantly higher intrinsic voltage gain and higher maximum-oscillation frequency at low current levels. TFET-based T/H circuits have better accuracy and better hold performance by using the dummy switch solution for the mitigation of the charge injection. Among the comparator circuits, the TFET-based conventional dynamic architecture exhibits the best performance while keeping lower area occupation with respect to the more complex double-tail circuits. Moreover, it outperforms all the FinFET counterparts over a wide range of supply voltage when considering low values of the common-mode voltage. [ABSTRACT FROM PUBLISHER]

Graphene-based capacitors and Graphene base transistors (GBTs) featuring innovative engineered tunnel barriers are characterized in DC and the data are thoroughly analyzed by means of an electrical model and a Monte Carlo transport simulator. Following model calibration on experiments, we then propose strategies to improve the DC common-base current gain and the cutoff frequency of GBTs. The DC and RF performance of optimized GBT structures based on realistic technology data are analyzed in detail to highlight advantages and potential limits of this device concept. [ABSTRACT FROM PUBLISHER]

We carefully scrutinize the potential of ultrathin body strained (111) GaAs MOSFETs to achieve better performance than other GaAs-based channel FETs at scaled channel length and with relaxed thickness requirements, thanks to L-valleys enhanced density-of-states (DoS) and carrier transport. Calibrated multi-subband Monte Carlo simulations including scattering provide the modeling framework necessary for accurate simulations. The results show that L-valley-enhanced transport most likely will not yield the I\rm{\scriptscriptstyle ON} and switching time improvements observed in simple ballistic simulations, even if considering the ideal material properties and purely phonon scattering limited transport. In fact, the increased DoS and inversion charge at the virtual source provided by the L-valleys in the strained material is counterbalanced by an increased phonon scattering rate and reduced carrier velocity. [ABSTRACT FROM PUBLISHER]

Conspectus: We have developed a measurement platform for performing high-frequency AC detection at nanoelectrodes. The system consists of 65 536 electrodes (diameter 180 nm) arranged in a sub-micrometer rectangular array. The electrodes are actuated at frequencies up to 50 MHz, and the resulting AC current response at each separately addressable electrode is measured in real time. These capabilities are made possible by fabricating the electrodes on a complementary metal-oxide-semiconductor (CMOS) chip together with the associated control and readout electronics, thus minimizing parasitic capacitance and maximizing the signal-to-noise ratio. This combination of features offers several advantages for a broad range of experiments. First, in contrast to alternative CMOS-based electrical systems based on field-effect detection, high-frequency operation is sensitive beyond the electrical double layer and can probe entities at a range of micrometers in electrolytes with high ionic strength such as water at physiological salt concentrations. Far from being limited to single- or few-channel recordings like conventional electrochemical impedance spectroscopy, the massively parallel design of the array permits electrically imaging micrometer-scale entities with each electrode serving as a separate pixel. This allows observation of complex kinetics in heterogeneous environments, for example, the motion of living cells on the surface of the array. This imaging aspect is further strengthened by the ability to distinguish between analyte species based on the sign and magnitude of their AC response. Finally, we show here that sensitivity down to the attofarad level combined with the small electrode size permits detection of individual 28 nm diameter particles as they land on the sensor surface. Interestingly, using finite-element methods, it is also possible to calculate accurately the full three-dimensional electric field and current distributions during operation at the level of the Poisson-Nernst-Planck formalism. This makes it possible to validate the interpretation of measurements and to optimize the design of future experiments. Indeed, the complex frequency and spatial dependence of the data suggests that experiments to date have only scratched the surface of the method's capabilities. Future iterations of the hardware will take advantage of the higher frequencies, higher electrode packing densities and smaller electrode sizes made available by continuing advances in CMOS manufacturing. Combined with targeted immobilization of targets at the electrodes, we anticipate that it will soon be possible to realize complex biosensors based on spatial- and time-resolved nanoscale impedance detection. [ABSTRACT FROM AUTHOR]

In this work, a complementary InAs/Al0.05Ga0.95Sb tunnel field-effect-transistor (TFET) virtual technology platform is benchmarked against the projection to the CMOS FinFET 10-nm node, by means of device and basic circuit simulations. The comparison is performed in the ultralow voltage regime (below 500 mV), where the proposed III–V TFETs feature ON-current levels comparable to scaled FinFETs, for the same low-operating-power OFF-current. Due to the asymmetrical n- and p-type $I$ – V\text{s} , trends of noise margins and performances are investigated for different Wp/Wn ratios. Implications of the device threshold voltage variability, which turned out to be dramatic for steep slope TFETs, are also addressed. [ABSTRACT FROM PUBLISHER]

This paper reports about the implementation in a multisubband Monte Carlo device simulator of a comprehensive surface roughness scattering model, based on a nonlinear relation between the scattering matrix elements and the fluctuations \Delta (\text r) of the interface position. The model is first extended by including carrier screening effects and accounting for scattering at multiple interfaces, and it is then used for the analysis of relevant experimental data sets. We show that the new model can reproduce fairly well the silicon universal mobility curves as well as mobility data for ultrathin-body InGaAs MOSFETs using \Delta \mathrm{ rms} values consistent with atomic force microscopy (AFM) and TEM measurements. Our simulation results and some experimental data also indicate that mobility in InGaAs MOSFETs is reduced with decreasing well thickness, TW , with a weaker dependence compared with the TW^{6} behavior observed in Si devices. [ABSTRACT FROM AUTHOR]

The interplay between electrical stress and ionizing radiation effects is experimentally investigated in Si-based Tunnel Field Effect Transistors (TFETs). In particular, the impact of bias conditions on the performance degradation is discussed. We found that the electrical stress effects in TFETs could not be ignored in radiation tests, since they can possibly overwhelm the radiation-induced degradation. Under this circumstance, the worst-case bias condition for studying radiation effects is not straightforward to be determined when there is an interplay between electrical stress and ionizing radiation effects. [ABSTRACT FROM AUTHOR]

We present and thoroughly compare band-structures computed with density functional theory, tight-binding, k · p and non-parabolic effective mass models. Parameter sets for the non-parabolic Γ , the L and X valleys and intervalley bandgaps are extracted for bulk InAs, GaAs and InGaAs. We then consider quantum-wells with thickness ranging from 3 nm to 10 nm and the bandgap dependence on film thickness is compared with experiments for In 0.53 Ga 0.47 As quantum-wells. The impact of the band-structure on the drain current of nanoscale MOSFETs is simulated with ballistic transport models, the results provide a rigorous assessment of III–V semiconductor band structure calculation methods and calibrated band parameters for device simulations. [ABSTRACT FROM AUTHOR]

We present experimental data on analog device performance of p-type planar- and gate all around (GAA) nanowire (NW) Tunnel-FETs (TFETs) as well as on n-type Tri-Gate-TFETs. A significant improvement of the analog performance by enhancing the electrostatics from planar TFETs to GAA-NW-TFETs with diameters of 20 nm and 10 nm is demonstrated. A maximum transconductance of 122 μS/μm and on-currents up to 23 μA/μm at a gate overdrive of V gt = V d = −1 V were achieved for the GAA NW-pTFETs. Furthermore, a good output current-saturation is observed leading to high intrinsic gain up to 217. The Tri-Gate nTFETs beat the fundamental MOSFET limit for the subthreshold slope of 60 mV/dec and by that also reach extremely high transconductance efficiencies up to 82 V −1 . [ABSTRACT FROM AUTHOR]

In this paper, we investigate electron transport and electron scattering in the insulators of the Graphene Base Transistor (GBT) by means of a Monte Carlo transport model. We focus on electron backscattering in the base-collector insulator as the possible root cause of the large experimental base current and small measured common-base current gain ( α F ) of GBTs. Different GBT structures have been simulated and the impact of the scattering parameters on the base current is analyzed. Simulated backscattering-limited α F values are found to be much higher than available experimental data, suggesting that state-of-the-art technology is still far from being optimized. However, those simulated α F values can be low enough to limit the maximum achievable GBT performance. [ABSTRACT FROM AUTHOR]

We propose a new approach to describe in commercial TCAD the chemical reactions that occur at dielectric/electrolyte interface and make the ion sensitive FET (ISFET) sensitive to pH. The accuracy of the proposed method is successfully verified against the available experimental data. We demonstrate the usefulness of the method by performing, for the first time in a commercial TCAD environment, a full 2-D analysis of ISFET operation, and a comparison between threshold voltage and drain current differential sensitivities in the linear and saturation regimes. The method paves the way to accurate and efficient ISFET modeling with standard TCAD tools. [ABSTRACT FROM PUBLISHER]

This paper presents the design and implementation of dual-band LC-VCOs in the GHz-range featuring a switched coil LC-tank. The proposed design exploits the self-inductance technique. The design of the coil starts from simple considerations and back-of-the-envelope calculations, then electromagnetic simulations are used to optimize the coil layout. The sizing of the switch and its impact on the VCO performance are addressed as well. The VCOs have been implemented in 65 nm CMOS technology. Good correlation between simulated and measured tuning range and phase noise is obtained for all designs, thus confirming the validity and robustness of the design methodology and coil models. Copyright © 2013 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Accurate Schrödinger-Poisson and Multi-Subband Monte Carlo simulations are used to investigate the effect of interface states at the channel-insulator interface of In 0.53 Ga 0.47 As MOSFETs. Acceptor states with energy inside the conduction band of the semiconductor can explain the dramatic Fermi level pinning observed in the experiments. Our results show that these states significantly impact the electrical mobility measurements but they appear to have a limited influence on the static current drive of short channel devices. [ABSTRACT FROM AUTHOR]

Total ionizing dose (TID) effects in Si-based tunnel finite element transfers (FETs) were investigated for the first time. Under 10-keV X-ray irradiation environment, along with the increase in total dose, a shift of the transfer characteristics and an increase in the interface trap density could be observed. After irradiation at 1 Mrad( SiO2) (and higher dose), the threshold voltage and the band-to-band tunneling conduction were only modestly affected, despite the thick buried oxide (140 nm). In contrast, under the same bias and irradiation environment, a FDSOI nMOSFET fabricated with a similar process presented a more severe degradation, suggesting the robustness of TFETs against TID effects. The underlying mechanism was explored through device simulation and ascribed to be due to the peculiarity of the doping structures of TFETs. [ABSTRACT FROM PUBLISHER]

We examined the DC and RF performance of the graphene base transistor (GBT) in the ideal limit of unity common base current gain. To this purpose, we developed a model to calculate the current-voltage characteristics of GBTs with semiconductor or metal emitter taking into account space charge effects in the emitter-base and base-collector dielectrics that distort the potential profile and limit the upper value of \(f_T\) . Model predictions are compared with available experiments. We show that, in spite of space charge high current effects, optimized GBT designs still hold the promise to achieve intrinsic cutoff frequency in the terahertz region, provided that an appropriate set of dielectric and emitter materials is chosen. [ABSTRACT FROM AUTHOR]

Thanks to the high electron velocities, III–V semiconductors have the potential to meet the challenging ITRS requirements for high performance for sub-22-nm technology nodes and at a supply voltage approaching 0.5 V. This paper presents a comparative simulation study of ultrathin-body InAs, In0.53Ga0.47As , and strained Si MOSFETs, by using a comprehensive semiclassical multisubband Monte Carlo (MSMC) transport model. Our results show that: 1) due to the finite screening length in the source-drain regions, III–V and Si nanoscale MOSFETs with a given gate length (L{G}) may have a quite different effective channel length (Leff) ; 2) the difference in Leff provides a useful insight to interpret the performance comparison of III–V and Si MOSFETs; and 3) the engineering of the source-drain regions has a remarkable influence on the overall performance of nanoscale III–V MOSFETs. [ABSTRACT FROM AUTHOR]

We assess the analog/RF intrinsic performance of graphene FETs (GFETs) through a semiclassical transport model, including local and remote phonon scattering as well as band-to-band tunneling generation and recombination, validated by comparison with full quantum results over a wide range of bias voltages. We found that scaling is expected to improve the fT , and that scattering plays a role in reducing both the fT and the transconductance also in sub-100-nm GFETs. Moreover, we observed a strong degradation of the device performance due to the series resistances and source/drain to channel underlaps. [ABSTRACT FROM PUBLISHER]

We present and validate against experiments a modeling approach for high-speed serial links that combines the computational advantages of statistical techniques for intersymbol interference (ISI) (improved by employing the realistic pulse shape as from SPICE simulations) and a simple empirical methodology to account for the jitter of the transmitter. The proposed approach is validated by comparison with other modeling approaches such as full SPICE simulations (for ISI) and Simulink (for jitter) as well as against the experimental data for a 2.5 Gb/s CMOS differential transmitter driving different channels. [ABSTRACT FROM PUBLISHER]