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This work was conducted in the framework of ELICSIR project funded by the European Union H2020 Programme, under the grant agreement No. 857558., Instruments for measuring the absorbed dose and dose rate under radiation exposure, known as radiation dosimeters, are indispensable in space missions. They are composed of radiation sensors that generate current or voltage response when exposed to ionizing radiation, and processing electronics for computing the absorbed dose and dose rate. Among a wide range of existing radiation sensors, the Radiation Sensitive Field Effect Transistors (RADFETs) have unique advantages for absorbed dose measurement, and a proven record of successful exploitation in space missions. It has been shown that the RADFETs may be also used for the dose rate monitoring. In that regard, we propose a unique design concept that supports the simultaneous operation of a single RADFET as absorbed dose and dose rate monitor. This enables to reduce the cost of implementation, since the need for other types of radiation sensors can be minimized or eliminated. For processing the RADFET’s response we propose a readout system composed of analog signal conditioner (ASC) and a self-adaptive multiprocessing system-on-chip (MPSoC). The soft error rate of MPSoC is monitored in real time with embedded sensors, allowing the autonomous switching between three operating modes (high-performance, de-stress and fault-tolerant), according to the application requirements and radiation conditions., European Commission 857558

This work was supported in part by the European Union's Horizon 2020 research and innovation programme under grant agreement No. 857558, and the Ministry of Education, Science and Technological Development of the Republic of Serbia, under the project No. 43011., The radiation-sensitive field-effect transistors (RADFETs) with an oxide thickness of 400 nm are irradiated with gate voltages of 2, 4 and 6 V, and without gate voltage. A detailed analysis of the mechanisms responsible for the creation of traps during irradiation is performed. The creation of the traps in the oxide, near and at the silicon/silicon-dioxide (Si/SiO2) interface during irradiation is modelled very well. This modelling can also be used for other MOS transistors containing SiO2. The behaviour of radiation traps during postirradiation annealing is analysed, and the corresponding functions for their modelling are obtained. The switching traps (STs) do not have significant influence on threshold voltage shift, and two radiation-induced trap types fit the fixed traps (FTs) very well. The fading does not depend on the positive gate voltage applied during irradiation, but it is twice lower in case there is no gate voltage. A new dosimetric parameter, called the Golden Ratio (GR), is proposed, which represents the ratio between the threshold voltage shift after irradiation and fading after spontaneous annealing. This parameter can be useful for comparing MOS dosimeters., European Commission 857558, Ministry of Education, Science & Technological Development, Serbia 43011

Introduction. The approach to increase the sensitivity of semiconductor radiation dosimeter with a stacked design was presented for the thick oxide pMOS transistors, also known as RadFETs (A. Kelleher et al., IEEE transactions on nuclear science 42, 1995). The sensitivity is increasing with the number of RadFETs in stacked structure, but there were limitations because of the diode reverse breakdown voltage during readout current (B. O’Connell et al., In Proceedings of the Third European Conference on Radiation and its Effects on Components and Systems, 1995). Further improvement of the stacked RadFETs device enables detecting a minimum absorbed dose of less than 50 Gy for a 20 V power supply (B. O’Connell et al., Fifth European Conference on Radiation and Its Effects on Components and Systems, 1999). Floating gate MOSFET is a modified structure of MOSFET with another polysilicon gate surrounded by oxide. The advantages of the floating gate MOSFET as a radiation dosimeter are that it does not require thick oxide fabrication and the highest sensitivity is for the zero-bias at the control gate during irradiation (S. Ilić et al., Sensors 20 (11), 2020). Experimental setup. Commercial floating gate MOSFETs designed by Advanced Linear Devices Inc. were used in this paper. Four transistors were connected in the stacked structure (drain and control gate are shorted and connected to the source of the next stacked transistor), and their threshold voltage drift values were measured before and after each irradiation portion with the same conditions. The experiment was performed at the Institute of Nuclear Sciences “Vinča”, Belgrade, Serbia. Radiation source Co-60 was used for irradiation of the components, with the following portions of the absorbed dose (Si): 10 Gy, 10 Gy, 10 Gy, 20 Gy, 50 Gy, 400 Gy, 500 Gy, 4 mGy, 45 mGy, 50 mGy, respectively (absorbed dose was 100 mGy in total). All measurements were performed in a test fixture with triax cables by Keithley 2636A Source Measure Unit. During irradiation, all stacked transistors were zero-biased. Results. Observing the threshold voltage drift of the four stacked floating gate MOS transistors, we noticed that the stack of two transistors has the most stable reading values over time (smallest drift). Considering this, we analyzed only two stacked floating gate MOS transistors as a passive dosimeter for the low doses. The results show that it is possible to detect the first portion of 10 Gy at which the sensitivity of the two stacked transistors is 23 V/Gy. For the next same portion, the sensitivity is 17 V/Gy, while for the third, the value is 7 V/Gy. However, for the next 20 Gy, there is a tiny shift, and the sensitivity is only 1 V/Gy. Decreased sensitivity with absorbed dose is a feature of the floating gate MOSFET that has been observed before for much higher doses (S. Ilić et al., Sensors 20 (11), 2020). There is a large overlap in the threshold voltage drift values for the next four radiation portions. However, for the last two largest portions, 45 and 50 mGy, there is a significant threshold voltage shift with no overlapping, and thus it is possible to determine the sensitivity of 0.0226 and 0.0214 V/Gy, respectively. Conclusions. Using a floating gate MOSFET as a low-dose passive dosimeter is possible, but recharging the floating gate and reusing this device for higher total ionizing doses should be investigated. X JUBILEE International Conference on Radiation in Various Fields of Research : RAD 2022 (Spring Edition) : book of abstracts; June 13-17, 2022; Herceg Novi, Montenegro

A Metal Oxide Semiconductor (MOS) ionizing radiation detector architecture which senses trapped charge in the dielectric due to incident ionizing radiation is presented. The detector architecture increases output voltage signal as a function of trapped charge in the sensing dielectric in comparison with state of the art MOSFET (RADFET) technology. Numerical simulations were employed to help develop the device concept. It is shown that an improved voltage sensitivity is possible due to a reduction in the sensing capacitance which, unlike RADFET technology, is decoupled from the dielectric capacitance. An initial prototype of the detector has been fabricated in the silicon fabrication facility of Tyndall National Institute and irradiation experiments have been performed which confirm the improved voltage sensitivity versus commercial RADFET detectors. It is envisaged that further sensitivity increases may be possible by integrating dielectrics other than silicon dioxide. X JUBILEE International Conference on Radiation in Various Fields of Research : RAD 2022 (Spring Edition) : book of abstracts; June 13-17, 2022; Herceg Novi, Montenegro

This work was supported in part by the European Union's Horizon 2020 research and innovation programme (Grant No. 857558) and the Ministry of Education, Science and Technology Development of the Republic of Serbia (Project No. 43011)., We investigated the influence of gamma radiation of 50 Gy(H2O) on radiation-sensitive p-channel metal-oxide-semiconductor field-effect transistors with an Al gate (RADFETs) with gate oxide thicknesses of 400 and 1000 nm and gate voltages of 0 and 5 V. The obtained results showed that the sensitivity S at a given gate voltage increases with the square of the gate oxide thickness. After irradiation (IR), spontaneous annealing (SA) was performed at room temperature without voltage at the gate. We present the behaviors of fixed traps and switching traps, determined by the midgap technique, and that of fast switching traps, determined by the charge-pumping technique, during IR and SA. A very important characteristic of dosimetric transistors is fading, which represents the recovery of the threshold voltage of the irradiated RADFETs during SA. The maximum fading is about 15% after 9100 h, except for the RADFETs with a gate oxide thickness of 1000 nm and a gate voltage of 5 V, for which it is about 30%. A fitting equation for fading was proposed, which fitted the experimental fading values very well., European Union's Horizon 2020 research and innovation programme 857558, Ministry of Education, Science & Technological Development, Serbia 43011

This work was supported in part by the European Union's Horizon 2020 research and innovation programme under grant agreement No. 857558, and the Ministry of Education, Science and Technological Development of the Republic of Serbia, under the project No. 43011., The RADiation sensitive metal-oxide-semiconductor field-effect-transistors (RADFETs) were irradiated with gamma rays up to absorbed dose of 110 Gy(H2O). The results of threshold voltage, V-T , during irradiation with various positive gate biases showed the increase in V-T with gate bias. The threshold voltage shift, Delta V-T , during irradiation was fitted very well. The contributions of both the fixed traps (FTs) and switching traps (STs) during radiation on Delta V-T were analyzed. The results show the significantly higher contribution of FTs than STs. A function that describes the dependence of threshold voltage shift and its components on gate bias was proposed, which fitted the experimental values very well. The annealing at the room temperature without gate bias of irradiated RADFETs was investigated. The recovery of threshold voltage, known as fading, slightly increase with the gate bias applied during radiation. The Delta V-T shows the same changes as the threshold voltage component due to fixed states, Delta V-ft , while there is no change in the threshold voltage component due to switching traps, Delta V-st ., European Union's Horizon 2020 research and innovation programme 857558, Ministry of Education, Science & Technological Development, Serbia 43011

Pre-irradiation device characteristics, gamma radiation response, and possible use in radiation dosimetry have been investigated for MOSFETs with a 100 nm thick Er2O3 gate dielectric. The performance of these novel devices has been compared with that of commercial pMOS dosimeters (RadFETs) with a standard SiO2 gate oxide of the same thickness. The radiation sensitivity of the Er2O3 is significantly higher than that of SiO2, and this is particularly pronounced at lower dose levels. Significantly larger numbers of positive charges are trapped in the Er2O3 dielectric than in SiO2 during irradiation exposure, resulting in increased threshold voltage shift. After two weeks of room temperature annealing, 11.9% and 24.0% fading have been observed in SiO2 and Er2O3 samples, respectively. Higher fading for Er2O3 may be related to higher number of shallow traps close to the dielectric/silicon interface. These initial results are promising for the possible use of Er2O3 as a new gate dielectric in pMOS dosimeters. The observed enhancement of device sensitivity can be a milestone for the introduction of the pMOS dosimeters in personal dosimetry applications.

Silicon carbide is a wide band gap semiconductor which presents excellent physical properties such as a high critical electric field strength which enables the realisation of efficient power devices [1]. The cubic silicon carbide (3C-SiC) polytype has been less investigated than the more popular hexagonal structure 4H-SiC. 3C-SiC has the advantage that it can be epitaxially grown on Si by chemical vapour deposition (CVD) [2] and presents properties suitable for achieving cost effective SiC power devices in the range 650V to 1200V. These 3C-SiC/Si substrates offer a promising alternative to the costly hexagonal SiC (4H-SiC) wafers and can also be used as template for the epitaxy of cubic GaN [3]. However, the presence of the Si substrate does limit the temperature available to anneal out the implantation damage generated by some device processing sequences. This work investigates the properties of metal silicides as a potential Schottky contacts for high blocking voltage 3C-SiC/Si Schottky barrier diodes (SBDs). For this study, Ti and Pt silicide contacts are formed on the (100)3C-SiC surface. The influence of the silicide formation temperature (500oC-650oC) on the contact electrical properties is investigated in detail. Current voltage (I-V) and capacitance voltage characteristics (C-V) are used to evaluate the reverse leakage current and extract the Schottky barrier height as well as the concentration of electrically active dopants in the N type 3C-SiC/Si. The Pt silicide Schottky contact is found to present higher energy barrier height than the Ti silicide Schottky contact and this trend was confirmed by the associated improved reverse current in the Pt Schottky. This is a promising result as it suggests that the reverse leakage is not dominated by the stacking faults inherent to this material. Temperature dependent I-V characteristics are measured and compared to theoretical I-V curves to explore the mechanisms responsible of the reverse leakage. The effort towards high blocking voltage final SBD device requires excellent PN junction edge termination. In this work, to avoid the damage caused by Al ion implantation, the electrical properties of 3C-SiC/Si PN junction diodes fabricated by epitaxy of P type 3C-SiC layers on N type 3C-SiC/Si substrates are also investigated. The reverse current mechanisms in the PN junction and the Schottky are compared and the suitability of the PN for device termination is discussed. [1] Kimoto, T., Cooper, J.A. Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices and Applications, Wiley, (2014) [2] A. Severino, C. Locke, R. Anzalone, et al., ECS Transactions, 35 (6), 99 (2011) [3] Okumura, H., Ohta, K., Feuillet, G., et al. Journal of Crystal Growth, 178 (1-2), 113, (1997)

The thermal stability of two commercially available silicon carbide Schottky diode types has been evaluated following a 1000 h non-biased storage test under vacuum at 350 °C. The Ti-based Schottky (Anode) contact shows excellent stability over the duration of the test with less than 5% change in either extracted Schottky barrier height or ideality values. The Al die attach metalisation on the anode also shows no evidence of degradation after the test. However, a considerable change in series resistance was observed for both diode types, with up to a factor of 100 measured for one of the diodes. The primary early failure mode is related to degradation of the NiAg Ohmic (cathode) die attach metalisation. Demixing of the NiAg alloy, leading to Ag agglomeration is proposed to be the underlying degradation mechanism involved resulting in delamination of the die attach metalisation and the corresponding series resistance increase.

We investigate planar fully depleted silicon-on-insulator(SOI) MOSFETs with a thin buried oxide (BOX) and a ground plane (GP). To study the depletion effects in the lightly doped drain (LDD) and substrate, we compare different BOX/GP/ LDD structure combinations. A novel GP back-gate engineering approach is introduced to improve both short-channel effects (SCEs) and LDD resistance. In this technique, an LDD/channel/ LDD mirror doping structure is reproduced in the back gate underneath the thin BOX. It is shown that SCEs are rather insensitive to SOI layer thickness variations and remain well controlled for gate lengths down to 15 nm for both nMOS and pMOS transistors due to outstanding electrostatic control: 63 mV/dec subthreshold swing and 7 mV/V drain-induced barrier lowering at Vdd = 1 V. The shift of the threshold voltage ΔVth with silicon film thickness Tsi down to 0.5 mV/nm is obtained. Simulations show that a 20% reduction in LDD resistance can be achieved in thin BOX devices with an optimized GP, as compared with thick BOX transistors. In addition, an improvement in drive current is also reported.

Bistable-gated-bipolar (BGB) device is an impact-ionization based negative differential resistance (NDR) device featuring full process compatibility with CMOS. This paper presents measurement and analysis of the BGB-based static latches fabricated in a standard 0.35 partially depleted silicon-on-insulator (PD SOI) CMOS technology. The experimental results demonstrate the static storage functionality and the minimum standby current of 0.1-1 nA per BGB device for the drain-to-source voltage ranging from 2.0 to 1.6 V. Compared with the conventional CMOS static latch in the same technology, the delay time is shortened by 100 ps, verified by measurement, SPICE simulation and analysis. As the major penalty for speed enhancement, increase in standby current prevents the BGB devices and the associated MOS switches from aggressively scaling and the BGB-based latches are suitable for large-geometry CMOS logic and ultralow-voltage dynamic threshold voltage MOSFET (DTMOS) logic with high switching activity.

We have developed an integrated microfluidic platform for producing 2-[(18)F]-fluoro-2-deoxy-D-glucose ((18)F-FDG) in continuous flow from a single bolus of radioactive isotope solution, with constant product yields achieved throughout the operation that were comparable to those reported for commercially available vessel-based synthesisers (40-80%). The system would allow researchers to obtain radiopharmaceuticals in a dose-on-demand setting within a few minutes. The flexible architecture of the platform, based on a modular design, can potentially be applied to the synthesis of other radiotracers that require a two-step synthetic approach, and may be adaptable to more complex synthetic routes by implementing additional modules. It can therefore be employed for standard synthesis protocols as well as for research and development of new radiopharmaceuticals.

Dielectric charging at low electric fields is characterized on radio-frequency microelectromechanical systems (RF MEMS) capacitive switches. The dielectric under investigation is silicon dioxide deposited by plasma enhanced chemical vapor deposition. The switch membrane is fabricated using a metal alloy which is shown to be mechanically robust. In the absence of mechanical degradation, these capacitive switches are appropriate test structures for the study of dielectric charging in MEMS devices. Monitoring the shift and recovery of device capacitance-voltage characteristics revealed the presence of a charging mechanism which takes place across the bottom metal-dielectric interface. Current measurements on metal-insulator-metal devices confirmed the presence of interfacial charging and discharging transient currents. The field-and temperature-dependence of these currents is the same as the well-known transient stress-induced leakage current (SILC) observed in flash memory devices. A simple model was created based on established transient SILC theory which accurately fits the measured data and reveals that charge exchange at the bottom metal-dielectric interface is responsible for charging currents and pull-in voltage changes in these MEMS devices. (C) 2015 AIP Publishing LLC.

Bistable gated bipolar (BGB) devices, a novel negative differential resistance (NDR) device, is investigated in this paper. Experimental demonstration for both n-channel and p-channel devices is carried out in a partially depleted silicon-on-insulator technology. The temperature dependence of its NDR characteristics is measured and found to be in good agreement with analytical models. A feasible scheme is proposed to implement this device in scaled CMOS technologies. As the basic principle for applications, the measured hysteresis characteristic of a storage cell utilizing the BGB device is reported for the first time. Potential applications for logic and memory are also discussed

This paper describes the characterization, modelling and evaluation of multielectrode micromechanical structures. Firstly, results of interferometric inspection and electrostatic measurements of fixed–fixed beams with various anchor designs are presented. These data, combined with finite element (FE) analysis of anchor compliance, are used to extract the elastic modulus and residual stress for a thin film aluminium structural layer. Secondly, a multielectrode tunable capacitor (MTC) is presented. The device consists of a suspended top plate and split bottom electrode. The 'leveraged bending' method is examined for extending the tuning range (TR) of such a capacitor. FE simulation of the MTC up to pull-in instability for each drive electrode configuration indicates a TR varying from 1000% to 40% in the range of stress from 0 to 45 MPa. An analytical model for the pull-in voltage of the MTC taking into account partial and/or multielectrode configuration, non-ideal anchors, field fringing and plane strain is presented. The analytical and FE simulations are validated with measured data.

As microelectromechanical systems (MEMS) move rapidly towards commercialization, the issue of mechanical characterization has emerged as a major consideration in device design and fabrication. It is now common to include a set of test structures on a MEMS wafer for extraction of thin film material properties (in particular, residual stress, stress gradient and Young's modulus), and for process and device monitoring. These structures usually consist of micromachined beams and strain gauges. Measurement techniques include tensile testing, scanning electron microscopy (SEM) imaging, atomic force microscopy (AFM) analysis, surface profiling and Raman spectroscopy. However, these tests are often destructive and may be difficult to carry out at the wafer scale. Instead of these methods, this paper uses white-light interferometry surface profiling for material characterization and device inspection. Interferometry is quick, non-destructive, non-contact, and can offer a high density lateral resolution with extremely high sensitivities to the surface in the z-direction—all essential requirements for high volume manufacturing. A range of devices is employed to illustrate the capabilities of white-light interferometry as a measurement and process characterization tool.It is shown that residual stress may be determined by using electrostatic actuation to pull fixed–fixed beams towards the substrate, and interferometry to record the beam deflection profile. Finite-element simulation software is employed to model this deflection, and to estimate the material properties which minimize the difference between the measured and simulated profiles. The results agree well with blanket film measurements.

A novel nonvolatile memory top-floating-gate (TFG) device is demonstrated in a CMOS technology. This device differs in both structure and operation to typical split-gate or stacked-gate approaches. The TFG device offers low development cost, low power compliance, and high reliability. It can be fabricated using routine CMOS processing making it clearly competitive to options typically used in the industry. The structure and operation of this novel device structure is described. This is followed by a description of the processing steps required and measured electrical results.

This paper describes work carried out to assess the elastic performance of microelectromechanical (MEMS) test structures in a post-CMOS (complementary metal oxide semiconductor) metal oxide process. Electrostatic pull-in measurements are used to extract the residual stress, elastic modulus and stress-gradient for the process. Results are presented for metal structures and for composite metal/oxide structures. The extracted parameters are compared with values obtained from blanket film measurements and from analysis based on bulk material properties. Test structures have also been tested for cycling repeatability. A drift is observed in successive cycles of electrostatic actuation and this drift is attributed to charge trapping in the nitride passivation of the underlying CMOS process. A charge-balance model is used to estimate the trapped charge and the effect of actuation voltage polarity is also discussed. The results indicate that satisfactory elastic performance of mechanical structures is dependent on process conditions but can be achieved. The stability of electrical operating characteristics is dominated by nitride charge trapping effects. This effect can be quantified using a basic model. To minimize problems due to charge trapping dielectric properties must be investigated and operating characteristics modified.

Using a commercial finite-element simulation tool, this work considers some of the electromechanical effects commonly neglected during the analysis of electrostatically actuated fixed–fixed beams. These structures are used in many applications of micromechanical systems, from relay switches and RF resonators to thin film characterization tests, but much of the analytical modelling of the device behaviour disregards the effects of electrostatic field fringing, plane-strain conditions and anchor compliance. It is shown that the cumulative total of these errors can be substantial, and may lead to large discrepancies in the expected operational characteristics of the device. We quantify the influence of these effects on the electrostatic pull-in of fixed–fixed beams, and illustrate some of the limitations of ideal pull-in theory. In order to more accurately predict the pull-in voltage for a real structure, a model is developed that combines ideal case theory with anchor compliance correction factors extracted using finite-element analysis. Three common anchor types (ideal, step-up and cup-style) are characterized. The final model takes account of the compliance of the beam anchors, electrostatic field fringing and plane-strain effects, and agrees well with simulated results.

An accurate SPICE compatible model for a novel flash memory device, the Top Floating Gate (TFG) cell, is described. This device can be integrated into CMOS processes with minimal disruption to the standard process. The cell is programmed and erased by Fowler Nordheim tunnelling, which is a low power operation thereby complying with a major requirement of system-on-chip applications. The development of an accurate model for flash memory is complicated by the variable nature of the cell. In standard flash memory, the threshold voltage and, therefore, the drain current of the cell vary as the cell is programmed or erased. In the TFG case, both the threshold voltage and series resistance vary which further complicates the model development. Our model has been found to be accurate over the full range of floating gate charge.

In this paper, the on-wafer measurement of junction depletion capacitance is examined. This work provides an in-depth discussion of possible probing configurations which can be used. It outlines a method to consistently measure the junction capacitances accurately. The results from this method compare favorably with those extracted using S-parameter measurements. Additionally, methods are formulated to reduce the number of data points required for parameter extraction while at the same time maintaining a high model accuracy.

A bipolar hold-down voltage was used to study mechanical degradation in radio-frequency microelectromechanical capacitive shunt switches. The bipolar signal was used to prevent the occurrence of dielectric charging and to isolate mechanical effects. The characteristics of material stress relaxation and recovery were monitored by recording the change of the pull-in voltage of a device. The creep effect in movable components was saturated by repeated actuation to the pulled-in position, while comparison with a theoretical model confirmed the presence of linear viscoelasticity in the devices. (C) 2014 AIP Publishing LLC.

An analysis of extraction methodologies for the coupling ratios in non-volatile memories using numerical simulation is presented. The floating gate voltage of a non-volatile memory (NVM) cell cannot be accessed directly from measurements but can be derived using numerical simulation techniques. In this paper, various coupling ratio methodologies from literature are investigated using numerical simulation techniques and guidelines on improving the application of these methods to NVM cells are outlined. Measurements are performed which validate the increased accuracy of the methods and some of the improved methodologies are recommended for coupling ratio extraction in the Fowler–Nordheim regime. This work demonstrates the role of numerical simulation in supplementing the electrical characterisation of NVM cells.

The advent of the ULSI era, and the continuing decrease of the critical dimensions of MOSFETs, has raised a number of issues concerning the prediction of device reliability, and the consequences for overall product reliability. The established practice has been to assure reliability at the end of the lengthy product cycle. However, to achieve a shorter time-to-market, product reliability concerns should be addressed at the design stage (“design for reliability”). Accordingly, the design and implementation of reliability simulation tools, which give a prediction of the susceptibility of an IC design to device failure mechanisms, is becoming critical. This paper reviews some of the reliability simulation tools that are currently available to industry. The capability of the most popular of these tools is described for a number of different reliability hazards. A topical reliability simulation issue is addressed, and a statistical validation, comparing measured and simulated degraded ring oscillator data, is presented.

This paper provides a review of the use of simulation tools in the design process. It provides examples of applications where such tools can be effective in improving device functionality, yield, manufacturability and reliability. Topics covered are numerical process and device simulation, electromigration and stress migration simulation as well as circuit simulation and reliability modelling. Specific example of how such simulators work are provided and examples of currently available software tools are reviewed.

This work demonstrates that for constant oxide reliability stresses in the Fowler-Nordheim regime a low initial rate of charge trapping/detrapping results in long times to breakdown. It was found for MOS gate oxides that when the initial trapping has been completed at low fields times to breakdown enhance. Depending on the stress sequence measurement results can vary significantly which is of great relevance for correct oxide lifetime predictions.

A novel measurement methodology that extracts the gate capacitance coefficient of floating-gate memory cells is reported. This measurement methodology, which utilizes simple current-voltage measurements, exhibits several advantages over current methodologies. The measurement methodology has been verified using numerical simulation and measurements from two different technologies. Furthermore, a figure of merit for determining the matching performance of the equivalent transistor to the memory cell is also presented and discussed.

This work describes the influence of low current pulses during high current stress on the trapping properties of thin silicon dioxide layers. The determination of the trapped oxide charge during Fowler-Nordheim stress from low current steps is discussed. It is shown that low bias steps are not a reliable indicator of the amount of trapped charge in the oxide due to trapping of additional charges during this measurement period.

We report a semiconductor device that exhibits a negative differential resistance characteristic. The device has the same structure as metal-oxide-semiconductor (MOS) transistors currently used in integrated circuits. Biasing the structure in the subthreshold regime and sweeping the bulk bias results in the negative differential resistance characteristic. The device exhibits a peak valley current ratio of approximately 52 at room temperature while drawing ten nanoampers of current which is of sufficiently low power for ultra-large scale integration (ULSI) applications.

DC and bipolar voltage stresses are used to isolate mechanical degradation of the movable electrode from charging mechanism in microelectromechanical capacitive switches. Switches with different metals as the movable electrode were investigated. In titanium switches, a shift in the pull-in voltages is observed after dc stressing whereas no shift occurs after the bipolar stressing, which is to be expected from charging theory. On switches with similar dielectric but made of aluminium, the narrowing effect occurs regardless if dc or bipolar stressing is used, which indicates the mechanical degradation as the mechanism responsible. (C) 2012 American Institute of Physics. (http://dx.doi.org/10.1063/1.4726116)

In this paper, we give a thorough investigation of a new capacitance coupling coefficient measurement methodology (a back-bias method) that extracts the gate capacitance coefficient of floating-gate memory cells. This measurement methodology that utilizes simple current-voltage measurements presents several advantages over current methodologies. It includes a figure of merit for determining the matching performance of a reference transistor to a memory cell, which plays a crucial role for the extraction of the correct gate coupling coefficient value. By this means, we investigate, for the first time, the impact of structural differences between a reference transistor and a memory cell on the gate coupling coefficient extraction. The back-bias method is compared with commonly used gate coupling coefficient extraction methods, and it is shown that it has a smaller extraction error for nonmatching reference transistors and memory cell pairs. Furthermore, it is demonstrated how the gate coupling coefficient extraction can be corrected if matching reference and memory cell structures cannot be found.

In this paper, we analyze LDD depletion effects in Fully-Depleted SOI (FDSOI) devices with thin-BOX and ground plane (GP). Back-gate engineering is introduced to reduce the series resistance and threshold voltage shifts. We show that shortchannel effects are rather insensitive to SOI layer thickness variations and remains well controlled for gate lengths down to 15nm.

In this paper, we analyze LDD depletion effects in Fully-Depleted SOI (FDSOI) devices with thin-BOX and ground plane (GP). LDD engineering is introduced to reduce the source and drain resistance and threshold voltage shifts. Short-channel effects are rather insensitive to SOI layer thickness variations and remains well controlled for gate lengths down to 15nm.

The purpose of this comment is to provide additional insight into the reliability of microelectromechanical capacitive switches (MEMSs) investigated by Molinero and Casta er [Appl. Phys. Lett. 92, 043502 (2008)]. We show that the presence or absence of ambient humidity determines whether the shift in the capacitance-voltage (C-V) curve of oxide-based MEMS occurs as a result of voltage stress. In humid air, negative and positive shifts in the C-V curve are observed after negative and positive bias stress. In dry air no such shifts in the C-V curve are seen. These shifts are similar to those reported on oxide-based switches by Molinero and Castaner [Appl. Phys. Lett. 92, 043502 (2008)] where they show shifts occurring in room ambient pressure, but not in vacuum. This indicates that not only air pressure but also air humidity can be responsible for shifts in MEMS. (C) 2009 American Institute of Physics. (doi: 10.1063/1.3255008)

The matching performance of nonvolatile memory cells and their equivalent transistors is investigated using a novel matching-performance factor. Extensive measurements on three technologies show that matching pairs can be found, but there is an inherent mobility mismatch between the equivalent transistor and the memory cell. It is suggested that the cause of this mismatch is due to the necessary layout differences between the cell and the equivalent transistor that can cause different levels of plasma-induced damage in the structures

The analytical performance of an enhanced surface area electrolyte insulator semiconductor (EIS) device was investigated for DNA sensor development. The work endeavored to advance EIS performance by monitoring the effect of DNA probe layers have on the impedimetric signal during target hybridisation detection. Two universally employed covalent chemistries, direct and spacer-mediated attachment of amino modified probe molecules to amino-functionalised surfaces were investigated. Relative areal densities of immobilised probe were measured on planar and enhanced surface area substrates using epi-fluorescence microscopy. The reproducibility of the each immobilisation method was seen to have a direct effect on the reproducibility of the impedimetric signal. The sensitivity and selectivity was seen to be dependent on the type of immobilisation method. Real time, impedimetric detection of target DNA hybridisation concentrations as low as 25 and 1 nM were possible. The impact that probe concentration had on the impedimetric signal for selective and non-selective interactions was also investigated.

A novel combination of ground-based and flight tests was employed to examine the reliability of capacitive radio-frequency microelectromechanical switches for use in space applications. Laboratory tests were initially conducted to examine the thermomechanical effects of packaging and space-like thermal stresses on the pull-in voltage of the devices; during this process it was observed that operational stability is highly dependent on the geometrical design of the switch and this must be taken in to account during the design stage. To further expose the switches to acceleration levels experienced during a space mission, they were launched on board a sounding rocket and then subjected to free-fall from a height of over 1.3 km with a resulting impact of over 3500g. Post launch analysis indicates that the switches are remarkably resilient to high levels of acceleration. Some evidence is also present to indicate that time-dependent strain relaxation in die attach epoxy materials may contribute to minor variations in device shape and performance.

The detection offaint light sources, such as distant planets in astronomy; the fluorescence of biological trace elements in biosensors; and the spectral emissions from spectroscopy experiments; ideally requires instrumentation that can log the arrival of single photons in a temporally and spatially resolved fashion. Until recently, the most widely used sensor for such low light level optical measurements was the photomultiplier tube (PMT) but solid state solutions are now replacing them as the preferred detector. There are still a number of applications which include astronomical low light level imaging and photon counting spectroscopy which use conventional PMT and multichannel plate detectors because, until now, the technology has not been sufficiently flexible to replace them. Three solutions are currently available for low light level observation in the application areas mentioned above. Firstly, there are vacuum tube (PMT or multichannel plate) based systems. An example ofwhich is the PAPA Faint Object Camera [1] which indeed enables very low light level imaging to be performed but is extremely expensive and fragile: Secondly, Charge Coupled Device (CCD) based systems. These are very successful in many imaging applications, but have some limitations when low light level signals are to be addressed, and finally Avalanche Photodiode (APD) detectors. These detectors are not currently used for imaging but provide a robust replacement for the PMT in many applications. This work has involved the development of a novel, Avalanche Photodiode based optical integrated circuit, which enables the imaging of low light level signals and may potentially be a realistic alternative to PMTs in all of the above application areas. This paper describes the development of this novel and completely self contained integrated circuit for low light level imaging applications [2]. The technology developed to implement his integrated circuit has been called SPARCE.CMOS. (Single Photon ARray Control Electronics).