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Intrinsic Mismatch Between Floating-Gate Nonvolatile Memory Cell and Equivalent Transistor
- Source :
- IEEE Electron Device Letters, IEEE Electron Device Letters, Institute of Electrical and Electronics Engineers, 2007, 28 (5), pp.440-442
- Publication Year :
- 2007
- Publisher :
- HAL CCSD, 2007.
-
Abstract
- The matching performance of nonvolatile memory cells and their equivalent transistors is investigated using a novel matching-performance factor. Extensive measurements on three technologies show that matching pairs can be found, but there is an inherent mobility mismatch between the equivalent transistor and the memory cell. It is suggested that the cause of this mismatch is due to the necessary layout differences between the cell and the equivalent transistor that can cause different levels of plasma-induced damage in the structures
- Subjects :
- Materials science
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
02 engineering and technology
Integrated circuit
01 natural sciences
Capacitance
law.invention
Length measurement
Memory cell
law
0103 physical sciences
Hardware_INTEGRATEDCIRCUITS
Electronic engineering
Electrical and Electronic Engineering
[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
ComputingMilieux_MISCELLANEOUS
010302 applied physics
business.industry
Transistor
Testing equipment
equipment and supplies
021001 nanoscience & nanotechnology
Electronic, Optical and Magnetic Materials
Non-volatile memory
Optoelectronics
Mosfet circuits
0210 nano-technology
business
Subjects
Details
- Language :
- English
- ISSN :
- 07413106
- Database :
- OpenAIRE
- Journal :
- IEEE Electron Device Letters, IEEE Electron Device Letters, Institute of Electrical and Electronics Engineers, 2007, 28 (5), pp.440-442
- Accession number :
- edsair.doi.dedup.....f9d33fbd8dddb9a4276b7c03fa16157c