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Intrinsic Mismatch Between Floating-Gate Nonvolatile Memory Cell and Equivalent Transistor

Authors :
M.F. Beug
M. van Duuren
Quentin Rafhay
Russell Duane
Rafhay, Quentin
Tyndall National Institute [Cork]
Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC)
Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)
Source :
IEEE Electron Device Letters, IEEE Electron Device Letters, Institute of Electrical and Electronics Engineers, 2007, 28 (5), pp.440-442
Publication Year :
2007
Publisher :
HAL CCSD, 2007.

Abstract

The matching performance of nonvolatile memory cells and their equivalent transistors is investigated using a novel matching-performance factor. Extensive measurements on three technologies show that matching pairs can be found, but there is an inherent mobility mismatch between the equivalent transistor and the memory cell. It is suggested that the cause of this mismatch is due to the necessary layout differences between the cell and the equivalent transistor that can cause different levels of plasma-induced damage in the structures

Details

Language :
English
ISSN :
07413106
Database :
OpenAIRE
Journal :
IEEE Electron Device Letters, IEEE Electron Device Letters, Institute of Electrical and Electronics Engineers, 2007, 28 (5), pp.440-442
Accession number :
edsair.doi.dedup.....f9d33fbd8dddb9a4276b7c03fa16157c