Search

Germanium (Ge) films were heteroepitaxially grown on flexible, large-area, single-crystal-like metallic substrates. Multiple, heteroepitaxial, buffer layers of nanoscale dimensions were deposited on the triaxially textured, single-crystal-like, thermo-mechanically processed Ni–W alloy substrates. Ge films were deposited on a CeO2-terminated, heteroepitaxial buffer stack on the metallic substrate using electron beam evaporation. X-ray diffraction θ–2θ scans showed a very strong Ge (400) peak and the full width at half-maximum (FWHM) of the Ge (400) rocking curve was 0.93°. The Ge (111) ϕ-scan showed a FWHM value ∼4°. Based on the X-ray ω-scan, ϕ-scan and (111), (110), and (001) X-ray pole-figures, the Ge film deposited on the flexible, metallic substrate had a cube-on-cube heteroepitaxial relationship with the single-crystal-like metallic substrate. Reflection-high-energy-diffraction (RHEED) patterns from the Ge layer was streaky indicative of a smooth and essentially single-crystal-like Ge film. Cross-section TEM examination revealed a sharp interface between the Ge film and the topmost buffer layer, CeO2, with a low defect density. The CeO2 layer serves as a highly compliant layer that modulates its lattice parameter to attain excellent lattice-matching to the heteroepitaxial Ge layer. Ge films grown on these flexible metal substrates exhibited electron mobilities in the range of 175–250 cm2V–1s–1. Such single-crystal-like semiconductor films on low-cost, flexible, large-area, scalable, single-crystal-like metallic substrates could potentially enable high-performance electronic devices for a range of applications.

Tensile-strained pseudomorphic Ge1–x–ySnxCy was grown on GaAs substrates by molecular beam epitaxy using carbon tetrabromide (CBr4) at low temperatures (171–258 °C). High resolution x-ray diffraction reveals good crystallinity in all samples. Atomic force microscopy showed atomically smooth surfaces with a maximum roughness of 1.9 nm. The presence of the 530.5 cm−1 local vibrational mode of carbon in the Raman spectrum verifies substitutional C incorporation in Ge1–x–ySnxCy samples. X-ray photoelectron spectroscopy confirms carbon bonding with Sn and Ge without evidence of sp2 or sp3 carbon formation. The commonly observed Raman features corresponding to alternative carbon phases were not detected. Furthermore, no Sn droplets were visible in scanning electron microscopy, illustrating the synergy in C and Sn incorporation and the potential of Ge1–x–ySnxCy active regions for silicon-based lasers.

We present, in this paper, a non-conservative approach for building reliable magnetic field sensors based on the resistive and magnetoresistive responses of a varistor diode. These sensors can be built on a ceramic platform of a material which is a solid solution of the ilmenite–hematite consisting of 55 moles% ilmenite, FeTiO3, and 45 mole% of hematite, Fe2O3. This material is abbreviated as IHC 45. These sensors would be suitable for many applications in which a semiconductor Hall effect sensor is currently used. In addition, our ceramic sensors would be suitable for applications in high temperature, energy exploration and well logging, and radiation-dominant environments. The resistive mode sensor is expected to operate reliably and efficiently over the range of 0 $\text{m}\Omega $ /Oe at 0.5 mA which drops to a value of 24.2 $\text{m}\Omega $ /Oe at 2 mA. In the magnetoresistive mode, the sensor has the sensitivity of $142.6~\Omega $ /ln(Oe) and it is 15.6 $\text{m}\Omega $ /Oe at 2 mA. The magnetoresistive mode device also exhibits at room temperature a relatively large magnetoresistive ratio (MR%) of 57% at the modest field of just 4000 Oe making it potentially an attractive candidate for applications in spintronics and magneto-electronics.

Thin films of Ga2O3 and its alloys open the possibility of ultrawide bandgap heterostructure device designs that includes HEMT, quantum well UV optoelectronics, wide bandgap spintronics, high resistive buffer layers for FET and electrocatalytic applications. In this paper, (Ga1-xFex)2O3 (for x = 0.0–0.50) thin film alloys as a function of growth temperatures (450–750 °C) and partial oxygen pressures (10-1 −10-6 torr) grown using pulsed laser deposition are reported. The results suggest that, with the increase of Fe content at a fixed growth temperature and pressure, the bandgap decreases (4.93 to 3.43 eV and 4.39 to 2.25 eV for direct and indirect, respectively) due to a change in the Fe oxidation states as the Fe composition is increased from 0 to 50%. Density functional theory calculations also show a reduction in the bandgap of the alloy as the Fe content increases with the formation of a localized band of states close to the conduction band. Fe content, ≥ 40% in the alloy leads a phase change in the crystal structure with the formation of a gamma phase, also corroborated by theoretical calculations. Finally, room temperature ferromagnetic property was observed in thin films with the introduction of Fe into the Ga2O3 lattice.

A thin passivating SiO x control layer has been deposited via self-limiting CVD on the InGaAs(001)-(2x4) surface by first depositing 2 monolayers of silicon with –Cl x termination using Si 2 Cl 6 ,and then subsequently oxidizing the silicon seed layer by employing anhydrous HOOH(g) at a substrate temperature of 350 °C. After HOOH(g)) dosing, XPS spectra show a higher binding energy shoulder peak on Si2p indicative of SiO x bonding, while an unshifted Si 2p component remains, and In 3d, Ga 2p, and As 2p peaks show no higher binding energy components consistent with the prevention of III-V oxidation. Scanning tunneling spectroscopy (STS) measurements show after SiO x deposition on the InGaAs(001)-(2x4) surface, the bandgap broadens towards that of SiO 2 , with the electronic structure free of states in the bandgap leaving the surface ready for subsequent gate oxide ALD. Density functional theory calculations support the experimental STS data following TMA dosing, which shows TMA nucleates directly on the SiO x /InGaAs(001) surface and leaves an electrically passive interface with the bandgap free of defect states and the surface ready for high-K gate oxide nucleation.

The variation of the chemical composition and properties of PZT films as a function of oxygen pressure and laser fluence during pulsed laser deposition is used to tune the electrical properties of the PZT thin films. It is found that the deposition using a 248 nm laser fluence of 1.7 J/cm 2 and an oxygen pressure of 400 mtorr results the PZT films very similar to that of target material. Changing the laser fluences or oxygen pressure, affects the lead content of the deposited film. In the range of oxygen pressure 50–200 mtorr, the Zr/Zr+Ti and Ti/Zr+Ti ratio varies with oxygen pressure while the Pb/Zr+Ti ratio is almost uniform. Using oxygen pressure as a control parameter to tune the chemical compound and electrical properties of the deposited PZT films, the remnant polarization of the PZT films is tuned in the range of 6.6–42.2 µC/cm 2 , the dielectric constant is controlled in the range of 29–130, and the piezoelectric constant d 33 is controlled in the range of 3.82–4.96 pm/V for a 40 nm thick PZT film.

A large-signal circuit model is used to compute the switching time for double-barrier resonant-tunneling diodes. The model consists of linear circuit elements plus a nonlinear $I$ – $V$ characteristic. The linear elements include a series resistor, a capacitor, and an inductor. The capacitance considers the charge accumulation, depletion in spacer layers, as well as charging-discharging of the quantum-well (QW) region. The inductance accounts for the delay of the current with respect to the voltage across the QW during the abrupt switching transition through the negative differential resistance region. A second-order Runge–Kutta method is used to solve for the switching transient, and then fit to experimental data for a high-quality InGaAs/AlAs resonant tunneling diode (RTD) using the QW inductance as a fitting parameter. Excellent agreement is found for the 10%–90% switching time with a calculated capacitance of 98 fF and a fitted inductance of 1300 pH. This large-signal inductance is approximately $7\times $ greater than the small-signal inductance that has been successfully used to predict the fmax of RTDs such as the one tested here.

Intentional oxidation of an As2-decapped (100) In0.57Ga0.43As substrate by additional H2O dosing during initial Al2O3 gate dielectric atomic layer deposition (ALD) increases the interface trap density (Dit), lowers the band edge photoluminescence (PL) intensity, and generates Ga-oxide detected by X-ray photoelectron spectroscopy (XPS). Aberration-corrected high resolution transmission electron microscopy (TEM) reveals formation of an amorphous interfacial layer which is distinct from the Al2O3 dielectric and which is not present without the additional H2O dosing. Observation of a temperature dependent border trap response, associated with the frequency dispersion of the accumulation capacitance and conductance of metal-oxide-semiconductor (MOS) structures, is found to be correlated with the presence of this defective interfacial layer. MOS capacitors prepared with additional H2O dosing show a notable decrease (∼20%) of accumulation dispersion over 5 kHz to 500 kHz when the measurement temperature decrease...

Channel passivation of SiGe and InGaAs requires removal of dangling bonds and formation of a thermally stable interface. On InGaAs, one solution is the deposition by self-limiting CVD or ALD of a few monolayer of silicon, silicon oxide, or silicon nitride. To form an Si-OH terminated In0.53Ga0.47As(001) surface, two monolayers of Si were deposited at 350°C with self-limiting CVD using Si2Cl6 dosing following by dosing anhydrous HOOH(g). Scanning tunneling microcopy (STM) shows and ordered surface is form while scanning tunneling spectroscopy (STS) shows the surface Fermi level position moves towards midgap due to a surface dipole formation from –OH groups and oxygen bonding to the surface. TMA was dosed at 250°C onto the Si-OH terminated InGaAs(001), and XPS shows the emergence of the Al 2p and C 1s peaks indicative of TMA surface nucleation. The TMA shifts the InGaAs Fermi level back towards the conduction band, consistent with unpinning. MOSCAPs were fabricated to further demonstrate Fermi level unpinning using the Si-OH termination of InGaAs. While this same Si deposition process could be employed on SiGe, a simple annealing process can be employed to form a silicon terminated SiGe surface. A saturation dose of H2O2(g) at 25oC chemisorbs to on Si0.5Ge0.5(110) and Si0.47Ge0.53(001) surfaces leaving the Fermi level on the surface unpinned, and the surface is functionalized with mainly Si-OH, Ge-OH and Si-O-Ge bond. After a subsequent TMA dose at 25oC and annealing at 300oC, XPS and STM verify that a thermally stable and well-ordered monolayer of Al2O3 is formed on SiGe(110) and (001) surfaces with only Al-O-Si bonds and no detectable Ge-O-Si bonds. The H2O2(g) functionalization provides 3 times higher O sites on the surface and 3 times higher TMA nucleation density than H2O(g) at 25°C and 120°C. A variety of strongly bound passivating atoms can induce formation of a nearly pure Si interfacial layer between high-k dielectrics and SiGe. This annealing procedure was employed to form MOSCAP on SiGe(001) using Al2O3 and HfO2 gate oxides after either (NH4)2S or NH3 plasma passivation. For NH3 plasma passivation, angle-resolved XPS showed that the annealing allows formation of nearly Ge-free SiON layer. For higher Ge concentrations, the annealing process is unlikely to form a nearly Ge-free SiON layer so a novel plasma-free chemistry has been develop to deposit SiON using ALD with N2H4(g) as a precursor. Figure 1

We report on the use of SrTiO3 films on GaAs(001) substrates grown by molecular beam epitaxy (MBE) as intermediate buffer layers for the heteroepitaxial growth of ferromagnetic La0.7Sr0.3MnO3 (LSMO) and room temperature multiferroic (ferroelectric/antiferromagnetic) BiFeO3 (BFO) thin films using the pulsed laser deposition technique. The exchange bias coupling effect in the BFO/LSMO heterostructure has been investigated. The magnetization measurements with field cooling exhibit a surprising increment in the magnetic moment with enhanced magnetic hysteresis squareness. This we believe is the consequence of exchange interactions between the antiferromagnetic BFO and the ferromagnetic LSMO at the interface. The integration of BFO materials with LSMO on GaAs substrates facilitated the demonstration of resistive switching based non-volatile memory (NVM) devices which can be faster with lower energy consumption compared to present commercial technologies. Ferroelectric switching observations using piezoresponse force microscopy show polarization switching demonstrating its potential for read–write operation in NVM devices. The ferroelectric and electrical characterization exhibits strong resistive switching with low set/reset voltages. Furthermore, we demonstrate a prototypical epitaxial field effect transistor based on multiferroic BFO as the gate dielectric and ferromagnetic LSMO as the conducting channel. The device exhibits a modulation in channel conductance with a high ON/OFF ratio. This work also demonstrates the first step towards the development of magneto-electronic devices integrated with a compound semiconductor.

Display Omitted Single crystal ferroelectric oxides deposited GaAs.Molecular beam epitaxy of crystalline SrTiO3 and BaTiO3 on GaAs.Crystalline PZT was deposited on STO/Si and STO/GaAs using solution spin coating.DFT calculations were used to determine properties of oxide/semiconductor interfaces. The integration of ferroelectric oxides on semiconductors has been achieved through the use of molecular beam epitaxy and solution spin coating. The oxide layers were determined to be single phase and crystalline and were oriented with the (100) along the growth direction. Epitaxial SrTiO3 and BaTiO3 buffer layers were grown on GaAs and Si using a unique MBE process for nucleation that suppressed the formation of interfacial oxide. The deposition of ferroelectric Pb(Zr)TiO3, on STO buffered Si and GaAs was carried out using solution spin coating. The nucleation of the oxide growth by solution spin coating was promoted by the crystallinity of the surface structure of the SrTiO3 buffer layer. Ab initio Density Functional Theory calculations were used to determine the interfacial structure and band alignments for the STO/GaAs and BTO/GaAs interfaces. Initial electrical characterization of the PZT grown on GaAs was determined by measuring the polarization versus electric field which suggests evidence of ferroelectricity.

In an era of power-constrained transistor scaling, III-V semiconductors, with high electron velocities, appear promising as the n-channel solution in post-Si CMOS technologies [1]. To make this a reality, substantial undertaking has gone into finding solutions for the technological challenges facing III-V MOSFETs [1,2]. InGaAs, in particular, has been the centre of extensive research effort. This has led to the development of surface passivation measures capable of significantly minimizing the defects at the gate dielectric/III-V interface [3,4], ultra-low resistance source/drain contact technology [5], III-V heterointegration capability on Si substrates [6] and demonstration of record performing planar MOSFETs suited for high-performance and low-power logic [7-9]. Currently, InGaAs is being primed for entry into CMOS at the 7nm technology node and beyond. However, given the transition to FinFETs in CMOS technology [10], there is a need to develop dry etch processes capable of nanometer-scale fin definition in III-Vs. Key requirements of the dry etch process are vertical sidewalls and minimum etch damage. The former provides for efficient device electrostatics while the latter is required for a high quality sidewall MOS interface [11]. However, satisfying both criteria is challenging. Highly anisotropic dry etching required for sidewall verticality is more damaging due to the physical nature of the process. Unlike Si, the induced damage cannot be cured by post etch annealing in III-Vs [1]. In this talk we will first report on the dry etch processing systematically investigated for fin formation, with the aim of obtaining high resolution fins with vertical sidewalls and clean etch surfaces. Fins were etched in InGaAs, masked with HSQ of nanometric linewidths, for a variety of dry etch gas chemistries using either a RIE or an ICP process. A fin profile within 3¢ª of vertical was achieved with an ICP etch process based around Cl2/CH4/H2 gas chemistry (Fig. 1a). Highly vertical 10nm fins with 16:1 aspect ratio, perhaps the highest aspect ratio, smallest critical dimension fins to date in InGaAs, have also been demonstrated using this chemistry (Fig. 1b). Impact of the various ICP processes were assessed on Al2O3/InGaAs(100) MOS capacitors subject to blanket etch processing prior to (NH4)2S wet treatment and ALD gate dielectric. Despite the promising fin profile, the Cl2/CH4/H2 based ICP process yielded a severely degraded CV characteristic, featuring a peak Dit that is ~5x higher than the control (unetched) sample (Fig. 2). TEM and AFM were used to further elucidate the impact of the various ICP etch processes on the physical properties of the Al2O3/InGaAs interface. The second part of the talk will focus on the mitigation of etch-induced sidewall damage via dry etch process optimization and sidewall passivation techniques. It will be demonstrated that the modification of Cl2/CH4/H2 gas chemistry to include O2 results in the substantial reduction of etch-induced damage, due to the lowering of the ICP power. A near-vertical sidewall profile similar to that obtained for the etch chemistry without O2 is further retained. Some examples of nanowires realized using this gas chemistry will also be shown. The sidewall damage arising from Cl2/CH4/H2/O2 etch chemistry will be assessed on both (100) and (110) oriented InGaAs. To alleviate the damage two post-etch sidewall passivation schemes were explored. The first was based on a photon-assisted hydrogenation process developed by Amethyst Research Inc., applied post-etch or post ALD high-k, and was investigated on Al2O3/InGaAs(100) MOS capacitors subject to Cl2/CH4/H2 blanket etch. The CV results indicated a larger reduction of etch damage for hydrogenation done post ALD high-k (Fig. 3). In the second approach, a wet “digital” etch surface clean was applied following a Cl2/CH4/H2/O2 blanket etch, resulting in a complete recovery of etch damage as determined from CV characteristics of Al2O3/InGaAs(100) MOS capacitor. The process was also investigated for (110) oriented InGaAs. Details of the passivation schemes and the associated results will be discussed further. References [1] J. del Alamo, Nature, 479, 317 (2011). [2] S. Oktyabrsky et al., IJHSES, 18, 761 (2008). [3] P.K. Hurley et al., IEEE T-DMR, 13, 429 (2013). [4] V. Chobpattana et al., JAP, 116, 124104 (2014). [5] R. Oxland et al., IEEE EDL, 33, 501 (2012). [6] R.J.W. Hill et al., IEEE IEDM, 2010. [7] S. Lee et al., VLSI Symp., 2014. [8] C.Y. Huang et al., IEEE IEDM, 2014. [9] S.W. Chang et al., IEEE IEDM, 2013. [10] C.C. Wu et al., IEEE IEDM, 2010. [11] X. Zhao et al., IEEE EDL, 35, 521 (2014). Figure 1

The impact of scaling on off-state current of p-i-n diodes is studied. A sub-micron p-i-n diode exhibits a dominating surface component of leakage current. Variation in i-layer thickness has an impact on bulk leakage. Bulk leakage scales with cross-sectional area of the diode and surface leakage has been controlled using surface treatments to give ultra low leakage currents of 210 fA for a device of cross sectional area of 0.44 μ m2. Devices of 100 nm i-layer thickness show an average bulk and surface current densities of 100 mA/cm2 and 150 fA/ μ m, respectively.

The integration of III–V compound semiconductors with Si can combine the cost advantage and maturity of Si technology with the superior performance of III–V materials. We have achieved the heteroepitaxial growth of III–V compound semiconductors on a crystalline SrTiO 3 buffer layer grown on Si(0 0 1) substrates. A two-step growth process utilizing a high temperature nucleation layer of GaAs, followed by a low-temperature GaAs layer at a higher growth rate was employed to achieve highly crystalline thick GaAs layers on the SrTiO 3 /Si substrates with low surface roughness as seen by AFM. The effect of the GaAs nucleation layer on different surface terminations for the SrTiO 3 layer was studied for both on axis and miscut wafers, which led to the conclusion that the Sr terminated surface on miscut substrates provides the best GaAs films. Using GaAs/STO/Si as virtual substrates, we have optimized the growth of high quality GaSb using the interfacial misfit (IMF) dislocation array technique. This work can lead to the possibility of realizing infrared detectors and next-generation high mobility III–V CMOS within the existing Si substrate infrastructure.

In0.53Ga0.47As Esaki tunnel diodes grown by molecular beam epitaxy on an Si substrate via a graded buffer and control In0.53Ga0.47As Esaki tunnel diodes grown on an InP substrate are compared in this paper. Statistics are used as a tool to show peak-to-valley ratio for the III–V on Si sample and the control that perform similarly below $8.6 \times 10^{-10}$ cm $^{2}$ . The existence of a critical device area suggests the potential to utilize III–V on Si for other deeply scaled tunnel devices.

Frequency (100 ${\rm Hz}\le f \le 1$ MHz) and temperature ( $- 50 \le T \le 20^{\circ }\text{C}$ ) characteristics of low interface state density $D_{\rm {it}}$ high- $\kappa $ gate-stacks on n-InAs have been investigated. Capacitance–voltage ( $C$ – $V$ ) curves exhibit typical accumulation/depletion/inversion behavior with midgap $D_{\rm {it}}$ of $2\times 10^{11}$ and $4\times 10^{11}$ cm $^{-2}$ eV $^{-1}$ at −50 °C and 20 °C, respectively. Asymmetry of low-frequency s $C$ – $V$ curves and $C$ – $T$ dependence for negative voltage showing a sharp transition of $\cong -20$ dB/decade between low- and high-frequency behavior indicate surface inversion. An inversion carrier activation energy and an InAs hole lifetime of 0.32 eV and 2 ns have been extracted, respectively. Surface channel nMOSFETs with gate length $L_{g} =$ 1 $\mu \text{m}$ , channel thickness = 10 nm, and equivalent oxide thickness (EOT) $1 \le {\rm EOT} \le 1.6$ nm have been fabricated. For ${\rm EOT} = 1$ nm, a subthreshold swing $S = 65$ mV/decade, transconductance $g_{m} =1.6$ mS/ $\mu \text{m}$ , and ON-current $I_{{\mathrm{{\scriptscriptstyle ON}}}} =$ 426 $\mu \text{A}/\mu \text{m}$ at an OFF-current $I_{{\mathrm{{\scriptscriptstyle OFF}}}} =100$ nA/ $\mu \text{m}$ (supply voltage $V_{\rm {dd}} =$ 0.5 V) have been measured. Peak electron field-effect mobilities of 6000–7000 cm $^{2}$ /Vs at sheet electron densities of 2– $3\times 10^{12}$ cm $^{-2}$ were obtained for EOT as small as 1 nm.

A saturated Si-Hx seed layer for gate oxide or contact conductor ALD has been deposited via two separate self-limiting and saturating CVD processes on InGaAs(001)-(2 × 4) at substrate temperatures of 250 and 350 °C. For the first self-limiting process, a single silicon precursor, Si3H8, was dosed at a substrate temperature of 250 °C, and XPS results show the deposited silicon hydride layer saturated at about 4 monolayers of silicon coverage with hydrogen termination. STS results show the surface Fermi level remains unpinned following the deposition of the saturated silicon hydride layer, indicating the InGaAs surface dangling bonds are electrically passivated by Si-Hx. For the second self-limiting process, Si2Cl6 was dosed at a substrate temperature of 350 °C, and XPS results show the deposited silicon chloride layer saturated at about 2.5 monolayers of silicon coverage with chlorine termination. Atomic hydrogen produced by a thermal gas cracker was subsequently dosed at 350 °C to remove the Si-Cl termination by replacing with Si-H termination as confirmed by XPS, and STS results confirm the saturated Si-Hx bilayer leaves the InGaAs(001)-(2 × 4) surface Fermi level unpinned. Density function theory modeling of silicon hydride surface passivation shows an Si-Hx monolayer can remove all the dangling bonds and leave a charge balanced surface on InGaAs.

Studies have shown that metal oxide semiconductor field-effect transistors fabricated utilizing compound semiconductors as the channel are limited in their electrical performance. This is attributed to imperfections at the semiconductor/oxide interface which cause electronic trap states, resulting in inefficient modulation of the Fermi level. The physical origin of these states is still debated mainly because of the difficulty in assigning a particular electronic state to a specific physical defect. To gain insight into the exact source of the electronic trap states, density functional theory was employed to model the intrinsic physical defects on the InGaAs (2 × 4) surface and to model the effective passivation of these defects by utilizing both an oxidant and a reductant to eliminate metallic bonds and dangling-bond-induced strain at the interface. Scanning tunneling microscopy and spectroscopy were employed to experimentally determine the physical and electronic defects and to verify the effectiveness of dual passivation with an oxidant and a reductant. While subsurface chemisorption of oxidants on compound semiconductor substrates can be detrimental, it has been shown theoretically and experimentally that oxidants are critical to removing metallic defects at oxide/compound semiconductor interfaces present in nanoscale channels, oxides, and other nanostructures.

The electronic properties of epitaxial oxide thin films grown on compound semiconductors are largely determined by the interfacial atomic structure, as well as the thermodynamic conditions during synthesis. Ferroelectric polarization and Fermi-level pinning in ${\mathrm{SrTiO}}_{3}$ films have been attributed to the presence of oxygen vacancies at the oxide/semiconductor interface. Here, we present scanning transmission electron microscopy (STEM) and electron energy-loss spectroscopy analyses of GaAs films grown on ${\mathrm{SrTiO}}_{3}$ combined with first-principles calculations to determine the atomic and electronic structures of the ${\mathrm{SrTiO}}_{3}/\mathrm{GaAs}$ interfaces. An atomically abrupt SrO/As interface is observed and the interfacial SrO layer is found to be O-deficient. First-principles density functional theory (DFT) calculations show SrO/Ga and Sr/As interfaces are favorable under O-rich and O-poor conditions, respectively. The SrO/Ga interface is reconstructed via the formation of Ga-Ga dimers while the Sr/As interface is abrupt and consistent with the experiment. DFT calculations further reveal that intrinsic two-dimensional electron gas (2DEG) forms in both SrO/Ga and Sr/As interfaces, and the Fermi level is pinned to the localized 2DEG states. Interfacial O vacancies can enhance the 2DEG density while it is possible for Ga/As vacancies to unpin the Fermi level from the 2DEG states.

We investigate the effects of pre- and postatomic layer deposition (ALD) defect passivation with hydrogen on the trap density and reliability of Al2O3/InGaAs gate stacks. Reliability is characterized by capacitance-voltage hysteresis measurements on samples prepared using different fabrication procedures and having different initial trap densities. Despite its beneficial capability to passivate both interface and border traps, a final forming gas (H2/N2) anneal (FGA) step is correlated with a significant hysteresis. This appears to be caused by hydrogen depassivation of defects in the gate stack under bias stress, supported by the observed bias stress-induced increase of interface trap density, and strong hydrogen isotope effects on the measured hysteresis. On the other hand, intentional air exposure of the InGaAs surface prior to Al2O3 ALD increases the initial interface trap density (Dit) but considerably lowers the hysteresis. Fil: Tang, Kechao. University of Stanford; Estados Unidos Fil: Palumbo, Félix Roberto Mario. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentina. Comisión Nacional de Energía Atómica. Gerencia del Área Investigaciones y Aplicaciones no Nucleares; Argentina. Universidad Tecnológica Nacional; Argentina Fil: Zhang, Liangliang. University of Stanford; Estados Unidos Fil: Droopad, Ravi. University of Texas; Estados Unidos Fil: McIntyre, Paul C.. University of Stanford; Estados Unidos

We investigate the effects of pre- and postatomic layer deposition (ALD) defect passivation with hydrogen on the trap density and reliability of Al

A major obstacle facing III-V semiconductor based metal oxide semiconductor field effect transistors (MOSFETs) is the large density of trap states that exist at the semiconductor/oxide interface.[1] These trap states can pin the Fermi level preventing the MOSFET from acting as a switch in logic devices. Several sources of Fermi level pinning have been proposed including oxidation of the III-V substrate.[2, 3] In order to minimize the presence of III-V oxides it is crucial to employ either an ex-situ etch or to use an in-situ method such as atomic hydrogen cleaning.[4, 5] Although atomic H cleaning of III-V surfaces is well known, it has never been demonstrated on InGaAs (110) crystallographic faces. Furthermore, tri-gate field effect transistors (finFETs) have recently been employed in commercially available logic chips.[6] This unique device architecture allows for a reduction in short channel effects, minimization of the subthreshold swing, and a higher transconductance.[7] The InGaAs (110) surface would be the sidewalls of a vertically aligned (001) based finFETs.[8] Therefore, it is essential to find an in-situ method to efficiently remove any oxides or contamination from the (110) surfaces that is also compatible with the (001) surface. In this study, STM was employed to determine if atomic hydrogen can be used to remove the native oxide from air exposed InGaAs (110) samples. A post clean anneal was used to restore the surface to molecular beam epitaxy (MBE) levels of cleanliness.

Growing good quality III–V epitaxial layers on Si substrate is of utmost importance to produce next generation high-performance devices in a cost effective way. In this paper, using physical analysis and electrical measurements of Esaki diodes, fabricated using molecular beam epitaxy grown ${\rm In}_{0.53}{\rm Ga}_{0.47}{\rm As}$ layers on Si substrate, we show that the valley current density is strongly correlated with the underlying epi defect density. Such a strong correlation indicates that the valley characteristics can be used to monitor the epi quality. A model is proposed to explain the experimental observations and is validated using multiple temperature diode $I{-}V$ data. An excess defect density is introduced within the device using electrical and mechanical stress, both of which are found to have a direct impact on the valley current with a negligible change in the peak current characteristics, qualitatively supporting the model predictions.

Intentional oxidation of an As

Oxide multilayer heteroepitaxy combining Mott-insulator vanadium dioxide (VO2) films and functional conducting/ferroelectric/dielectric films opens new opportunities in creating functional devices with applicability in the field of nonvolatile memories for neuromorphic devices. The growth of high quality VO2 films is challenging due to the necessity of precise control of the vanadium cation valence state. In this study, the authors report on electrical and structural properties of VO2 thin films deposited on various single crystal oxide substrates commonly used in oxide electronics and on PbZrxTi(1−x)O3/SrRuO3 ferroelectric heterostructures deposited on SrTiO3 and GaScO3 single crystal substrates. The optimized VO2 films exhibit a metal-to-insulator phase transition on all applied substrate/film combinations.

Single crystal SrTiO3 layers were grown on GaAs using both molecular and atomic oxygen and the interfaces were probed using room temperature photoluminescence and in-situ X-ray photoemission spectroscopy. The increase in PL intensity for the oxide/GaAs structure in which molecular oxygen was used suggest a decrease in the density of interfacial defects resulting in some level of Fermi level unpinning. When atomic oxygen was used during growth the interface appears to have an increase in the density of defects and a pinned Fermi level similar to that of a GaAs layer with a native oxide. X-ray photoemission measurements indicate an increase in the Ga–O bonding at the interface when the plasma source was used with an addition of As–As bonding not present in the sample grown using molecular oxygen. These results suggest the possibility of using a crystalline oxide as a gate dielectric in III–V MOSFET devices.

Graphical abstractDisplay Omitted Single crystal ferroelectric oxides were grown on both Si and GaAs.Molecular beam epitaxy of BaTiO3 using molecular oxygen.STEM reveals oxide/GaAs interface is more stable to reaction with diffused oxygen.PFM and PFS measurements demonstrate ferroelectricity on both Si and GaAs substrates. Epitaxial ferroelectric BaTiO3 layers were deposited on both Si and compound semiconductor substrates using molecular beam epitaxy. The films were grown using molecular oxygen and were found to be c-axis oriented as determined from X-ray diffraction measurements. High resolution transmission electron microscopy indicated the interface between the oxide and GaAs is free of structural defects while a thick layer of amorphous SiO2 layer is present at the interface of the oxide and Si. Ferroelectric properties of the BaTiO3 films were measured using piezoresponse force microscopy and spectroscopy. The BTO films show a piezoresponse amplitude ~5pm/V, and a coercive voltage of Vc=1-2V with an as-grown polarization along the growth direction consistent with TEM observations.

The growth of heterostructures lattice matched to InAs(100) substrates for high mobility electronic devices has been investigated. The oxide removal process and homoepitaxial nucleation depends on the deposition parameters to avoid the formation of surface defects that can propagate through the structure during growth which can result in degraded device performance. The growth parameters for InAs homoepitaxy were found to be within an extremely narrow range when using As 4 with a slight increase using As 2 . High structural quality lattice matched AlAs x Sb 1− x buffer layer was grown on InAs(100) substrates using a digital growth technique with the AlAs mole fraction adjusted by varying the incident As flux. Using the AlAs x Sb 1− x buffer layer, the transport properties of thin InAs channel layers were determined on conducting native substrates.

We demonstrate MOVPE-growth of InAs/AlAs0.16Sb0.84/GaSb and InAs/AlAs0.16Sb0.84/InAs heterostructures of excellent quality as observed by transmission electron microscopy and x-ray diffraction 2-theta-omega and rocking curve scans with full width at half maximum routinely below 100 arcsec. Key points regarding interface control for heteroepitaxial nucleation are reviewed and the choice of suitable precursors to minimize the incorporation of C and O are discussed.

A procedure has been developed for the preparation of clean, ordered InSb(001) surfaces outside epitaxial growth systems. This involves deposition of Sb caps onto freshly grown InSb(001) in a MBE system. The cap protects the underlying InSb from atmospheric contamination and can be removed subsequently from the InSb surface by thermal treatment alone to regenerate an ordered InSb(001) surface suitable for surface science experiments. HREELS measurement show that the carrier concentration at the surface of Si-doped InSb(001) ( n + = 1 × 10 18 cm −3 ) prepared in this way is close to the bulk value.

InAs nanowires (NW) grown by MOCVD with diameter d as small as 10 nm and gate-all-around (GAA) MOSFETs with d = 12–15 nm are demonstrated. I on = 314 µA/µm, and S sat =68 mV/dec was achieved at V dd = 0.5 V (I off = 0.1 µA/µm). Highest g m measured is 2693 µS/µm. Device performance is enabled by small diameter and optimized high-k/InAs gate stack process. Device performance tradeoffs between g m , R on , and I min are discussed.

Metal oxide semiconductor field effect transistors (MOSFETs) are diverging from the exclusive use of silicon and germanium to the employment of compound semiconductors such as SiGe and InGaAs to further increase transistor performance. A broader range of channel materials allowing better carrier confinement and higher mobility could be employed if a universal control monolayer (UCM) could be ALD or self-limiting CVD deposited on multiple materials and crystallographic faces. Silicon uniquely bonds strongly to all crystallographic faces of InGa1−xAs, InxGa1−xSb, InxGa1−xN, SiGe, and Ge enabling transfer of substrate dangling bonds to silicon, which may subsequently be passivated by atomic hydrogen. Subsequently, the surface may be functionalized with an oxidant such as HOOH(g) in order to create a UCM terminating Si-OH layer, or a nitriding agent such as N2H4(g) in order to create an Si-Nx diffusion barrier and surface protection layer. This study focuses on depositing saturated Si-Hx, and Si-OH seed layers via two separate self-limiting CVD processes on InGaAs(001)−(2x4), and depositing a Si-Nx seed layer on Si0.5Ge0.5(110) via an ALD process. XPS in combination with STS/STM were employed to characterize the electrical and surface properties of these silicon containing control layers on InGaAs(001)−(2x4) and Si0.5Ge0.5(110) surfaces. MOSCAP device fabrication was performed on n-type InGaAs(001) substrates with and without a Si-Hx passivation control layer deposited by self-limiting CVD in order to determine the effects on Cmax, frequency dispersion, and midgap trap states.

We have used X-ray photoelectron diffraction (XPD), low energy electron diffraction (LEED), and low energy ion scattering (LEIS) to determine the atomic structure of V thin films grown on the Al(100) single crystal surface. For V film thicknesses ranging from 0.75 ML–7 ML, the LEED patterns show no significant changes from the p(1 × 1) symmetry of a clean Al(100) surface, other than becoming more diffuse for higher V coverage. XPD and LEIS spectra indicate that during the initial deposition (1–3 ML) V atoms diffuse into the Al lattice, and tend to accumulate at the surface during subsequent deposition. Strain associated with the lattice mismatch for V and Al is likely relieved by the formation of a surface alloy during the first few ML's of V deposition. For 7 ML V coverage, XPD and LEED showed that an ordered V structure is stabilized on the Al(100) surface. Due to the close resemblance of the V and Al XPD polar scans, we conclude that V and Al are occupying similar lattice sites in tetragonally distorted bcc lattice, although the specific lattice location of the V and Al atoms is not clear.

The growth and bonding chemistry at a gate dielectric Ga 2 O 3 /GaAs interface is investigated using in-situ photoemission techniques. A multi-chamber molecular beam epitaxy/analysis system allows for the controlled deposition of III-V and oxide layers and the probing of these layers without exposure to atmosphere. The growth of Ga 2 O 3 on a (2 x 4) reconstructed GaAs surface proceeds with molecules of Ga 2 O insertion into pairs of As-dimers with the surface void of As-0 bonding. Subsequent growth involved the combination of Ga 2 O with oxygen to form Ga 2 O 3 . However, for stoichiometric Ga 2 O 3 , the substrate temperature > 440 °C is required to provide the necessary energy for the reaction. This growth process is unique and represents a method for unpinning the Fermi level for GaAs with a low level of interface state density required for the fabrication of enhancement mode MOSFET devices.

Air exposed III-V surfaces nearly always have electronic defects which prevent full modulation of the Fermi level thereby impeding their use in practical semiconductor devices such as metal oxide field effect transistors (MOSFETs). For a high speed device, the air induced defects and contaminants need to be removed to reduce trap states while maintaining an atomically flat surface to minimize interface scattering thereby maintaining a high carrier mobility. Using in-situ atomic scaling imaging with scanning tunneling microscopy, a combination of atomic hydrogen dosing, annealing and trimethyl aluminum dosing is observed to produce an ordered passivation layer on air exposed InGaAs(001)-(4×2) surface with only monatomic steps.

Ga"2O and In"2O oxides were deposited on In"0"."5"3Ga"0"."4"7As(001)-(4x2) surface by a high temperature effusion cell to investigate the interfacial bonding geometries and electronic structures by scanning tunneling microscopy/spectroscopy (STM/STS). At low coverage, Ga"2O molecules bond to the As atoms at the edge of the rows and preexisting Ga"2O on the surface. Annealing the Ga"2O/In"0"."5"3Ga"0"."4"7As(001)-(4x2) to 340^oC results in formation of slightly ordered islands running in the [[email protected]?10] direction and rectangle shape flat islands on the surface. At high coverage with 340^oC post-deposition annealing (PDA), Ga"2O oxides form disordered structures with the large flat terraces on the surface. Conversely, at high coverage with 380^oC PDA, In"2O on In"0"."5"3Ga"0"."4"7As(001)-(4x2) forms ordered structures running in the [110] direction. STS results show that Ga"2O oxide does not passivate the interface nor unpin the In"0"."5"3Ga"0"."4"7As(001)-(4x2) surface consistent with its inability to form monolayer ordered islands on the surface; conversely, In"2O/In"0"."5"3Ga"0"."4"7As(001)-(4x2) has an ordered monolayer coverage and is unpinned.

Electrical interface quality of various high- k dielectrics on GaSb, including Al2O3, HfO2, LaAlO3, GdScO3, and HfO2/Ga2O3 bilayer has been studied and compared with reference low (AlGaSb) and high Dit (native oxide) interfaces using photoluminescence intensity measurements for the first time. Al2O3 and HfO2/Ga2O3 bilayer dielectrics are identified with the lowest interface recombination velocity (S=7×104 cm/s) and consequently Dit integrated across essentially the entire bandgap. However, S for even the best identified high- k dielectrics is elevated by 140× over the low Dit AlGaSb reference indicating the need of further improvements for envisioned use in Sb based MOSFETs.

The suitability of oxide/GaAs interfaces for MOSFET applications has been investigated. Electrical properties of Ga2O3/GaAs interfaces, dielectric stacks utilizing the Ga2O3/GaAs interface, and Al2O3/GaAs interfaces have been studied using a set of independent techniques, including admittance-voltage (ac C-V and G-V at 25°C and 150°C), quasi-static static C-V, photoluminescence intensity (PL-I), and MOSFET I-V measurements. The side-by-side comparison reveals the fundamental differences in their respective data sets. The GdGaO/Ga2O3/GaAs system has been found to exhibit a U-shaped Dit distribution with a midgap Dit plateau of 2 - 3 × 1011 cm-2 · eV-1, which has allowed manufacturing GaAs MOSFETs with dc performance close to ideal model predictions. Some other ternary oxides such as GdScO3 and LaAlO3 can also be deposited on a Ga2O3 template without disrupting the Ga2O3/GaAs interface. Beyond GaAs bulk, the use of a surface heterostructure has been investigated, which shifts, in energy space, the mobile charge distribution in the channel layer away from a branch of rising Dit in the vicinity of Ec at the Ga2O3/GaAs interface. In contrast, Al2O3/GaAs(100) interfaces show a typical GaAs native oxide behavior with a

Article history:Received 9 January 2010Accepted 14 July 2010Available online 23 July 2010Keywords:Scanning tunneling microscopyIndium arsenideSemiconducting surfacesSurface chemical reactionAtomic layer depositionOxidants The substrate reactions of three common oxygen sources for gate oxide deposition on the group III rich InAs(0 0 1)-(4×2)/c(8×2) surface are compared: water, hydrogen peroxide (HOOH), and isopropyl alcohol(IPA). Scanning tunneling microscopy reveals that surface atom displacement occurs in all cases, but viadifferent mechanisms for each oxygen precursor. The reactions are examined as a function of post-depositionannealing temperature. Water reaction shows displacement of surface As atoms, but it does not fully oxidizethe As; the reaction is reversed by high temperature (450 °C) annealing. Exposure to IPA and subsequentlow-temperature annealing (100 °C) show the preferential reaction on the row features of InAs(0 0 1)-(4×2)/c(8×2), but higher temperature anneals result in permanent surface atom displacement/etching.Etching of the substrate is observed with HOOH exposure for all annealing temperatures. While nearly alloxidation reactions on group IV semiconductors are irreversible, the group III rich surface of InAs(0 0 1)shows that oxidation displacement reactions can be reversible at low temperature, thereby providing amechanism of self-healing during oxidation reactions.© 2010 Elsevier B.V. All rights reserved.