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Direct silicon bonding (DSB) for hybrid orientation technology has recently generated a lot of interest due to the significant performance enhancements reported for PMOS devices that are fabricated on alternative substrate orientations. Significantly higher leakage was observed for P+/N diodes if the junction depletion region was located close to the interface between the (110) and (100) Si surfaces. Hydrogen and fluorine passivation of this interface by ion implantation resulted in an order of magnitude improvement in the reverse leakage. In this brief, the experiments that performed using several dose levels of H2, F, and N implants are described. Electrical characterization data for reverse leakage, forward current, and ideality factors are presented in the form of cumulative probability plots, from which it is concluded that H and F passivation by ion implantation consistently provides a significant improvement in junction leakage, as compared to an unimplanted DSB wafer. An increase in the forward resistance was observed due to the implants, as compared to bulk Si (100) control samples.

A simple model based on the representation of capacitive coupling effects between the front- and back-gate and the channels, has been developed for tri-gate and pi-gate SOI MOSFETs. The model has been validated using numerical simulation of the body factor in such devices, as well as by experimental results. The body factor is much smaller than in regular, single-gate silicon-on-insulator devices because of the enhanced coupling between gate and channel and because the lateral gates shield the device from the electrostatic field from the back gate.

The typical electrical properties of triple-gate SOI MOSFETs are investigated. The relationship between the short-channel effect (SCE) and the inter-gate coupling effect is studied as a function of the channel length and width. The three-dimensional coupling effect due to electric field penetration from substrate to channel, from source and drain to body, and from lateral gates to back interface is examined systematically by considering the fin width, channel length, and back bias variations. The gate-induced floating body effect (GIFBE), which shows partially depleted (PD) device properties in the fully depleted (FD) device is documented in n- and p-channel triplegate MOSFETs.

In order to evaluate the impact of the presence of individual doping atoms in a trigate MOSFET, three-dimensional simulations were carried out. The Poisson equation is solved numerically in the channel of the devices numerically using Comsol Multiphysics . The gate oxide thickness is 2 of a single doping impurity atom increases threshold voltage. Electrical SOI MOSFETs (MuGFETs) using numerical simulation. The presence C.A. COLINGE, W. XIONG, C. R. CLEAVELIN AND J.-P. COLINGE

Due to material properties and geometric aspects self heating simulation of silicon devices requires 3D simulation of large structures. Fully coupled electrothermal simulation in three spatial dimensions is extremely memory and CPU time intensive. This work demonstrates a simplification of the approach to a thermal only problem from which much useful information can be extracted. We have applied this approach to a typical trigate device on SOI substrate. The simulated thermal resistance is in reasonable agreement with measurements. Parameters for the width dependent compact model for the thermal resistance can readily be extracted. The dependence of thermal resistance on the thickness of the bottom oxide has also been investigated. Moreover this permits transient behavior to be simulated in much more detail than is possible to be measured experimentally. Thus time constants and thermal capacitances for thermal compact models which are usually difficult to extract experimentally may be simulated numerically.

Future CMOS technology generations may implement multi-gate architectures according to S. M. Kim et al. (2004), D Ha et al. (2004), S.-Y. Kim et al. (2005), W.-S. Liao et al. (2005), S. Maeda et al. (2004), N. Collaert et al. (2005),and C. Jahan et al. (2005), together with a change from SiO2-based to high-k gate dielectrics and a change from poly-silicon to metal gate. The purpose of this work is to identify the influences of multi-gate architecture and metal gate on gate dielectric reliability and to demonstrate the dielectric reliability trend along the road map towards a CMOS process using triple gate architecture, metal gate, and HfSiON gate dielectric

Multi-gate FETs are promising for sub-45nm CMOS technologies. To address the link between design and technology, basic digital and analog circuits are fabricated using FinFET and triple-gate FETs. Digital circuit performance, leakage currents, and power dissipation are characterized. The triple-gate FET achieves the lowest gate delay (27ps at 1.2V) and is >30% faster than FinFET with same oxide thickness of 2nm and gate lengths of 80nm. A FinFET-based Miller OpAmp achieves 45dB dc gain at 1.5V

As the challenges to conventional scaling become more difficult, strained Si/relaxed Si/sub 1-x/Ge/sub x/ structures provide a viable means of improving CMOS performance. For NMOSFETs, the tensile strain in pseudomorphic Si on relaxed Si/sub 1-x/Ge/sub x/ splits the six-fold degeneracy of the conduction band minimum, rendering increased electron mobility due to a lower in-plane effective mass and reduced inter-valley scattering. In this paper, in addition to confirming enhanced performance for strained Si NMOSFETs, we present hot-electron degradation characteristics for the first time, showing improvement over unstrained Si.

Summary form only given. The 1999 International Technology Roadmap for Semiconductors (ITRS) is currently being developed and is scheduled for release in November 1999. Key to this roadmap is the evolutionary development of manufacturable front-end processes that will help the industry maintain the historical product performance trend. This talk will focus on the key challenges, technology requirements and potential solutions as presented in the roadmap in the Front-End Process (FEP) areas of starting materials, surface preparation, etch, doping, thermal/thin films and device modeling, The talk will also explore the FEP grand challenge: a CMOS compatible, robust, high-K dielectric gate stack process.

The authors describe a 256-kbit flash EEPROM (electrically erasable and programmable read-only memory) device which requires only 5 V for program, erase, and read operations and has performance and cost comparable to that of the recently reported dual-power-supply flash EEPROMs, which require 12 V for programming and erase and 5 V for read. The memory cell consists of a floating-gate transistor and a merged-pass-gate transistor. The process is array-contactless EEPROM (ACEE), with buried source/drain for the bit lines with a tunnel oxide module and a 20-V CMOS module. The program and erase operations employ the Fowler-Nordheim current tunneled through 100-AA oxide when the proper electrical voltages are applied to the selected bit. The device and technology parameters are summarized. >

A novel tunnel diode has been developed for high-density 5-V-only flash memories. The memory tunnel diode is remote from the channel, self-aligned, sublithographic, and scalable. This remote tunnel diode provides several advantages over a conventional tunnel diode: higher junction breakdown voltage, reduced substrate current during erase, reduced tunnel oxide area, reduced cell area, and competitive cell endurance. A 256-kb 5-V-only flash memory incorporating this tunnel diode is shown to have excellent operation and reliability characteristics. >

A model is presented for an intra semiconductor user-equipment supplier-SEMATECH project effort. The on-going 0.25 /spl mu/m Source/Drain Rapid Thermal Process (S/D RTP) project is used as the basis for this model. The successful completion of this project supports the model's assertions. A methodological approach taken from the initial stages of a project to the completion generates valuable and valid data, provides a planned strategy, allows for timely allocation of resources, and results in a win-win situation for all involved. This model will be referred to as "Model for Supplier/User Partnering" or MSUP.

Direct silicon bonding (DSB) for hybrid orientation technology has recently generated a lot of interest due to the significant performance enhancements reported for p-channel metal oxide semiconductor devices fabricated on alternative substrate orientations. This letter reports on the experimental observation and density functional theory (DFT) based theoretical prediction of a valence band offset between the (100) and (110) silicon surfaces directly bonded to each other. This constitutes a different type of junction created by the presence of two different surface orientations in close proximity to each other and not by doping or material variations. Experimentally, this band offset was observed as an asymmetry in the forward and reverse current-voltage characteristics of a two terminal device designed to flow a current across the DSB interface. Further, the valence band offset obtained from DFT simulations was used in a conventional device simulator (TAURUS-MEDICI) to simulate the behavior of this struc...

The adiabatic elastic constants have been measured in single crystals of rubidium fluoride over the temperature range of 300 to 4.2 K to investigate a discrepancy with neutron scattering data. The values of the elastic constants at 0 K, extrapolated from 4.2 K, are ${C}_{11}=6.527$, ${C}_{44}=0.952$, and ${C}_{12}=1.255$ in units of ${10}^{11}$ ${\mathrm{d}\mathrm{y}\mathrm{n}/\mathrm{c}\mathrm{m}}^{2}$. The Debye characteristic temperature at 0 K (${\ensuremath{\Theta}}_{D}$) as calculated from the elastic constants is ${\ensuremath{\Theta}}_{D}=221.0$ K. A summary of Debye temperature values calculated from elastic constant data at 0 K is presented for all previously measured face-centered-cubic alkali halides.

A CMOS contactless cell array technology has been developed for a single-power-supply high-density, five-V-only flash memory and for system programmable IC applications. The technology's suitability for VLSI memories has been demonstrated by a 256-kb flash EEPROM (electronically erasable programmable read-only memory) chip. This low-current five-V-only approach has been proved, with cell area and cost comparable to recently reported high-current dual-power-supply flash EEPROMs

With trends toward smaller geometries and improved circuit performance continuing, an option being investigated is multigate FETs on SOI substrates. SOI lends itself to SOC systems due to its inherently lower noise and ease of integration of analog, digital, RF and power circuits. A critical analog circuit requirement is accurate current mirroring. Here characteristics of fully depleted FinFET current mirrors are presented. Silicon FinFET current mirrors and their bulk planar counterparts have similar performance and matching: a vital requirement for analog circuitry on this type of material.