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A 5 V-only 256 kbit CMOS flash EEPROM

Authors :
D. McElroy
P. Shah
Giovanni Santin
A. Nguyen
S. Spagliccia
R. Cleavelin
G. Savarese
Sung-Wei Lin
Sebastiano D'Arrigo
E. Tomassetti
Manzur Gill
Giuliano Imondi
Source :
IEEE International Solid-State Circuits Conference.
Publication Year :
2003
Publisher :
IEEE, 2003.

Abstract

The authors describe a 256-kbit flash EEPROM (electrically erasable and programmable read-only memory) device which requires only 5 V for program, erase, and read operations and has performance and cost comparable to that of the recently reported dual-power-supply flash EEPROMs, which require 12 V for programming and erase and 5 V for read. The memory cell consists of a floating-gate transistor and a merged-pass-gate transistor. The process is array-contactless EEPROM (ACEE), with buried source/drain for the bit lines with a tunnel oxide module and a 20-V CMOS module. The program and erase operations employ the Fowler-Nordheim current tunneled through 100-AA oxide when the proper electrical voltages are applied to the selected bit. The device and technology parameters are summarized. >

Details

Database :
OpenAIRE
Journal :
IEEE International Solid-State Circuits Conference
Accession number :
edsair.doi...........79714336ab70dd7068c8a63c873a4532
Full Text :
https://doi.org/10.1109/isscc.1989.48207