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It is usually very difficult to find the causes of low yield performance in semiconductor manufacturing. In a typical wafer probing process, when the yield is low, engineers are required to examine both the equipment and the products to clarify if the low yield performance could be contributed by the testing conditions or the products. No matter which were the main cause, the time-consuming trouble-shooting process itself demanded resources thus the overall equipment effectiveness (OEE) is also damaged. This paper dealt with the trouble shooting data of wafer probing process. By examining the main factors that may affect the yield and equipment downtime in the wafer probing process, this study conducted various experiments to explore the relationship between yield and various wafer probing settings such as cleaning sheet size, probing overdrive, touch down time, and contact resistance. As a results, the optimal conditions of the main factors for improving yield and OEE are presented.

A prototype RF probe card is assembled to test the feasibility of Pogo-pins as robust probe tips for the automized testing of multiple-port millimeter-wave circuits. A custom-made ceramic housing machined from a low-loss dielectric holds an array of 157 Pogo-pins, each with 2.9 mm-length in fixed positions. The ceramic housing is then mounted onto a probe-card PCB for power-loss measurements on two signal-ground Pogo-pin connections arbitrarily selected from the array. The probing results on a test circuit with a simple thru-line indicate a successful power transfer with a small insertion loss of less than 0.5 dB per single Pogo-pin connection up to 25 GHz. A new probe card design using shorter Pogo-pins is being prepared to extend the operation frequency to beyond 40 GHz.

In this present work, a highly damped deployable solar panel module was developed for application in the 3 U CubeSat. The solar panel proposed herein is effective in guaranteeing the structural safety of solar cells under a launch environment owing to the superior damping characteristics achieved using multilayered stiffeners with viscoelastic acrylic tapes. A holding and release action of the solar panel was achieved by a new version of spring-loaded pogo pin-based burn wire triggering mechanism. A demonstration model of high-damping solar panel assembly was fabricated and tested to validate the effectiveness of the design. The holding and release mechanism achieved using a pogo pin was functionally tested through solar panel deployment tests under ambient room temperature and a thermal vacuum environment. The design effectiveness and structural safety of the solar panel module were validated through qualification-level launch and in-orbit environment tests.

Catering to a large undergraduate laboratory class requires the experiments to be robust, low maintenance, and easy to set up with low cost test equipment at the disposal of most university laboratories. Most introductory undergraduate semiconductor device laboratory courses utilize packaged semiconductor integrated circuit chips to illustrate the functioning and applications of fundamental semiconductor devices such as diodes and transistors. While such methods do justice to the illustration of device concepts, the packages abstract the device physics and manufacturing and promote a "black-box" mentality towards device engineering. We have proposed and implemented a novel undergraduate device laboratory experiment, where metal oxide semiconductor capacitor (MOSCAP) devices were designed and fabricated at our university cleanroom and provided to students to perform basic capacitance-voltage profile measurements. To allow over a hundred students to simultaneously perform the experiments, we fabricated miniature test jigs that served as probe stations with spring-loaded pogo pins to make electrical contact with the devices. Using a simple op-amp based circuit that is easy for second year undergraduates to analyze, students are able to successfully extract device parameters such as substrate doping density and flat-band voltage using this experiment, and visualize the different modes of operation of a MOSCAP. (C) 2018 American Association of Physics Teachers.

Charge Device Model (CDM) events contribute to most of the Electrostatic Discharge (ESD) failures of semiconductor devices in the field. One of the major components of a CDM tester is a grounded pogo pin/probe which is used to create a discharge path for the charged device. There are many device packages in the market, however, this paper will focus on the most common flip chip packages types in the industry - Ball Grid Array (BGA), Pin Grid Array (PGA) and Land Grid Array (LGA). Three pogo probe types will be used and are described in detail in the paper. This study recommends the best fit pogo probe tip type for each package type based on the magnitude and standard deviation of the discharge current. The results and statistical methods can be useful for all Reliability engineers in helping them to choose the most appropriate pogo probe type for the various packages. Choosing the right pin can increase the robustness and quality of CDM testing.

As a demand for electrical systems with a wide data bandwidth has increased, high-performance packages ensuring high data rates, such as low power double data rate series, have become common. The need for high-performance test sockets has also emerged to test these packages. However, a conventional pogo pin socket has a limited test bandwidth due to the parasitic components arising from its spring. On the other hand, a silicone rubber socket satisfies the wide bandwidth requirement because it has low parasitic components due to high-density conductive metal powders in an elastic silicone rubber. In this paper, we propose an RLGC equivalent circuit model of a silicone rubber socket and first experimentally verify it. The proposed model is experimentally verified in the frequency domain by comparing the insertion loss obtained from the proposed model to the measurement up to 20 GHz. The proposed model is experimentally verified in the time domain by comparing the eye diagrams obtained from the proposed model to the measurement at a data rate of 12.5 Gb/s. Also, the insertion loss of the sockets with varied height, diameter, and pitch is analyzed using the proposed model. The proposed model provides physical insight of a silicone rubber socket, and it allows to determine whether a socket is reliable for testing high performance packages in a short time. It also gives us the idea how to design a high-performance test socket. Furthermore, we discuss the current capacity and life cycle of the silicone rubber socket in terms of signal integrity as well.

This study investigated the effects of electrical contact resistance (ECR) on pogo pins used in mobile phones, chargers, digital cameras, Bluetooth headsets, medical equipment, and other electronic products with different surface roughness. Experimental results revealed that metallic wear debris is generated by fretting motion and formation of a third body on rough surfaces without removal by fretting motion, thus increasing ECR. Wear debris does not easily form the third body at contact areas of smooth surfaces and causes formation of metal–metal contact pattern. Results showed low ECR with fretting motion. 3D and 2D profiles of contact area verified the definition of contacting high spots, further explaining increases in ECR.

CubeSats are revolutionary to the space industry and are transforming space exploration which enables the next generation of scientists and engineers to complete all phases of space missions. Deployable solar panels have been widely used for the generation of enough power in CubeSats due to their limited volume area for solar cell integration. In general, the cable cutting release mechanism have been used in 1U-3U small satellites because of its simplicity and low cost. However, this mechanism has a low constraint force and is unable to apply constraints along the in-plane and out-of-plane directions. In this study, for the improvement of the conventional cable cutting mechanism, a spring-loaded pogo pin-based nichrome burn wire holding and release mechanism (HRM) was proposed and fabricated. The pogo pin constitutes an immensely attractive function for the holding and release mechanism of solar panels because it works as an electrical interface to provide power, a separation spring to initiate the reaction force to deploy the panels, and a status switch to determine deployments. In addition, the proposed mechanism guarantees the loading capability along the in-plane and out-of-plane directions of solar panels, the synchronous release of multiple panels, and a handling simplicity that differentiates it from the conventional mechanism. The design feasibility, structural safety, and reliability of the mechanism were verified through functionality tests and launch and on-orbit environmental tests. The proposed pogo pin-based holding and release mechanism would be equally applicable for other CubeSat deployable appendages.

Field Induced Charged Board Events (FICBE) experiments were conducted. The waveforms were verified using charged device model (CDM) standards. The discharge probe was constructed to determine the electrostatic discharge sensitivity of a PCB. The standard CDM current waveforms were used as a reference to ensure proper function of the discharge probe. The investigation revealed that a lower impedance of a pogo pin improved the sensitivity. The parallelizing of a pair of 2 Ω resistors reduced the parasitic inductance. Inclusion of a ferrite bead on the current sensing wires reduced the common mode noise. This test bench complies with standard CDM current waveforms.

Nowadays, begin increasing gradually deep searches on Brain Computer Interface (BCI) technologies by Academic Institutes and Research Laboratories with newly technological advancements. However, This research area needs still low cost solutions in order to become widely research topic all around the world. There are leading important reasons at that point which The used equipment is expensive and professional utilities. Many parameters of them are not allowed to changing flexibly in point of increasing effectiveness. In this paper, we cover the developing a low cost and productive BCI hardware and performance results over commercial grade counterparts. In this work, we also developed an active dry electrode which is based on a special pin which is called the pogo pin. Finally, In order to test the developed equipment, the EEG measurements are implemented in Real-Time. The Result shows that The System is able to manage near results to the commercial version while is maintaining reasonable price and providing more portability over them

CDM discharges exhibit a fast initial current step when the stray capacitance of the pogo pin is charged. It is demonstrated that the high slew rate can damage sensitive gate oxides. The miscorrelation of CDM and CC-TLP methodologies is addressed by applying pulses with 20 ps rise time.

A large 9-10 GHz tile-based scalable phased-array system (over 128 elements) is built by flip-chip bonding of elementary antenna-in-package (AiP) modules on a large interposer PCB. Each module has a top radiating surface and a bottom BGA bonding surface. Due to the strict spacing requirement of a phased-array system, rework of any failed modules from the interposer PCB is prone to create more damages to the system and is prohibited. It is necessary to have a reliable and Automatic Test Equipment (ATE)-compatible test procedures to pre-screen qualified elementary modules for bonding. However, conventional ATE-compatible test jig designs can neither receive radiation signals from antenna nor feed test signals into the antenna. In this paper, a waveguide jig for AiP pre-screening is proposed. This jig system consists of a WR-90 adapter, a horn antenna, a Torlon cap and socket with POGO pins, and a PCB to interface with ATE. To test AiP transmitter, controls and test signals are provided through PCB connectors, with radiation signals collected from the WR-90 adaptor. To test the AiP receiver, radiation signals are feeding through the WR-90 adaptor, and the receiver output signals are collected from the PCB connectors. To calibrate waveguide jig return loss, a set of AiP SOL modules are used to remove PCB and test fixture loss from the overall system loss. The waveguide jig achieves a flat simulated −2.4 dB from AiP antenna port to waveguide port from 8 to 12 GHz. This waveguide jig provides a fast and reliable approach to select qualified AiP for phased array system assemblies, and the final system-level over-the-air testing.

A landing probe design is proposed in this paper based on pogo-pins. Landing probes are usually used to obtain TDR and S-parameters of the device under test (DUT) so that the performance of the DUT can be evaluated. This design has two major advantages. First, it is durable. Second, it can be easily integrated into automated testing systems. The designed probe works well up to 20 GHz, which is validated by measurement.

We demonstrate a pogo pin package for a superconducting quantum processor specifically designed with a nontrivial layout topology (e.g., a center qubit that cannot be accessed from the sides of the chip). Two experiments on two nominally identical superconducting quantum processors in pogo packages, which use commercially available parts and require modest machining tolerances, are performed at low temperature (10 mK) in a dilution refrigerator and both found to behave comparably to processors in standard planar packages with wirebonds where control and readout signals come in from the edges. Single- and two-qubit gate errors are also characterized via randomized benchmarking. More detailed crosstalk measurements indicate levels of crosstalk less than -40 dB at the qubit frequencies, opening the possibility of integration with extensible qubit architectures., Comment: 9 pages, 5 figures, 2 tables

A spring-loaded pogo pin as a holding and release mechanism of solar panels for cube satellite applications is proposed which functions as an electrical interface, a separation spring, and a status switch. The proposed mechanism has many advantages, including an increased loading capability, negligible induced shock level, synchronous release of multiple panels, and handling simplicity during integration. A demonstration model of the mechanism was fabricated and functionally tested under various test conditions such as different input voltages, different numbers of tightened nylon wires, and different temperatures (ranging from −40°C to 70°C).

Joint Test Action Group (JTAG) extractions will require a vast number of specialized tools. Jigs, wires, and pogo pins are just some of the commercially available hardware items that can be needed. Examiners must also be resourceful; items such as rubber bands, plastic clamps, hot glue, electrical tape, cardboard, and other specifically modified items will be necessary. Manufacturers also sell Molex parts that are specifically designed for certain model phones. 20-pin adaptors that allow connections to occur between the flasher box and the Test Access Port (TAP) wires are also available. Premade RJ45 style wire connectors are also popular and allow the opposite ends to be soldered directly to the TAP locations or the adaptor boards. 20-pin female ribbon cables can also be used to connect to the TAP locations or to adaptor boards. JTAG Finders and precise soldering units are also used when conducting JTAG exams. Hot glue, rubber bands, and cardboard also have their use.

This study presents the deposition of micro contact probe cell for IC testing deposited by dc sputtering technique on a glass substrate. Micro contact with thickness of 2800-7000 nm were deposited from Copper target at sputtering power of 125 W in argon ambient at a room temperature on a base layer of copper using mask. Then, the micro contacts were investigated by using profilometer. All the obtained results show the potential viability of the novel test fixture and thus solve the limitation of the pogo pin based testing tools by replacing them with the novel IC test fixture as demonstrated in this study.

Signal transmission characteristics of the barrel-less pogo pins are analyzed using 3-dimensional electromagnetic field simulation. To obtain better signal transmission, the insertion loss and the reflection loss of the pogo pins are calculated with various signal-ground pin assignments. The effects of the signal transmission characteristics of the pogo pins on the increase in the number of the ground pin are investigated. Their characteristic impedances (Z0) are also calculated to analyze the frequency response of the pins.

The socket is regarded as a testing interface. It can measure the performance of package and fix the signal path from ATE to DUT (Device under Test). With testing frequency getting higher and higher, it will cause SI (Signal Integrity) problem when testing. The signal can't transmit completely with high frequency because of the excessive loss. Therefore, to solve this problem, use de-embedding method to remove effects caused by the socket and the load board. To simplify these complicated steps, this paper proposes the calibration kits to apply on the socket especially. Move the reference plane from the two sides of the load board to the tip of pogo pins. And use SOLT calibration method to have a standard definition table. As a result, tester can use this table to extract the error from tester and signal path and the error can be modified. In this way, tester can measure the performance of DUT directly.

Physical parameters of a pogo pin that can influence the pogo pin characteristic impedance are identified. A coupled impedance extraction method is used to extract the characteristic impedance of a pogo pin. An impedance matching technique is introduced, utilizing commercial software. A pin design experiment is presented, parameterizing the pogo pin geometry, optimizing the characteristic impedance to meet the S-Parameter requirements.

A high performance connector and USB3.1 gen2 co-design fabricated using pogo pin and new RF pin structure are presented. A prototype of the proposed pogo pin connector with a compact area size of 1.8mm pitch is implemented, and the pogo pin connector shows a wide operating bandwidth, making it easy to cover the USB 3.1 gen1 and gen2 for high speed connector operation.

This paper presents the fatigue analysis of the top part of micro contact cell via the constant amplitude loading of new electrical conductive cell contact using micro-structures. The cell is purposely developed to replace the pogo pin used in the assembly line of semi-conductor industry. The new design of micro contact cell utilizes different concept with the typical mechanism of pogo pin nowadays. The development of the cell is using a quasi-solid material as a function of spring mechanism. There are a number of studies giving promising results regarding the design of micro contact cell. This study determines the fatigue failure of micro-contact pins in order to analyze the reliability of the cell under the load of repetitive condition. This study also monitors the fatigue life of micro contact under certain parameters of the constantly repeated loading and suggests the most suitable pin number according to fatigue analysis. The fatigue lives of four (4) models of micro contact cell with different number of pins are studied. The results obtained from the study shows that 16-pin model of micro contact cell is the most reliable and robust design for the repetitive application.

A new isolation structure is integrated in the test socket to reduce the crosstalk between pogo pins with various pin patterns and different signal to ground (S/G) ratios. It comprises inserted vias to shield the signal coupling and two metal planes to connect the inserted vias with the ground pogo pins. The crosstalk between pogo pins with and without the isolation structure is simulated and investigated by 3-D full wave analysis. A systematic design methodology is established to determine various structural parameters. It is found that the optimal pin radius to pitch ratio is about 0.2, thereby achieving crosstalk and reflection both smaller than -20 dB for all considered patterns from dc to 10 GHz. Experimental results are in good agreement with the simulation and both validate the proposed design.

Novel spring contactors were designed and characterized for wafer-level interposer and high-speed package test system applications, especially for wafer-level packages. These contactors can be used as replacement for vertical wafer probes as well as test sockets used in the final test. The contactor pin consists of a plunger section made of beryllium copper and a plated helical stainless steel spring wire. It is 5 mm in uncompressed total length, including the plunger and the spring. The overall diameter of the spring wire section was 0.51 mm. The design of the contactor is much simpler and more scalable than that of traditional spring pins called Pogo pins used in package tests. A test socket containing 36 contactor pins was constructed for tests and measurements. The experimental characterization shows -1-dB bandwidth of 3.73 GHz for 0.8-mm pitch, measured by the direct contact method. This experimental result correlates well with the simulated results. The rise time was 82 ps as measured by TDR, and the propagation delay was 23 ps. The electrical conduction path is through the pin and the spring, making it a reliable contact. However, the electrical path is known to be through the barrel, not the spring for the regular spring pins.

This paper describes the design and fabrication of a MEMS guide plate, which was used for a vertical probe card to test a wafer level packaged die wafer. The size of the fabricated MEMS guide plate was 10.6 × 10.6 cm. The MEMS guide plate consisted of 8,192 holes to insert pogo pins, and four holes for bolting between the guide plate and the housing. To insert pogo pins easily, an inclined plane was defined at the back of each hole. Pitch and diameter of the hole were 650 and 260 µm, respectively. In order to define inserting holes and inclined planes at an exact position, silicon MEMS technology was used such as anisotropic etching, deep reactive etching and more. Silicon was used as the material of the guide plate to reduce alignment mismatch between the pogo pins and solder bumps during a high temperature testing. A combined probe card with the fabricated MEMS guide plate showed good x–y alignment and planarity errors within ±9 and ±10 μm at room temperature, respectively. In addition, x–y alignment and planarity are ±20 and ±16 μm at 125°C, respectively. The proposed MEMS guide plate can be applied to a vertical probe card for burn-in testing of a wafer level packaged die wafer because the thermal expansion coefficient of the MEMS guide plate and die wafer is same.

A new concept of compromise impedance match design is proposed for pogo pins with various signal-ground patterns. To begin with, the methodologies of equivalent circuit modeling for single-ended and differential pogo pins are described. A de-embedding technique is proposed to eliminate the effect of a specialized test fixture for the characterization of the pogo pins. Good agreement is found from the comparison between measured and simulated results, which validates the modeling and simulation methodologies. Then, the reflection of pogo pins with various signal-ground patterns is investigated and the optimal pin radius to pitch ratio is found to be 0.20-0.21, thereby achieving a return loss better than 15 dB for all these patterns in both single-ended and differential configurations from dc to 10 GHz. In addition, the effects of pin length are considered and a general design chart is constructed for determining the pogo pin geometry and the applicable impedance range to meet the specification on the return loss. Several compromise impedance design applications demonstrating the proposed methods are given.

A practical quantum computer requires quantum bit (qubit) operations with low error probabilities in extensible architectures. We study a packaging method that makes it possible to address hundreds of superconducting qubits by means of coaxial Pogo pins. A qubit chip is housed in a superconducting box, where both box and chip dimensions lead to unwanted modes that can interfere with qubit operations. We analyze these interference effects in the context of qubit coherent leakage and qubit decoherence induced by damped modes. We propose two methods, half-wave fencing and antinode pinning, to mitigate the resulting errors by detuning the resonance frequency of the modes from the qubit frequency. We perform electromagnetic field simulations indicating that the resonance frequency of the modes increases with the number of installed pins and can be engineered to be significantly higher than the highest qubit frequency. We estimate that the error probabilities and decoherence rates due to suitably shifted modes in realistic scenarios can be up to two orders of magnitude lower than the state-of-the-art superconducting qubit error and decoherence rates. Our methods can be extended to different types of packages that do not rely on Pogo pins. Conductive bump bonds, for example, can serve the same purpose in qubit architectures based on flip chip technology. Metalized vias, instead, can be used to mitigate modes due to the increasing size of the dielectric substrate on which qubit arrays are patterned.

The effects of oxide etch on the surface morphology of metals for industrial application is a common cause of electrical contacts failure, and it has becomes a more severe problem with the miniaturization of modern electronic devices. This study investigated the effects of electrical contact resistance on the contactor under three different atmospheres (oxygen, air, and nitrogen) based on 99.9% copper/pogo pins contacts through fretting experiments. The results showed the minimum and stable electrical contact resistance value when shrouded in the nitrogen environment and with high friction coefficient. The rich oxygen environment promotes the formation of cuprous oxide, thereby the electrical contact resistance increases. Scanning electron microscope microscopy and electron probe microanalysis were used to analyze the morphology and distribution of elements of the wear area, respectively. The surface product between contacts was investigated by x-ray photoelectron spectroscopy analysis to explain the different electrical contact properties of the three tested samples during fretting.

Integrated Circuit (IC) product test in semiconductor manufacturing industry is commonly conducted through the socket pogo pins contacting with the IC products. The socket pogo pins can be degraded due to repeatedly plugging-into and pulling-out from the socket. Degradation in socket pogo pins will greatly affect the accuracy of final test in semiconductor manufacturing, which in turn results in economic and reputation losses of manufacturers. How to rapidly and accurately detect the degraded pogo pins is still unresolved. In addition, the very huge data produced by a large amount of tester machines will further bring difficulties into degradation detection of socket pogo pins. Focusing on those existing problems in semiconductor manufacturing, this paper proposed a data driven framework with adopting data mining techniques to tackle them. This framework transforms the test data generated by manufacturing machines into human readable format and then analyzes them by data mining techniques, which empowers the manufacturing engineers to automatically detect the degraded socket pogo pins from the test data. Extensive experimental studies with real data were carried out and the results show great application prospect of the proposed framework.

This paper presents a comparison of two different printed circuit board (PCB) via field designs for high density ATE pogo pin interconnects running at Gb/s data rates. The first design is a simple straight through, one-for-one, pogo pin to via design while the second is a higher performance via design that does a transformation of the pogo pin pitch. The higher performance design takes the non-uniform signal/ground pin map of the high density pogo block and translates it to a uniform signal-ground-signal topology to increase the useable bandwidth.

In the design of traditional IC only take into the effect of IC and load board, but ignored the effect of testing sockets during testing. With testing frequency get higher and higher, signal will easily have signal integrity (SI) problem. Higher frequency couldn't achieve goal because of the loss on the transmission path. And the most easily part cause loss was the impedance matched socket. To overcome the signal loss problem, this project proposed an ideal design of sockets. The reasons of signal loss are impedance or the long path. We can only try to shrink the path to overcome the later. And this project is to improve impedance mismatched problem. QFN (Quad Flat No Leads) for example, traditional sockets placed copper cube and thermal ground pin in the middle of sockets to release heat. And placed I/O pins under IC's leads. Signal will pass through pogo pin and reach the load board. But signal will reflect because of impedance mismatched. This project use transmission line theory to match the impedance by change the distance between copper and I/O pin.

Contactor pin is commonly used as the test tooling to enable million times of repeatability functional testing in manufacturing. Simulation should be performed before contactor sent for prototyping. The objective is to optimize the design according to device performance and avoid design faulty which may lead to higher testing cost. This paper introduces the methodology on contactor pin characterization specifically the pin inductance that are helpful for high speed tooling engineer to access their contactor's performances. The impact of the contactor pin design, topology and contactor housing design will be explained in this paper. Indirectly, this is to emphasize the importance of assessing the contactor by considering many design factors instead of assessing in ideal way. It is widely applicable to any electronic devices testing that need contactor.

In this paper we propose a simple, reusable and non-intrusive approach for programming the Zolertia-Z1 mote through the JTAG-port. Programming the Zolertia-Z1 mote is generally achieved by using the Contiki Boot Script Loader and a USB cable. However, complications arise when building programs which exceed the 64kB-boundary of program memory. Special care must be taken in order to fully utilize the 92kB of available memory. At one hand, a 20 bit compiler is needed to support the complete available memory. At the other hand, a JTAG connection must then be used in order to flash the program onto the MSP430-microcontroller of the Zolertia-Z1 mote. Solutions exist in the aim of facilitating the JTAG-programming. However, these solutions are generally not reliable or need an intrusive approach, or are prohibitively expensive. Therefore, we propose a non-intrusive, reusable and reliable solution based on pogo pins. The Pogo-Pin JTAG Programmer Box consists out of an adapter board and the box itself. The adapter board can be used separately from the box for one-time flashing. Using both at the same time ensures reliable consecutive reprogramming cycles of the Zolertia-Z1 mote.

Parameters associated with an observed variation in charged device model (CDM) ESD waveforms are shown to be pogo pin diameter, pogo pin length, distance between ground plane and charge plate, verification module disk diameter, dielectric area, and ground plane size. The effects on resulting discharge waveforms and solutions for improvement of existing CDM standards are discussed.

During the semiconductor evaluation of modern Power Management Integrated Circuit (PMIC) devices, high quality Zero-Insertion-Force (ZIF) sockets must be used in order to measure many semiconductor parts with a single dedicated hardware. The most critical part of socket is contact between the device terminal and PCB. There are couples of technology processes that can provide solid contact between the device and the rest of the circuit, but the most common technology uses so called Pogo-pin, also called spring pin. Pogo pin must have as small as possible parasitic impedance, since the signal frequency and the signal power transfer between the PMIC terminal and the rest of the circuit must be without distortions, in order to obtain correct measurement results of tested devices. In some cases, influence of Pogo-pin parasitic impedance can lead to the partial damage of the device internal structure. This article should point to the potential problems using simulation results and should describe the simple procedure of Pogo-pin impedance characterization using network analyzer with appropriate aperture. Couples of measurements results from different Pogo-pin suppliers are also shown in this example with some practical results.

Integrated circuit packages are tested for component function before shipped to customers. The testing involves probing of the package leads with Pogo pins/spring probes having sharp-edge tips manufactured from harder BeCu or Pd alloys. The spring-controlled pins forced onto the pad surface penetrate the surface oxide layers to establish electrical contact with the metal underneath for assessment of test parameters. However, this also can lead to form scratch marks and pad cracks on the lead surfaces and achieving good contact with minimum damage to pad surfaces is important. Also pin tips tend to deform due to mechanical interactions with the package lead & wear upon continuous insertions. Since reliability testing over millions of insertions can be a very time consuming process, here's, an attempt to utilise simulation method/approach to quantify plunger pin insertion induced stress/strain at the pin-pad interfaces & evaluate variations in tip profile on probe and pad performance in a standard manner. This paper describes a non-linear contact analysis of spring-loaded palladium vertical probes with wedge & crown tip profiles insertion onto lead surface during package testing and evaluating penetration induced deformation, stress and strain at contacting interfaces of both probe tip and pad and compared with indentation measurements. The non-linear analysis involves Bilinear Isotropic hardening plasticity (BISO) elasto-plastic material and rough contacts in Ansys Workbench environment.

We introduce an automated digital microfluidic (DMF) platform capable of performing immunoassays from sample to analysis with minimal manual intervention. This platform features (a) a 90 Pogo pin interface for digital microfluidic control, (b) an integrated (and motorized) photomultiplier tube for chemiluminescent detection, and (c) a magnetic lens assembly which focuses magnetic fields into a narrow region on the surface of the DMF device, facilitating up to eight simultaneous digital microfluidic magnetic separations. The new platform was used to implement a three-level full factorial design of experiments (DOE) optimization for thyroid-stimulating hormone immunoassays, varying (1) the analyte concentration, (2) the sample incubation time, and (3) the sample volume, resulting in an optimized protocol that reduced the detection limit and sample incubation time by up to 5-fold and 2-fold, respectively, relative to those from previous work. To our knowledge, this is the first report of a DOE optimization for immunoassays in a microfluidic system of any format. We propose that this new platform paves the way for a benchtop tool that is useful for implementing immunoassays in near-patient settings, including community hospitals, physicians' offices, and small clinical laboratories.

The Karlsruhe Tritium Neutrino Experiment (KATRIN) will detect tritium beta- decay electrons that pass through its electromagnetic spectrometer with a highly- segmented monolithic silicon pin-diode focal-plane detector (FPD). This pin-diode array will be on a single piece of 500-{\mu}m-thick silicon, with contact between titanium nitride (TiN) coated detector pixels and front-end electronics made by spring-loaded pogo pins. The pogo pins will exert a total force of up to 50N on the detector, deforming it and resulting in mechanical stress up to 50 MPa in the silicon bulk. We have evaluated a prototype pin-diode array with a pogo-pin connection scheme similar to the KATRIN FPD. We find that pogo pins make good electrical contact to TiN and observe no effects on detector resolution or reverse-bias leakage current which can be attributed to mechanical stress., Comment: 13 pages, 7 figures

Mechanical design and analysis of innovative test socket is done in this study by using ANSYS as Finite Element Analysis (FEA) software. It is designed to solve the problems brought to the IC leads by pogo pins in the IC testing process. Proposed test socket is formed as an array of holes filled with electrical conductive cells. Each cell consists of three different parts, including micro-contactors, polymer house and liquid metal. Liquid metal is used to absorb the pressure and prevent damaging to the IC leads. Mechanical and electrical analysis was done on the different models with 4, 8, 12, 16 and 20 micro-contactors. The 16 pin model showed the best results. This model was analyzed with different height and the results indicate that the 5mm height electrical conductive cell has the best characteristics. In optimization process, the 16 pin model with 5 mm height was optimized by changing the polymer house material and copper thickness. The enhancement was over 50 percents in some cases such as stress, strain and deformation. Stress and strain analysis shows that all of models have better results with many novelties to be commercially viable.

Semiconductor testing plant usually increases tester utilization and reduces overkill to increase profits and decreases the cost of replacement parts. Traditionally, IC product test is conducted through the socket pogo pin contact with IC pin or solder ball. Semiconductor test facility solves the oxidation of socket pogo pin, tin slag adhesion, and adhesion of dust and other problems by means of brushing it with a specific cleaning solution. Socket pogo pin is directly to be cleaned by brushing back and forth. This action will cause the gold-plated surface layer of socket pogo pin peeling off. The cleaning fluid flows into the load board along the socket pogo pin will damage the board. These phenomena decrease the life time of socket pogo pin and influence the yield of IC product test. In this study, YAG laser was used to clean the surface oxide, tin-slag, and powder layer of socket pogo pin. This non-contact cleaning method improves the test yield, machine utilization and reduces the testing cost.

This work develops a double-sided probing system and calibration method for measuring the S-parameters of vertical interconnects at the wafer, package and socket level. The applicable device under test (DUTs) include through silicon vias (TSVs), plated through holes (PTHs), pogo pins and pressure sensitive conductive rubbers (PCRs). The effects of solder bumps and balls can also be taken into account. A short-open-load-reciprocal (SOLR) calibration method is used with a reciprocal thru to instead of the conventional short-open-load-thru (SOLT) which uses a standard thru. The S-parameters can be measured up to 40 GHz with a repeatable S21 parameter accuracy of better than 0.2 dB and 1 degree in magnitude and phase, respectively. Additionally, the eye diagrams are measured at a maximum data rate of 40 Gb/s and a minimum rise time of 10 ps with the help of Agilent physical layer test system (PLTS).

We have designed and tested two amplification circuits for measuring HL-1 cardiac action potentials, single-ended and differential. We describe the improvements in performance resulting from the differential configuration. These improvements are especially important considering the cell culture's aqueous environment that experiences DC drift. In addition we have designed and fabricated a 4×4 gold microelectrode array and cultured HL-1 cells on the electrodes. The array is connected to our circuit through a custom made Pogo pin jig to allow for easy measurements from the electrodes while cells are being cultured. This setup allowed us to obtain initial results for modeling the transfer function of the cell culture as a passive device network. Testing has confirmed the circuits are capable of filtering low frequency signals including DC drift and frequencies above 5 kHz. The amplification was achieved through two gain stages with a total gain of 60 dB for the single-ended and 46 dB for the differential circuits.

In this paper, a novel electrical contact mechanism that serves as a low insertion-force test socket is investigated by Finite Element Analysis. The proposed electrical contact mechanism is made up of three different materials such as polymer, metallic alloy and liquid metal. Due to the uneven stress distribution of the conventional pogo pin systems, large puncture marks occur on the integrated circuit contacts. The proposed design enhances the overall stress distribution performance of the electrical contact with integrated circuit as found from the analysis. Parameters such as the number of microstructure contacts and the pitch size among them give influential impact on the overall stress distribution performance. Generally, the more the microstructure contact, the more the stress distribution gets evenness. However, the stress distribution becomes saturated when the number of microstructure contacts reaches 16 for a total area of 0.25 mm × 0.25 mm. The pitch size of 0.07 mm gives the best performance for the given total contact area. Any pitch above will set the microstructure contacts to the edges of the contact area, which decreases the stress distribution performance. A factor of safety analysis is performed for the proposed design and a value of 4.9 is achieved, which is almost 5 times greater than the minimum requirement of 1.0.

This paper proposes a new isolation structure integrated in the dielectric holder of a test socket for reducing the crosstalk noise. The isolation structure consists of inserted vias and metallic planes, connecting the inserted vias with ground pogo pins. It can provide better than −20dB crosstalk and reflection noises from DC to 10GHz, with 10dB improvement in crosstalk at 10 GHz.

This paper proposes a systematic methodology to model the single-ended and differential pogo pin structures for the analysis of signal integrity (SI), especially the reflected noise. A measurement method is developed for de-embedding the specialized fixture in the characterization of the pogo pins. The simulation and modeling methodologies are verified by the favorable comparison with the measured results from DC to 10GHz. Finally, an applicable range of impedance for satisfying the desired specifications of return loss is derived. By a design chart of the impedance versus the pogo pin geometry, the compromised impedance design charts for small reflection in different S/G ratios and pin patterns are given.

The root causes of the mechanical limitations are analyzed and their damages to the device-under-test (DUT) lead are demonstrated in this study. The evolution of microelectronics toward more densely packed contacts in a much smaller foot print has set a higher standard for the test socket used in the final test. This trend of evolution has brought several mechanical challenges for the pogo pin test socket, such as, (a) inability to overcome the trade off of the witness marks and contact resistance, (b) difficulties to target a specific contact area on a solder ball/unit leads when the pitches become too fine (c) difficulties in tolerance control as the pitch drops below 1.016 mm and (d) smaller metal contacts have lower fatigue life. All such problems are discussed here based on some experimental observations.