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Continuous scaling of device dimension pushed Si channel to its physical limit, alternative high mobility channels such as (Si)Ge and (In)GaAs have been considered to replace Si to further enhance CMOS performance. In the meantime, ultrathin body (UTB) semiconductor-on-insulator is compulsory structure for improved gate control and immunity against short channel effects in the ultimately scaled high performance and low power dissipation CMOS. To realize stacked multi- channel semiconductor-on-insulator platform on current mainstream Si wafers, layer transfer technology [1-3] utilizing direct bonding and selective etching was developed to integrate (Si)Ge or (In)GaAs channels on Si, showing great potential for ultimate device structures with heterogeneous integration. Figure 1(a) is the process flow for integrating InGaAs channel onto SiGe-on-insulator (SGOI) structure utilizing layer transfer technology [4]. It started with bottom SGOI pMOSFET fabrication. The SGOI structure was realized by 2-step Ge condensation technique, resulting in Ge content of 70%. After high k metal gate process, self-aligned Ni-SiGe alloy was formed as S/D metal. Subsequently, SiO2 interlayer was deposited by CVD, followed by CMP planarization. Then, InGaAs grown on InP was directly bonded onto SiO2 and InP substrates were selectively etched away. Finally, the top InGaAsOI nMOSFET fabrication and metal interconnection completed the CMOS fabrication. Fig. 1(b) shows the cross-sectional TEM images of fabricated InGaAs/SiGe channel stacked CMOS. Well aligned top and bottom devices are seen without any distinct defects. Figures 2 is a schematic flow for fabricating Ge/Si double channel-on-insulator structure by low temperature hetero-layer bonding technology (LT-HBT). The technology starts with the preparation of donor wafers (Fig. 2(a)) for the top Ge channel layer and host wafers (Fig. 2(b)) for the bottom Si channel layer. For donor wafers, a 200-nm-thick Ge was epitaxially grown on SOI wafer by reduced pressure CVD. After CMP planarization, ALD SiO2 is deposited onto Ge. For host wafers, implantation and dopant activation were carried out, followed by chemical treatment for Si oxidation. After surface activation by room temperature chemical treatment (Fig. 2(c)), the direct wafer bonding of both SiO2 surface was performed at 200 °C in a press machine (Fig. 2(d)). Then, the Si substrate of the donor wafer was removed with deep RIE. At this time, the BOX layer of the donor wafer serves as an etch-stop layer. Subsequently, the BOX layer and thin Si layer of the donor wafer were removed selectively in HF and TMAH solution, respectively (Fig. 2(f)). To precise control the top Ge channel thickness, a series of low damage etching process was adapted to thin down Ge (Fig. 2(g)). The realized double channel structure is fully isolated with an insulating insertion layer,[5] which is very promising for realizing novel complementary FET (CFET) with minimum process steps. The cross-sectional TEM image of Ge/Si stacked channel of CFET after high k metal gate process is demonstrated in Fig. 2(h). Even more multiple stacks can be realized by using LT-HBT. A vertically stacked three-layer structure with 2 bottom Si layers and 1 top Ge layers is also demonstrated using SOI-based donor wafers in Fig. 3, indicating the highly integrated density channel structure is possible. The feasibility of layer transfer technology has been proved for multi-channel structure with high mobility channels for N2 node and beyond. Acknowledgement This work was supported by JST Japan-Taiwan Collaborative Research Program, Grant Number JPMJKB1902, Japan and the Ministry of Science and Technology under Grant Number MOST-109-2628-E-492-001-MY3, 109-2923-E-492-001-MY3, 107-2221-E-492-016-MY3. References [1] T. Maeda et al., Appl. Phys. Lett. 109, 262104 (2016). [2] W. H. Chang et al., Mater. Sci. Semicond. Process 70, 123 (2017). [3]W. H. Chang et al., IEEE Trans. Electron Device 64, 4615 (2017). [4] T. Irisawa et al., VLSI 146 (2014). [5] T. Z. Hong et al., IEDM (2020) Figure 1

In this paper, we achieved excellent variation control, endurance enhancement, and leakage reduction in zirconium (Zr)-doped hafnium oxide (Hf1–xZrxO2) based ferroelectric films by the germination ...

In this study, ferroelectric FETs (FeFETs) and CMOS inverters are fabricated and analyzed, exhibiting 13% of 593 devices with sub-60 mV subthreshold swing (SS) at room temperature. Forming gas annealing (FGA) is found to not only enhance ferroelectricity but also significantly improve FeFET electrostatics. The experimental results indicate that FeFET with a narrow width shows weaker ferroelectric properties, and SS of sub-60 mV/dec with ID change less than two orders of magnitude. However, FeFET with a broad channel width reveals stronger ferroelectric properties, and SS of sub-60 mV/dec is over 2 orders of magnitude of Id. Finally, typical voltage transfer characteristics (VTCs) of a FeFET CMOS inverter with double sweeps at various VD from 0.6 to 2 V are demonstrated. The results show that hysteresis in a FeFET CMOS inverter could have both clockwise (CW) and counter-clockwise (CCW) loops.

For the first time, we demonstrate heterogeneous complementary FETs (hCFETs) with Ge and Si channels fabricated with a layer transfer technique. The 3D channel stacking integration particularly employs a low-temperature (200 °C) hetero-layers bonding technique (LT-HBT) realized by a surface activating chemical treatment at room temperature, enabling Ge channels bonded onto Si wafers. Furthermore, to obtain symmetric performance in n/p FETs, a multi-channel structure of two-channel Si and one-channel Ge is also implemented. Wafer-scale LT-HBT is demonstrated successfully, showing new opportunities for the ultimate device footprint scaling with heterogeneous integration.

Evolution of transistor structures, from planar, fin to gate-all-around (GAA) nanowire (NW)/nanosheet (NS), enables consecutive device scaling and performance boost. To further enhance the drive current per footprint, a vertically stacked configuration compatible with current CMOS technology may be a promising approach for extending Moore's Law. In this paper, we review the recent status of stacked FET architectures and beyond, as well as pointing out the challenges and perspectives.

This paper reports detailed analysis on switching dynamics and device variability over a wide range of temperatures for deeply scaled (40nm gate length) tri-gate ferroelectric FETs with 10nm HZO fabricated using gate first process on SOI wafers. Our experimental results manifest, 99% ferroelectric switching at room temperature and at 233K. A memory window over 5V and strong gate length dependence of memory window is observed. Highly linear and symmetric multilevel switching characteristics makes our ferroelectric FETs suitable for neuromorphic applications, as demonstrated with neural network online training simulations.

In this paper, one proposed an effective method to enhance current drivability of junctionless FETs (JL-FETs) by utilizing uniaxial tensile strain effects. The strained layers were deposited on JL-FETs on silicon-on-insulator (SOI) and bulk Si wafers, respectively. Strained JL SOI FETs show an extremely low subthreshold swing (S.S.) of 65 mV/decade with $I_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}} >10^{9}$ ; strained JL bulk FinFETs show an S.S. of 75 mV/decade with $I_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}}>10^{7}$ . For strained JL bulk FinFETs, a triangular fin shape could suppress leakage current effectively. Regardless of substrates, JL FETs showed excellent performance owing to uniaxial tensile strain technology. Analysis of leakage current in strained JL FETs included effects on Gate-induced drain leakage trap-assisted tunneling effects were discussed by ${I}_{D}$ – ${V}_{G}$ curves under various temperatures and activation energy. Compared with JL SOI gate-all-around structures, JL bulk FinFET possesses higher ${I}_{D}$ and offer the promise of higher integration flexibility for Si CMOS compatible process for the future applications.

For the first time, CMOS inverters and 6T-SRAM cells based on vertically stacked gate-all-around complementary FETs (CFETs) are experimentally demonstrated. Manufacturing difficulties of vertically stacked source and drain electrodes of the CFETs have been overcome by using junctionless transistors, thereby reducing the number of lithographic steps required. Furthermore, with post metallization treatments, both the voltage transfer characteristics (VTCs) of CMOS inverters and butterfly curves of SRAM show significant improvements due to the symmetry of nMOS and pMOS threshold voltages. Simulation shows that 3-dimensional CFET inverters have lower input parasitic capacitance than standard 2-dimensional CMOS, leading to reduced gate delay and lower power consumption.

Microwave annealing (MWA) activates dopants through solid-phase epitaxial regrowth with low thermal budget. Optimizing the microwave power during MWA is capable of realizing low defect density at the junction, suppressing the dopant diffusion, and mitigating the straggle effect of ion implantation. These favorable features of MWA facilitate the formation of extremely abrupt junction profiles in tunnel FETs (TFETs). In conjunction with the improved gate-to-channel controllability of the multiple-gate (MG) structure, we demonstrate high-performance lateral n-type Si-TFETs using a CMOS-compatible process flow with excellent band-to-band tunneling efficiency and device scalability. The 32-nm MG Si-TFET shows promising characteristics, including a high ON-state current of 41.3 $\mu \text{A}/\mu \text{m}$ , a large current ON/OFF ratio of $> 5\times 10^{7}$ , and minimal short-channel effect using $V_{G}=2$ V and $V_{D}=1$ V.

Microwave annealing (MWA) and rapid thermal annealing (RTA) of dopants in implanted Si are compared in their abilities to produce very shallow and highly activated junctions. First, arsenic (As), phosphorus (P), and BF2 implants in Si substrate were annealed by MWA at temperatures below 550 °C. Next, enhancing the substitutional carbon concentration ([C]sub) by cluster carbon implantation in (100) Si substrates with MWA or RTA techniques was investigated. Annealing temperatures and time effects were studied. Different formation mechanisms of SiCx layer were observed. In addition, substrate temperature is an important factor for dopant activation during MWA and in situ doped a-Si on oxide/Si substrate or glass were compared to elucidate the substrate temperature effect. After the discussion of dopant activation in Si substrates, low temperature formation of ultrathin NiGe layer is presented. Ultrathin NiGe films with low sheet resistance have been demonstrated with a novel two-step MWA process. In the two-step MWA process, the first step anneals the sample with low power MWA, and the second step applies higher power MWA for reducing sheet resistance. During fixed-frequency microwave heating, standing wave patterns may be present in the MWA chamber resulting in nodes and antinodes and thermal variations over the process wafer. Therefore, the effects of Si or quartz susceptor wafers on dopant activation and sheet resistance uniformity during fixed-frequency MWA were investigated.

NiSi,atransitionmetalsilicide,hasbeenincreasinglyusedforcontacts in the latest complementary metal oxide semiconductor (CMOS) devices, owing to its low temperature of formation and low Si consumption during silicidation, low sheet resistance (RS) and lower leakage current. 1,2 The use of NiSi currently faces a difficult trade-off between thickness and sheet resistance. The contact junction depth must still scale with gate length. To avoid high contact resistance and high contact leakage, no more than half the contact junction depth can be consumed in the formation of the silicide. Therefore, the silicide must become progressively thinner to accommodate the more shallow contact junction for scaled contacts. The rapid thermal annealing (RTA) has been widely used for silicidation and exhibits difficult thinthickness and phase control. Microwave annealing (MWA) 3 has been realized to activate implanted dopants through solid phase epitaxial regrowth at low temperature. 4 It is promising for achieving advanced Si or Ge CMOS because of its unique volumetric heating and low temperature due to apparent non-thermal energy transfer. 5 The advantages of replacing rapid thermal annealing (RTA) with MWA are ultra-thin NiSi formation, diffusion-less junction, improved capacity of gate oxide and lower gate leakage. In this work, a novel two-step low temperature MWA process is used to form homogeneous NiSi contact films with low sheet resistance while not sacrificing thickness and quality. During silicidation, many kinds of nickel silicide phases may appearsimultaneously. 6 Ithasbeenreportedthatthepredominantphases are Ni2Si, NiSi and NiSi2, form in the ranges 200‐350, 350‐750, and 750‐1000 ◦ C, respectively. 7 The NiSi has the lowest resistivity among three different phases and other metal silicides. Furthermore, the Ni atoms are the primary moving species during the formation of NiSi phase. It could prevent the bridging effect which results in short circuit area between gate and source/drain. 8 It is well recognized that identification of nickel silicide phases after annealing is of crucial importance to its performance, especially, while these phases are formed innano-polycrystallinelayer.Inthisstudy,weuseelectronenergy-loss spectroscopy 9‐13 andenergydispersiveX-rayspectroscopy 13,14 inconjunction with scanning transmission electron microscopy 14 (STEMEELS/EDS) in order to identify the nickel silicide phases concentrating primarily on the Z-contrast image with atomic spatial resolution, elemental analysis, bulk plasmon excitaions and the chemical bonding.

Ge peaking n- and p-FinFETs have been demonstrated by adopting neutral beam etching (NBE) and anisotropic neutral beam oxidation (NBO) processes. The irradiation-free NB processes not only suppress surface roughness but also guarantee low defect generation on the etched Ge surface. The fabricated Ge peaking FinFETs possess several unique features: (1) A peaking fin configuration with a 6-nm top-gate formed by an anisotropic NBO process at room temperature. (2) Nearly defect-free three dimensional channel surfaces by NB processes. (3) Ion and Gm improvement by NB processes as compared to that by conventional inductively coupled plasma etching (ICP). (4) Recorded high Ion/Ioff ratio and low subthreshold swing (S.S. ∼ 70 mV/dec.) of Ge n-FinFETs. (5) Excellent immunity for short channel effect of Ge FinFETs.

We propose a feasible pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge and Ge09Si01 gate-all-around (GAA) nanowire (NW) FETs with four {111} facets. The device fabrication requires only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. The proposed dry etching process involves three isotropic/anisotropic etching steps with different Cl2/HBr ratios for forming the suspended diamond-shaped channel. Taking advantages of the GAA configuration, favorable carrier mobility of the {111} surface, nearly defect-free suspended channel, and improved dopant activation by incorporating Si, nFET and pFET with excellent performance have been demonstrated, including an Ion/Ioff ratio exceeding 108, the highest ever reported for Ge-based pFETs.

A junctionless (JL) fin thin film transistor (FinTFT) with a novel shell doping profile (SDP) formed by a damage-free conformal molecular monolayer doping (MLD) method and a combination of microwave annealing (MWA) and CO2 laser spike annealing (COLSA) is demonstrated and studied. MWA drives in and partially activates the MLD dopants; the resultant SDP features an ultra-shallow depth ( 107) for 3D stacked ICs applications. Our results reveal the potential of the proposed SDP formed by MLD, MWA and COLSA enabling a JLFinTFT showing excellent performance.

In this letter, low-temperature (480°C) microwave annealing (MWA) for MOS devices with high-k/metal gate-stacks is demonstrated. The capacitance-voltage (C-V) characteristics of the MOS gate-stacks, TiN/HfO2, and TaN/HfO2, after different annealing methods are discussed. The increases in equivalent oxide thickness (EOT) of the MOS devices after dopant activation processing can be eliminated using low temperature MWA. In addition, the short channel effects in nMOSFETs annealed by MWA can be also improved because of the suppression of dopant diffusion and stabilization of EOT.

For the first time, a novel junctionless (JL) FinFET structure with a shell doping profile (SDP) formed by molecular monolayer doping (MLD) method and microwave annealing (MWA) at low temperature is proposed and studied. Thanks to the ultra thin SDP leading to an easily-depleted channel, the proposed JLFinFET can retain the ideal subthreshold swing (∼ 60 mV/dec) at a high doping level according to simulations. Poly Si based JLFinFETs processed with MLD and MWA exhibit superior subthreshold swing (S.S. ∼ 67mV/dec) and excellent on-off ratio (>106) for both n and p channel devices. Threshold voltage (V TH ) variation due to random dopant fluctuation (RDF) is reduced in MLD-JLFinFETs, which can be attributed to the molecule self-limiting property of MLD on the Si surface and quasi-diffusionless MWA at low temperature. Our results reveal the potential of the proposed SDP enabling a JLFET showing reduced variation and outstanding performance for low power applications.

For the first time, Ge CMOS with all thermal processes performed by microwave annealing (MWA) has been realized. The full MWA process is under 390 oC. It significantly outperforms conventional rapid thermal annealing (RTA) process in 3 aspects: (1) Diffusion-less junction: for easily diffused n-type dopant, phosphorous (P), the ion implantation dopant profile after the MWA activation process remains unchanged. (2) Increased C ox and lower gate leakage: the low temperature activation process leads to less Ge out-diffusion during MWA than RTA, suppressing the degradation of gate dielectric/ Ge channel interface. (3) Ultrathin 7.5nm Ni mono-germanide with low sheet resistance (Rs) and contact resistivity: after two-step MWA, a thin mono-NiGe layer was obtained which has larger crystallite size to lower Rs. Ge n- and p-MOSFET were also demonstrated. Compared to conventional RTA, the MWA gives 50% and 24% drive current enhancement for p- and n-MOSFET, respectively. These data show that the low temperature MWA is a very promising thermal process technology for Ge CMOS manufacturing.

Due to the highest electron mobility (2200 cm2/Vs) on (111) Ge surface, the n-channel triangular Ge gate-all-around (GAA) FET with (111) sidewalls on Si and L g =350 nm shows 2x enhanced I on of 110 μA/μm at 1V with respect to the devices with near (110) sidewalls. A novel process to etch away the defective Ge near Ge/Si interface from epitaxial Ge grown on SOI achieves a nearly defect-free channel, good gate control triangular gate, and larger effective width. Electrostatic control of SS= 94 mV/dec (at 1V) can be further improved if superior gate stack than EOT= 5.5 nm and D it = 1×1012 cm−2eV−1 is used. The I on can be further enhanced if the line edge roughness (LER) can be reduced. The Ge GAA n-FET is reported for the first time with CMOS compatible process, which makes the circuits integration much easier.

Very high 6.5 aspect ratio, 30nm diameter contacts are filled with a novel bottom-up Ag electroplating technology for the first time. The technology utilizes two distinct advantages of Ag over Cu: (1) Ag has the lower metal resistivity, and (2) Ag has several orders of magnitude lower diffusivity in Si than Cu. The bottom-up deposition technology intrinsically avoids the issue of seam formation arising from sidewall deposition, and thus is very promising” for future scaled contacts, even down to single digit nano-meter technology nodes.

Low temperature microwave annealing (MWA) for IC processing is promising. In this study, using microwave annealing for dopant activation and thermal stability of the high-k/metal gate is investigated. Implanted species, such as phosphorus, arsenic, and boron, can also be well-activated and diffusionless in Si after microwave annealing. The flat band voltage shift of metal gate was suppressed due to the low temperature process. The increases in equivalent oxide thickness (EOT) of the MOS devices after dopant activation processing can be eliminated by using low temperature MWA. In addition, the short channel effects in n & pMOSFETs annealed by MWA can be also improved due to the suppression of dopant diffusion and stabilization of EOT.