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We report a study on moisture effect on optical performance of monolithic silicon photonics technologies featuring V-grooves for self-aligned fiber attach. Chip-level hermetic sealing was achieved by implementing moisture barrier for the fiber coupler.

We report the hybrid flip-chip integration of III-V laser on a monolithic silicon photonics (SiPh) platform. Wafer-scale laser attach was demonstrated with the assistance of a laser cavity on a Si substrate. The attach process was accomplished through precise optical and mechanical alignment features on the laser and SiPh wafer. Efficient laser-to-photonic integrated circuit (PIC) butt-coupling with optical power up to 11 dBm was achieved through a combination of precise mechanical stops and optical alignment features. Key laser performance metrics such as mode hopping and relative intensity noise (RIN) vs. reflectivity were also studied. The impact of laser-PIC alignment on the coupling efficiency was studied through comprehensive two-dimensional (2D) and three-dimensional (3D) numerical modeling. Simulations were also performed to explore different coupler designs for optimized laser coupling performance.

The Charge Trap Transistor (CTT) technology is an emerging memory solution that turns as-fabricated high- ${k}$ /metal gate (HKMG) logic transistors into secure, embedded non-volatile memory (eNVM) elements with excellent data retention and operation capability at military grade temperatures. In other words, the CTTs offer a completely process-free and mask-free eNVM solution for advanced HKMG CMOS technology nodes. In this letter, bitcell design to enhance programming efficiency and modeling of the charge trapping behavior of CTTs in 14 nm FinFET technology is discussed.

An 8Kx192b charge trap transistor one time programmable memory (OTPM) is designed and manufactured in GLOBALFOUNDRIES 14-nm bulk FinFET technology without process adders or additional masks. A write timer state machine issues multicycle 192b parallel programming with per bit overwrite protection to minimize stress conditions during a write. On-chip generated voltages are temperature dependent, enabling writes and reads at military grade temperatures. A differential current sense amplifier with self-biased margining circuitry enables programming the OTPM twin cell with known repeatable margin across process–voltage–temperature. Hardware qualification certifies the OTPM to a 10-year 105 °C data retention specification and

3D integration technologies are becoming increasingly viable to mitigate the limitations and slowdown in traditional 2D transistor scaling. 3D-Split SRAMs, realized by splitting the bitlines (BL) and/or wordlines (WL) across two or more 3D-arranged tiers, promise improved power/performance due to reduced RC parasitics. However, their feasibility and efficacy depend on the pitch and RC parasitics of the inter-tier BEOL connections (3D-BEOL). In this work, we analyze the impact of 3D-BEOL on the 3D-Split SRAM gains, in a face-to-face (F2F) hybrid wafer bonding 3D integration technology. Two separate approaches for reducing 3D-BEOL parasitics viz (1) M Z -Supervia, & (2) M Z -less 3D-BEOL are proposed. Measurements from 64 Kb 12 nm FinFET SRAM prototype, reconfigured to capture the BL-split and the WL-split 3D SRAM effects, show up to 107 mV lower V min as well as $\sim$15% better access-time, equivalent to the performance gains from one technology node dimensional scaling.

We report a hybrid flip-chip-integrated laser attach technology on a monolithic SiPh platform. Efficient laser-to-PIC butt-coupling with optical power up to 11dBm was demonstrated through a combination of precise mechanical stops and optical alignment features.

A high-density-3D test-vehicle showcasing a synchronous cache coherent mesh interconnect design (Arm Neoverse® CMN-600) operational at frequencies up to 2.4 GHz and partitioned in 3D using 5.76µm pitch face-to-face wafer-bond 3D connections on a 12nm FinFET process is presented. The test-vehicle is designed using an industry tool compatible innovative physical implementation flow and serves as the first known industry demonstration of the IEEE 1838 3DIC Design-for-Test (DFT) standard. We demonstrate a 3D aggregate bandwidth of 307 GB/s, a record bandwidth density of 3.4 TB/s/mm2, and an energy efficiency of 0.02 pJ/bit for the 3D-stacked dies. We present measurement and analysis data from 945 dies where a total of 13.5 million signal 3D wafer-bond nets and 20 million power-delivery 3D wafer-bond nets on multiple wafer-bonded pairs are tested showing robust functionality, paving the path for 3D-stacked high performance logic-on-logic applications.

This work demonstrates face-to-face hybrid wafer bonding at GLOBALFOUNDRIES, including fine pitch characterization and processing, along with preliminary reliability results. Bonding alignment data analysis is shown, as it is imperative to have high bonding alignment in order to assure full yield of the fine pitch interconnects. As a preliminary proof- of-concept check, simple device test data is shown as a way to electrically analyze the bond quality. Limited thermal stress testing results for reliability (utilizing JEDEC-type standards) are shown as well, proving a robust build quality.

Described is a secure, multi-time programmable memory (MTPM) solution for the 14 nm FINFET node and beyond, which turns as-fabricated standard logic transistors into embedded non-volatile memory (eNVM) elements, without the need for any process adders or additional masks. These logic transistors, when employed as eNVM elements, are dubbed “Charge Trap Transistors” (CTTs). Outlined are the technological breakthroughs required for employing logic transistors as an MTPM. An erase technique, called “Self-heating Temperature Assisted eRase” (STAR), is introduced which enables 100% erase efficiency, as compared to $ erase efficiency using conventional methods, in turn enabling MTPM functionality in CTTs. For the first time, hardware results demonstrate an endurance of $> 10^{4}$ program/erase cycles. Data retention lifetime of $> 10$ years at 125°C and scalability to 7 nm have been confirmed.

This paper describes orthogonal scaling of dynamic-random-access-memories (DRAMs) using through-silicon-vias (TSVs). We review 3D DRAMs including DDR3, wide I/O mobile DRAM (WIDE I/O), and more recently, the hybrid-memory cube (HMC) and high-bandwidth memory (HBM) targeted for high-performance computing systems. We then cover embedded 3D DRAM for high-performance cache memories, reviewing an early cache prototype employing face-to-face 3D stacking which confirmed negligible performance and retention degradation using 32 nm server and ASIC embedded DRAM macros. A second cache system prototype based on POWER7 was developed to confirm feasibility of stacking $\mu {\rm P}$ and high density cache memory, with $> 2~{\rm GHz}$ operation. For test and assembly, a micro-electro-mechanical-system (MEMS) probe-card with an integrated active silicon chip, realized a 50 $\mu{\rm m}$ pitch micro-probing at-speed-active-test for known-good-die (KGD) sorting. Finally, oxide wafer bonding with Cu TSV demonstrated wafer-scale 3D integration, with TSV diameters as small as 1 $\mu{\rm m}$ . The paper concludes with comments on the challenges for future 3D DRAMs.

Ramped programming optimization is investigated in order to limit the risk of gate oxide breakdown (BD) during the programming of a Multi-Time Programmable Memory. Optimization of the programming ramp rate has been proven to be beneficial at both device level and array level. This allows for inline monitoring of programmability and BD-risk reduction as a function of process changes.

For high-volume production of 3D-stacked chips with through-silicon-vias (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology and is promising for interconnect pitches smaller than 5 µ using available tooling. Prior work has presented wafer-scale integration with tungsten TSV for low-power applications. This paper reports the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45 nm Silicon On Insulator-Complementary Metal Oxide Semiconductor (SOI-CMOS) embedded DRAM (EDRAM) having 12 to 13 copper wiring levels per strata and upto 11000 TSVs at 13 µm pitch for power and signal delivery. The wafers are thinned to 13 µm using grind polish and etch. TSVs are defined post bonding and thinning using conventional alignment techniques. Up to four additional metal levels are formed post bonding and TSV definition. A key feature of this process is its compatibility with the existing high performance POWER7™ EDRAM core requiring neither modification of the existing CMOS fabrication process nor re-design since the TSV RC characteristic is similar to typical 100–200 µm length wiring load enabling 3D macro-to-macro signaling without additional buffering Hardware measurements show no significant impact on device drive and off-current. Functional test at wafer level confirms 2.1 GHz 3D stacked EDRAM operation.

Novel device structures with vertical channels gated by TSV's are demonstrated. The unique device structure is realized in a standard TSV process flow, without new material systems or processes. They can be used for both characterizing the TSV process as well as enable new functions. They can be easily integrated into product designs thus enabling field monitoring.

An architecture for enabling self-authenticating chips uses 4 Kb electrically programmable fuses (eFUSE) to store bit strings representing encrypted intrinsic fingerprints obtained by offset-superimposing six out of one thousand 4 Kb domains randomly chosen in 4 Mb embedded DRAM. Authentication is accomplished by regenerating various encrypted intrinsic fingerprints, which are then compared with the bit strings in the eFUSE. Monte Carlo simulations demonstrate that, targeting an average of 32 retention fails per domain, the strings are unique and authentication is statistically guaranteed without bit correction even when unstable bits are introduced. The preliminary results are confirmed in > 50 parts containing 4 Mb memory implemented in 22-nm SOI hardware under the target voltage ±10% conditions. The analytical model predicts > 10 20 years to crack the encryption by brute force, while satisfying > 99.9999% successful authentication for one million parts.

High performance processors and ASICs typically require multiple voltages and multi-domain voltage controls across the die. Conventional approaches distribute the voltage regulation elements between the processor, the package laminate, and the printed circuit board. We propose an alternative approach where the voltage regulator is embodied in a 3D configuration such that the inductor, capacitor and the switches are formed on a separate silicon chip sandwiched between the processor and the laminate. Due to the close proximity of regulator to the processor, this approach can enable granular voltage domains, while minimizing disruptions to the processor layout. We describe a 4-f DC-DC buck converter fabricated on 32nm SOI wafers using TSVs to connect the switches on the front-side of the wafer to the inductors on the grind-side. The process builds on a 32nm SOI CMOS flow, adding deep trench (DT) capacitors and TSV's. Down conversion from a standard I/O voltage under various load conditions was evaluated, and an efficiency of 77% was achieved.

The reliability of NiPtSi/p-poly Si electrical fuses with different programming mechanisms, i.e., electromigration and thermal rupture, was investigated in terms of fuse resistance stability and fuse array functionality for the 65-nm technology node. The resistance of the fuses programmed within the electromigration programming window was found to be very stable; resistance shift was only observed on fuses programmed in the underprogrammed mode, which results in incomplete electromigration. For fuses programmed with the thermal rupture mechanism, both resistance shift and functional sensing fails were observed. Furthermore, a guard band was defined for fuses programmed with an electromigration mechanism to ensure sufficient margins for fuse reliability. However, a guard band cannot be defined for fuses programmed with a rupture mode due to the unpredictable nature of the rupture programming mechanism. The unprogrammed fuse elements were shown to be stable through extensive reliability evaluations.

We explore the use of oxygen vacancies for nonvolatile data storage by trapping electrons in the high-k, gate dielectric layer of NFETs. Programming is performed via channel carrier injection and is erased by tunneling. 64Kb arrays were constructed and reliability is demonstrated.

A new interaction between TSV processes and devices in close proximity, different from mechanical stress, is identified, studied and mitigated. Detailed characterization via Triangular Voltage Sweep (TVS) and SIMS shows the role of mobile ion penetration from BEOL layers. An improved process is presented and confirmed in test structures and DRAM.

This paper presents the industry's smallest Embedded Dynamic Random Access Memory (eDRAM) implemented in IBM's 22nm SOI technology. The bit cell area of 0.026µm2 achieves ∼60% scaling over the previous generation with deep trench (DT) capacitance optimized for performance and retention requirements. We report, for the first time, the asymmetric embedded stressor, cavity implant, through gate implant, and substrate n-band innovations to maintain aggressive cell scaling for the 22nm eDRAM technology.

An 800-MHz embedded DRAM macro employs a memory cell utilizing a device from the 90-nm high-performance technology menu; a 2.2-nm gate oxide 1.5 V IO device. A concurrent refresh mode is designed to improve the memory utilization to over 99% for a 64 /spl mu/s data retention time. A concurrent refresh scheduler utilizes up-count and down-count registers to identify at least one array to be refreshed at every clock cycle, emulating a classical distributed refresh mode. A command multiplier employs low frequency phased clock signals to generate the clock, commands, and addresses at rates up to 4/spl times/ that of the tester frequency. The macro integrates masked redundancy allocation logic during at speed multibank test. The hardware results show a 312-MHz random access frequency and 800-MHz multibank frequency at 1.2 V, respectively.

For high-volume production of 3D-stacked chips with through-silicon-via (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology [1][2][3] and is promising for interconnect pitch

A random intrinsic chip ID method generates a pair of 4Kb binary strings using retention fails in 32nm SOI embedded DRAM. Hardware results show ID overlap distance mean=0.58 and σ=0.76 and demonstrate 100% authentication for 346 chips. The analytical model predicts > 99.999% unique IDs for 106 parts.

Differential thermal expansion mismatch between Cu and Si along with high aspect ratios required for TSV pose unique challenges to the integration and reliability of Cu TSV. A TSV structure that successfully mitigates these concerns has been integrated into CMOS with high K/metal gates. Data from test structures demonstrate no ‘Cu pumping’ or other deleterious effects to neighboring devices or interconnects. Functional 3D prototypes utilizing stacked embedded DRAMs were demonstrated showing no impact from TSV processing.

We present industry's smallest eDRAM cell and the densest embedded memory integrated into the highest performance 32nm High-K Metal Gate (HKMG) SOI based logic technology. The cell is aggressively scaled at 58% (vs. 45nm) and features the key innovation of High-K Metal (HK/M) stack in the Deep Trench (DT) capacitor. This has enabled 25% higher capacitance and 70% lower resistance compared to conventional SiON/Poly stack at matched leakage and reliability. The HKMG access transistor developed in high performance optimized technology features sub 3fA leakage and well-controlled threshold voltage sigma of 40mV. The fully integrated 32Mb product prototypes demonstrate state of the art performance with excellent retention and yield characteristics. The sub 1.5ns latency and 2ns cycle time have been verified with preliminary testing whereas even better performance is expected with further characterization. In addition, the trench capacitors set the industry benchmark for the most efficient decoupling in any 32nm technology.

This paper describes a second-generation one-time programmable read-only memory (OTPROM) that provides these features through a balanced bitline, resistor pull-up, differential sense amp with a programmable reference.

Demonstrating a >10X density increase over traditional VLSI fuse circuits, a compact eFUSE programmable array memory configured as a 4 Kb one-time programmable ROM (OTPROM) is presented using a 6.2 mum2 NiSix silicide electromigration ITIR cell in 65 nm SOI CMOS. A 20 mus programming time at 1.5 V is achieved by asymmetrical scaling of the fuse and a shared differential sensing scheme. Having zero process cost adder, eFUSE is fully compatible with standard VLSI manufacturing.

The reliability of CoSi2/p-poly Si electrical fuse (eFUSE) programmed by electromigration for 90nm technology will be presented. Both programmed and unprogrammed fuse elements were shown to be stable through extensive reliability evaluations. A qualification methodology is demonstrated to define an optimized reliable electrical fuse programming window by combining fuse resistance measurements, physical analysis, and functional sensing data. This methodology addresses the impact on electrical fuse reliability caused by process variation and device degradation (e.g., NBTI) in the sensing circuit and allows an adequate margin to ensure electrical fuse reliability over the chip lifetime.

A high performance embedded DRAM cell has been developed in 90nm technology using a pass transistor with standard 2.2nm gate oxide and trench capacitor. This device offers 25% on-current improvement with 1.5V wordline boosted voltage, and reduces the cell size by 10%. Measured data retention of >200/spl mu/s is ideal for 200+MHz random access cycle embedded DRAM macro with a concurrent refresh mode. The scalability of the cell to 0.11 /spl mu/m/sup 2/ in 65-nm node is also demonstrated.

A 0.18 /spl mu/m high performance/low power technology platform is described which allows 'system on a chip integration' for a broad spectrum of products. Based on a generic digital process additional modules can be added in a modular and cost effective-manner for mixed signal as well as for eDRAM applications offering a maximum of flexibility for product designers. For mixed signal applications a precision metal-insulator-metal capacitor (MIMCAP) was developed. This is for the first time a realization of a metal-insulator-metal capacitor in a copper dual damascene metallization scheme.

Embedded DRAM (eDRAM) has been fabricated successfully with 0.13 /spl mu/m technology for the first time using Cu interconnects and low-/spl kappa/ SiLK/sup TM/ dielectric. Sub-7 ns random access time has been achieved. Extension of the technology to 0.10 /spl mu/m and electrical fuse (eFuse) implementation for flexible redundancy are also described.