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A model for work-function variability (WFV) based on grain orientation differences of the polycrystalline metal gate is proposed, and the impact of the WFV on device and circuit performance is investigated. The model predicts that the WFV will surpass random dopant fluctuation beyond the 22-nm technology node and become the dominant factor to significantly increase static RAM failure probabilities. The prediction is verified through experimental characterization and analysis. [ABSTRACT FROM PUBLISHER]

In this work, we have investigated the influence of Vt extraction procedure on overall Vt variability of sub-10 nm Wfin FinFETs. Using six different Vt extraction techniques, we have experimentally demonstrated that the Vt variability is independent of Vt extraction procedure (unlike reported earlier). Furthermore, through systematic evaluation on commonly used Vt extraction techniques, the physics behind this anomalous behavior is investigated. It is shown that the significant variation in metal gate work-function and gate dielectric charges in advanced CMOS nodes is mainly responsible for this behavior. This claim is further validated for FinFETs with deeply scaled fin-width and effective oxide thickness (EOT). [ABSTRACT FROM AUTHOR]

Total-ionizing-dose (TID) effects are investigated in a highly-scaled gate-all-around (GAA) FET technology using Si nanowire channels with a diameter of 8 nm. n- and p-FETs are irradiated up to 300 Mrad(SiO2) and annealed at room temperature. TID effects are negligible up to 10 Mrad(SiO2). At ultrahigh doses, the TID degradation depends on the irradiation bias condition, with more severe effects observed in longer channel devices. The worst case irradiation condition is when positive bias is applied to the gate. Threshold-voltage shifts are caused by H+-driven generation of interface traps at the oxide/channel interface. In contrast, FETs irradiated under negative gate bias are dominated by transconductance loss and increases of low-frequency noise, suggesting the activation of border traps. Enhanced off-leakage current is observed in n-FETs due to charge trapping in shallow-trench isolation, and in p-FETs due to trap-assisted recombination at STI sidewalls and/or spacer dielectrics at drain/bulk junctions. [ABSTRACT FROM AUTHOR]

In this paper, we have fabricated high-performance Si0.45Ge0.55 implant-free quantum well (IFQW) pFET with embedded SiGe source/drain stressor. This device showed high drive current of 1.28 mA/ \mu m at I_{\mathrm {\scriptstyle OFF}\_{D}} of 160 nA/ \mu $ m with channel length/width of 30 nm/0.16 $\mu $ m ( $V_{{\rm {DD}}} =-1$ V). Conventional ion-implanted extension is replaced with in situ boron-doped epitaxial Si0.75Ge0.25 layer. This enables lower process temperature which can maintain an integrity of Si0.45Ge0.55 film and thus higher hole mobility. In narrower width devices, we observed significant hole mobility boost ( $1.9\times $ improvement from active width of 10 to $0.1~\mu $ m). This is due to the relaxation of unwanted transverse stress in Si0.45Ge0.55 channel applied from Si substrate. IFQW devices show improved short channel control thanks to the epitaxially formed raised extension structure compared with conventional devices which have implanted extension. Achieved device performance is one of the best among all Si1–xGex-based channel pFET up to date. [ABSTRACT FROM AUTHOR]

Negative-bias-stress and total-ionizing-dose (TID) effects in deeply scaled Ge-gate-all-around (GAA) nanowire (NW) devices are characterized for different biasing conditions. Negative-bias-stress-induced degradation in Ge GAA device originates primarily from the interface- and border-trap generation. Devices stressed at high gate voltage show rapid initial degradation and quick saturation dominated by interface-trap generation. Radiation-induced OFF-state leakage current in Ge GAA NWs increases with dose due to enhanced band-to-band tunneling (BTBT) caused by charge trapping in the shallow trench isolation (STI). [ABSTRACT FROM AUTHOR]

Abstract: The Implant-Free Quantum Well Field-Effect Transistor (FET) offers enhanced scalability in a planar architecture through the integration of heterostructures. The Implant-Free architecture fully utilizes the band offsets between different materials, whereby charge carriers are effectively confined to a thin channel layer. This prevents sub-surface source/drain leakage observed in classical bulk Metal-Oxide-Semiconductor FETs at small gate lengths. An investigation of the VT-tuning capabilities of this technology reveals sensitivity to both well doping and bulk voltage. [Copyright &y& Elsevier]

Peak transient currents due to pulsed-laser or heavy-ion irradiation of Ge $p$ MOS FinFETs are nearly independent of gate bias. This is because the prompt photocurrent is due primarily to a transient source–drain shunt. In contrast, long-term diffusion charge collection is strongly gate-bias dependent. This bias dependence results from hole injection from the source in response to the transient increase in electron concentration in the channel. The transients measured at the source terminal change polarity when the strike location moves from the source to the drain, but this effect does not occur for the transients measured at the drain terminal. Charge collection mechanisms are studied using TCAD simulations. [ABSTRACT FROM AUTHOR]

Gate-all-around (GAA) silicon nanowire (NW) CMOS transistors demonstrate outstanding total-ionizing-dose (TID) tolerance due to the ultrascaled gate dielectric thickness, enhanced electrostatic gate control, and suppression of parasitic leakage current paths. nFETs and pFETs show similar TID responses, making the GAA NW technology an excellent candidate for CMOS IC applications in high-radiation environments. The slight degradation of the threshold voltage suggests limited charge buildup in the gate dielectrics. However, low-frequency noise and random telegraph noise measurements show the importance of change in trap configurations in both the near-interfacial SiO2 and HfO2 dielectric layers to the radiation response and reliability of GAA NW devices. These traps are most likely due to oxygen vacancies and/or hydrogen complexes. [ABSTRACT FROM AUTHOR]

The energy distributions of electrons in gate-all-around (GAA) Si MOSFETs are analyzed using full-band 3-D Monte Carlo (MC) simulations. Excellent agreement is obtained with experimental current–voltage characteristics. For these 24-nm gate length devices, the electron distribution features a smeared energy peak with an extended tail. This extension of the tail results primarily from the Coulomb scattering within the channel. A fraction of electrons that enter the drain retains their energy, resulting in an out-of-equilibrium distribution in the drain region. The simulated density and average energy of the hot electrons correlate well with experimentally observed device degradation. We propose that the interaction of high-energy electrons with hydrogen-passivated phosphorus dopant complexes within the drain may provide an additional pathway for interface-trap formation in these devices. [ABSTRACT FROM AUTHOR]

A new methodology is demonstrated to assess the impact of fabrication inherent process variability on 14-nm fin field effect transistor (FinFET) device performance. A model of a FinFET device was built using virtual device fabrication and testing. The model was subsequently calibrated on Design of Experiment corner case data that had been collected on a limited number of processed fab wafers. We then performed 400 virtual experiments comprising seven sources of process variation. Using this virtual fabrication technique, we were able to identify a minimum gate-to-source/drain spacer thickness for a high-temperature post-EPI rapid thermal anneal (RTA) anneal process that avoided device subthreshold slope penalties. The model allowed us to determine the optimal Si recess depth target and process window prior to source/drain epitaxy. We obtained these results by reviewing device performance as a function of statistical process sensitivity and highlighting key process parameters requiring variation control. These experiments would have been impractical to perform in an actual fab, due to the time, cost, and equipment requirements of running 400 fab-based process variation experiments for each process parameter. This methodology can be used to avoid wafer-based testing during early technology development. [ABSTRACT FROM AUTHOR]

Pulsed, laser-induced, single-event current measurements on silicon-on-insulator (SOI) FinFETs at subbandgap wavelength (1260 nm) are affected by the polarization of the laser light used in the experimental testing setup. Such polarization dependence is not observed during pulsed laser, single-event effects testing on large-area silicon diodes, suggesting that polarization dependence arises due to the presence of the nanoscale fin. Plasmonic enhancement is proposed as a likely mechanism for the polarization effects due to the metal/dielectric interfaces in the fin region. The observed polarization dependence has ramifications for collection and interpretation of data acquired by pulsed laser testing. Device orientation of FinFETs and other nanoscale devices during pulsed laser testing should be considered in order to ensure consistent testing conditions and reproducible measurement results across multiple measurement campaigns. [ABSTRACT FROM AUTHOR]

In this article, we explore different device and standard cell architectures for scaling the Germanium fin field-effect transistor (FinFET) and nanosheet (NS) at the sub-5-nm node. It is demonstrated that the Germanium device provides approximately 70% improvement in drive current and $3.4\times $ less device resistance. The main concern for Germanium devices remains the high leakage current due to the gate-induced drain leakage, which limits their usage to high-speed applications. Overall, Germanium devices require fewer boosters than silicon to scale beyond the 5-nm node. Contact resistivity is found to be a critical knob for Germanium and it can be relaxed to 3e $- 9\,\,\Omega $ -cm2 to meet the power and performance targets for the sub-5-nm node. Moving to the NS helps in relaxing this constraint further. [ABSTRACT FROM AUTHOR]

We evaluate the total ionizing dose (TID) responses of InGaAs nMOS FinFETs with different gate lengths irradiated with 10-keV X-rays under different gate biases. The largest degradation after irradiation occurs at $V_{\mathrm {G}} = -1$ V. Radiation-induced trapped positive charge dominates the TID response of InGaAs FinFET transistors, consistent with previous results for InGaAs multifin capacitors. Shorter gate-length devices show larger radiation-induced charge trapping than longer gate-length devices, most likely due to the electrostatic effects of trapped charge in the surrounding SiO2 isolation and SiO2/Si3N4 spacer oxides. The 1/ $f$ noise measurements indicate a high trap density and a nonuniform defect-energy distribution, consistent with a strong variation of effective border-trap density with surface potential. [ABSTRACT FROM AUTHOR]

Low-frequency noise is used to estimate the quality of the gate stack for planar Ge nMOSFETs with different effective work function metals and cap layers. It is shown that replacing TiN by a TiAl-based metal gate will induce a significant decline of the threshold voltage ${V}_{T}$ and noise power spectral density, indicating the introduction of Al will induce an advantageous effect on the trap density in the underlying HfO2. Meanwhile, the application of a LaOx cap tends to reduce ${V}_{T}$ and the trap density in the gate oxide, which could attribute to the La in-diffusion in the gate stack. The 1/f noise analysis shows that the noise could mainly be associated with number fluctuations and correlated mobility fluctuations. [ABSTRACT FROM AUTHOR]

We use capacitance–frequency ( $C$ – $f$ ) measurements to provide lower bound estimates of border-trap densities in multifin MOS capacitors with high-K dielectrics built in Ge and InGaAs fin field effect transistor (FinFET) technologies before and after X-ray irradiation. The $C$ – $f$ method is illustrated for SiO2-based planar MOS capacitors and compared with high-frequency capacitance–voltage measurements. Lower effective border-trap densities are found before and after irradiation for multifin capacitors built in a strained Ge $p$ MOS FinFET technology than for similar devices built using an early-developmental stage InGaAs MOS technology. These results show the utility of $C$ – $f$ measurements in characterizing defect densities in MOS capacitors, particularly when large border-trap densities exist. [ABSTRACT FROM PUBLISHER]

We have characterized the total ionizing dose response of strained Ge p MOS FinFETs built on bulk Si using a fin replacement process. Devices irradiated to 1.0 Mrad(SiO2) show minimal transconductance degradation (less than 5%), very small \text {V}_{th} shifts (less than 40 mV in magnitude) and very little ON/OFF current ratio degradation (<5%), and only modest variation in radiation response with transistor geometry (typically less than normal part-to-part variation). Both before and after irradiation, the performance of these strained Ge p$ MOS FinFETs is far superior to that of past generations of planar Ge $p$ MOS devices. These improved properties result from significant improvements in processing technology, as well as the enhanced gate control provided by the strained Ge FinFET technology. [ABSTRACT FROM PUBLISHER]

Advanced devices are not only driven by minimum device geometry, performance enhancement, and cost issues, but also require a low power consumption. Device scaling for higher performance and lower power consumption necessitates the introduction of advanced process modules, new materials new device architectures and, finally, even the use of alternative device operation principles compared to the standard MOS transistor. Several of these advanced devices will be discussed in view of their scalability and their potential for coping with the ITRS roadmap. Key performance parameters will be investigated. [ABSTRACT FROM AUTHOR]

The high mobility germanium (Ge) channel is considered as a strong candidate for replacing Si in pMOSFETs in the near future. It has been reported that the conventional power-law degradation kinetics of Si devices is inapplicable to Ge. In this paper, further investigation is carried out on defect energy distribution, which clearly shows that this is because the defects in GeO2/Ge and SiON/Si devices have different physical properties. The three main differences are: 1) energy alternating defects (EAD) exist in Ge devices but are insignificant in Si; 2) the distribution of as-grown hole traps has a tail in the Ge bandgap but not in Si, which plays an important role in the degradation kinetics and device lifetime prediction; and 3) EAD generation in Ge devices requires the injected charge carriers to overcome a second energy barrier, but not in Si. Taking the above differences into account, the power-law kinetics of EAD generation can be successfully restored by following a new procedure, which can assist in the Ge process/device optimization. [ABSTRACT FROM PUBLISHER]

An experimental low-frequency noise (LFN) assessment of long channel Ge pFinFET devices fabricated in different shallow trench isolation (STI) processes is presented, taking into consideration devices with fin widths from 100 nm (planar-like) down to 20 nm. In addition, the correlation among LFN parameters, hole mobility and threshold voltage, is also evaluated. The carrier number fluctuation ( $\Delta N$ ) model is confirmed as dominant mechanism for all studied Ge pFinFETs and there is no correlation with the used STI process. From the LFN, it is evidenced that the Coulomb scattering mobility mechanism plays an important role for STI-first process, resulting in a mobility degradation. [ABSTRACT FROM PUBLISHER]

In this paper, a new scheme called diffusion and gate replacement (D&GR) metal-inserted polysilicon integration is demonstrated. The CMOS flow allows controlling the gate height asymmetry between the nMOS and the pMOS by driving the work function shifter directly into the high- $k$ , and then by removing the dopant source (dummy doped metal gate) and depositing a fresh TiN metal gate. Although the integration flow is compatible with a standard 45-/28-nm technological node, it has been specifically designed to be compatible with dynamic random access memory peripheral applications or other emerging memories (embedded applications). A material down-selection is done (TiN/Mg/TiN gate-stack for nMOS and Al2O3 capping layer for pMOS), and it is demonstrated that a process window exists and guarantees enough work function lowering without compromising the electrical parameters (electrical oxide thickness, mobility, subthreshold slope, and gate leakage). Regarding the CMOS integration, it is shown that an nMOS-first integration is preferable, and that there is no contamination issue of the pMOS work function shifter (in this case, Al2O3) on the nMOS side. Finally, CMOS device performance is on par with the non-D&GR baseline, validating the integration flow. [ABSTRACT FROM AUTHOR]

The total ionizing dose response of Ge channel pFETs with raised Si0.55Ge0.45 source/drain is investigated under different radiation bias conditions. Threshold-voltage shifts and transconductance degradation are noticeable only for negative-bias (on state) irradiation, and are mainly due to negative bias-temperature instability (NBTI). Nonmonotonic leakage changes during irradiation are observed, which are attributed to the competition of radiation-induced field transistor leakage and S/D junction leakage. [ABSTRACT FROM PUBLISHER]

Single-event transients in SiGe MOS devices with ultrathin quantum well channels have been shown in previous work to exhibit opposite polarities for source and drain strikes. This work reports polarity reversal in similar devices with thick Ge channels due to the favorability of prompt hole collection by either the source or drain region, depending on the strike location. A slower charge-collection mechanism is also present due to the n-well/p-substrate structure, which allows ion-generated carriers from the substrate to flood the body of the device. [ABSTRACT FROM PUBLISHER]

The gate-stack quality of planar MOSFETs fabricated in Ge-on-Si substrates and passivated by a GeOx interfacial layer is evaluated by low-frequency noise analysis. It is shown that for both n- and p-channel transistors predominantly 1/ f^\gamma noise ( $\gamma \sim 1$ ) has been observed, which originates from number and correlated mobility fluctuations. The oxide trap density and mobility scattering coefficient derived from the input-referred voltage noise power spectral density are demonstrated to be significantly higher for nMOSFETs than for pMOSFETs with the same gate-stack, which explains the low electron mobility. [ABSTRACT FROM PUBLISHER]

Heavy-ion and two-photon-absorption (TPA) experiments have been performed on ultra-thin implant-free quantum well SiGe channel pMOSFETs. Both the single-event-transient pulse magnitude and polarity can depend strongly on the location of the strike along the device channel. The polarity inversion occurs primarily because very limited transient charge collection occurs below the quantum well, as confirmed by two-dimensional TCAD simulation. [ABSTRACT FROM PUBLISHER]

Ge is a candidate for replacing Si, especially for pMOSFETs, because of its high hole mobility. For Si-pMOSFETs, negative-bias temperature instabilities (NBTI) limit their lifetime. There is little information available for the NBTI of Ge-pMOSFETs with Ge/GeO2/Al2O3 stack. The objective of this paper is to provide this information and compare the NBTI of Ge- and Si-pMOSFETs. New findings include: 1) the time exponent varies with stress biases/field when measured by either the conventional slow dc or pulse I-V technique, making the conventional Vg -accelerated method for predicting the lifetime of Si-pMOSFETs inapplicable to Ge-pMOSFETs used in this paper; 2) the NBTI is dominated by positive charges (PCs) in dielectric, rather than generated interface states; 3) the PC in Ge/GeO2/Al2O3 can be fully annealed at 150 ^\circC ; and 4) the defect losses reported for Si sample were not observed. For the first time, we report that the PCs in oxides on Ge and Si behave differently, and to explain the difference, an energy-switching model is proposed for hole traps in Ge-MOSEFTs: their energy levels have a spread below the edge of valence band, i.e., Ev , when neutral, lift well above Ev after charging, and return below Ev following neutralization. [ABSTRACT FROM PUBLISHER]

Irradiated Ge pMOSFETs have been characterized via charge pumping (ICP) and 1/f noise. The noise increases much more with irradiation than does ICP for devices with eight Si monolayers at the interface, while devices with five Si monolayers and lower halo implantation dose exhibit comparable increases in noise and ICP with irradiation. These results suggest that border traps in the HfO2 affect the noise more than interface traps, and that devices with eight Si monolayers have a higher border-trap density than devices with five Si monolayers. Noise measurements as a function of gate voltage show that the border trap density increases significantly toward the Ge valence band edge, while three-level charge pumping reveals an interface trap density that increases slightly toward midgap. [ABSTRACT FROM AUTHOR]

The irradiation and annealing responses of Ge pMOSFETs have been investigated under transmission gate bias. Both the radiation-induced charge trapping and the low frequency (1/ f ) noise increase with total ionizing dose and decrease with annealing time. The smallest increases in noise after irradiation are observed for Ge pMOSFETs with the lowest halo implantation doses. The smallest increases in oxide and interface trap charge densities are obtained for devices with eight monolayers of Si at the interface, as compared to devices with five Si monolayers. [ABSTRACT FROM AUTHOR]

The irradiation and annealing responses of Ge pMOSFETs are investigated as a function of device processing. Transmission gate bias is found to be the worst-case irradiation bias condition. Junction leakage increases with total dose, which leads to a decrease in the I on /I off ratio. The I on /I off ratio recovers with room temperature annealing. Both band-to-band tunneling and trap-assisted tunneling contribute to the observed leakage. Device leakage before and after irradiation is found to be sensitive to halo implant dose and the number of Si monolayers at the Ge/insulator interface. Interface trap densities and body leakage also increase with dose and decrease with annealing. [ABSTRACT FROM AUTHOR]

The total-dose response of Ge p-MOSFETs and p+-n junction diodes is reported for devices fabricated with several process variations. Radiation-induced reduction of the on-off current ratio increases with halo-doping density. Increasing the number of Si monolayers at the substrate/dielectric interface reduces total-dose sensitivity for p-MOSFETs. Reduced mobility degradation is observed after irradiation for devices with a higher number of Si monolayers. The radiation-induced increase in junction leakage is related to the increasing perimeter component of the leakage current. MOSFETs with a higher number of Si monolayers at the dielectric/substrate interface also have reduced perimeter leakage current. Diode leakage current increases with increasing halo-doping density. [ABSTRACT FROM AUTHOR]

The origin of performance difference between gate-first (GF) and replacement metal gate (RMG) fin field effect transistors (FinFETs) is investigated. Although RMG technology has the advantage of low thermal-budget, a 1.5 times lower effective hole mobility is shown for the high-k last (HKL) FinFET. Based on low frequency noise analysis, it is shown that the carrier transport is due to the carrier number fluctuation with correlated mobility fluctuation from the interface states. For HKL FinFETs, about 10 times higher trap density is observed compared to GF and high-k first FinFETs, which is generated during the dummy gate oxide removal process. [ABSTRACT FROM AUTHOR]