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In this paper, we present the fabrication method of asymmetric independent dual-gate FinFETs with different gate stack using sidewall spacer patterning and two-step chemical-mechanical polishing (CMP) processes. The fin width is controlled as a result of sidewall spacer patterning. The two-step CMP processes are conducted to separate two gates and to make different gate stacks for each gate, respectively. The fabricated devices can be used for multiple applications by utilizing independent two gates. First of all, the independent two gates offer the flexible threshold voltage modulation properties by applying the second gate (G2) bias with little subthreshold swing degradation. Second, the device can be utilized as a charge trap flash memory cell by trapping electrons in the charge storage layer. These results provide a possible way to fabricate asymmetric independent dual-gate FinFETs having potential as a multi-functional single device.

In this work, a novel silicon (Si) based floating body synaptic transistor (SFST) is studied to mimic the transition from short-term memory to long-term one in the biological system. The structure of the proposed SFST is based on an n-type metal-oxide-semiconductor field-effect transistor (MOSFET) with floating body and charge storage layer which provide the functions of short- and long-term memories, respectively. It has very similar characteristics with those of the biological memory system in the sense that the transition between short- and long-term memories is performed by the repetitive learning. Spike timing-dependent plasticity (STDP) characteristics are closely investigated for the SFST device. It has been found from the simulation results that the connectivity between pre- and post-synaptic neurons has strong dependence on the relative spike timing among electrical signals. In addition, the neuromorphic system having direct connection between the SFST devices and neuron circuits are designed.

In order to overcome small current drivability of a tunneling field-effect transistor (TFET), a TFET using Schottky barrier (SBTFET) is proposed. The proposed device has a metal source region unlike the conventional TFET. In addition, dopant segregation technology between the source and channel region is applied to reduce tunneling resistance. For TFET fabrication, spacer technique is adopted to enable self-aligned process because the SBTFET consists of source and drain with different types. Also the control device which has a doped source region is made to compare the electrical characteristics with those of the SBTFET. From the measured results, the SBTFET shows better on/off switching property than the control device. The observed drive current is larger than those of the previously reported TFET. Also, short-channel effects (SCEs) are investigated through the comparison of electrical characteristics between the long- and shortchannel SBTFET .

Control of threshold voltage (V T ) by ground-plane (GP) technique for planar tunnel fieldeffect transistor (TFET) is studied for the first time using TCAD simulation method. Although GP technique appears to be similarly useful for the TFET as for the metal-oxide-semiconductor field-effect transistor (MOSFET), some unique behaviors such as the small controllability under weak ground doping and dependence on the dopant polarity are also observed. For V T -modulation larger than 100 mV, heavy ground doping over 1×1020 cm -3 or back biasing scheme is preferred in case of TFETs. Polarity dependence is explained with a mechanism similar to the punch-through of MOSFETs. In spite of some minor differences, this result shows that both MOSFETs and TFETs can share common V T -control scheme when these devices are co-integrated.

In order to form practical arrays of Si nanowires narrower than 22nm using electron beam lithography (EBL) with hydrogen silsesquioxane (HSQ) resist and reactive ion etching (RIE) process with inductively-coupled plasma, a new type of lithography/etching interaction is studied. The inter-pattern electrostatic repulsion appears to determine the patterning limit to be 28nm while causing the RIE dummy patterns to collapse. Approaches to reduce the electrostatic force on the RIE dummies are tried from design and process perspectives. Designing additional dummy patterns next to the RIE dummies and fixing pattern-to-pattern distance to be 70nm are tried. Another efficient approach is to use thinner HSQ resist to reduce the repulsion among patterns. Here we confirm that the nanowire patterns narrower than 20nm can be formed by using diluted HSQ solutions.

Detailed study on how the plasma process during the sidewall spacer formation suppresses the formation of silicide is done. In non-patterned wafer test, it is found that both fluorocarbon reactive ion etch (RIE) and TEOS plasma-enhanced deposition processes modify the Si surface so that the silicide reaction is chemically inhibited or suppressed. In order to investigate the cause of the chemical modification , we analyze the elements on the silicon surface through Auger Electron Spectroscopy (AES). From the AES result, it is found that the carbon induces chemical modification which blocks the reaction between silicon and nickel. Thus, protecting the surface from the carbon-containing plasma process prior to nickel deposition appears critical in successful silicide formation.

In order to implement complementary logic function with L-shaped tunneling field-effect transistors (TFETs), current drivability and subthreshold swing (SS) need to be improved more. For this purpose, highk material such as hafnium dioxide (HfO2) has been used as gate dielectric rather than silicon dioxide (SiO2). The effects of device parameters on performance have been investigated and the design of L-shaped TFETs has been optimized. Finally, the performance of L-shaped TFET inverters have been compared with that of conventional TFET ones. key words: L-shaped TFETs, subthreshold swing, steep slope, complementary logic function

In this work, design considerations for highperformance silicon photodetector are thoroughly investi- gated. Besides the critical dimensions of device, guidelines for process architecture are suggested. Abiding by those criteria for improving both direct-current (DC) and alternating-current (AC) perfor- mances, a high-speed low-operation power silicon photodetector based on p-i-n structure for optical interconnect has been designed by device simulation. An f-3dB of 80 ㎓ at an operating voltage of 1 V was obtained.

Tunneling Field Effect Transistors (TFETs) are considered as a candidate for low power applications. However, most of TFETs have been researched on only for long channels due to the misalignment problem that occurs during the source/drain doping process in device fabrication. Thus, a new method is proposed for the fabrication of TFETs in nanoscale regions. This proposed fabrication process does not need an additional mask to define the source/drain regions, and makes it possible to form a self-aligned source/drain doping process. In addition, through TCAD simulation, the electrical characteristics of a TFET with dopant engineering and a rounded gate edge shape for a higher on/off current ratio were investigated. As a result, the TFET showed the properties of a larger on-current, a lower average subthreshold swing (58.5 mV/dec), and a 30-fold smaller leakage current compared to the conventional TFET The TFET with dopant engineering and a rounded gate edge shape can also be fabricated simply through the proposed fabrication process.

In order to extend the conventional low power Si CMOS technology beyond the 20-nm node without SOI substrates, we propose a novel co-integration scheme to build horizontal- and vertical-channel MOSFETs together and verify the idea using TCAD simulations. From the fabrication viewpoint, it is highlighted that this scheme provides additional vertical devices with good scalability by adding a few steps to the conventional CMOS process flow for fin formation. In addition, the benefits of the co-integrated vertical devices are investigated using a TCAD device simulation. From this study, it is confirmed that the vertical device shows improved off-current control and a larger drive current when the body dimension is less than 20 nm, due to the electric field coupling effect at the double-gated channel. Finally, the benefits from the circuit design viewpoint, such as the larger midpoint gain and beta and lower power consumption, are confirmed by the mixed-mode circuit simulation study.

In this work, a tunneling field-effect transistor (TFET) based on heterojunctions of compound and Group IV semiconductors is introduced and simulated. TFETs based on either silicon or compound semiconductors have been intensively researched due to their merits of robustness against short channel effects (SCEs) and excellent subthreshold swing (SS) characteristics. However, silicon TFETs have the drawback of low on-current and compound ones are difficult to integrate with silicon CMOS circuits. In order to combine the high tunneling efficiency of narrow bandgap material TFETs and the high mobility of III-V TFETs, a Type-I heterojunction tunneling field- effect transistor (I-HTFET) adopting Ge-AlxGa1-xAs- Ge system has been optimized by simulation in terms of aluminum (Al) composition. To maximize device performance, we considered a nanowire structure, and it was shown that high performance (HP) logic technology can be achieved by the proposed device. The optimum Al composition turned out to be around 20% (x=0.2). Index Terms—Tunneling field-effect transistor (TFET), Type-I heterojunction, narrow bandgap material, high mobility, simulation, nanowire, high performance (HP) logic technology

As the feature size of the conventional 1T-1C DRAM scales down, difficulties of the fabrication process are increasing and it is becoming harder to keep a constant capacitance value for data storage. Capacitor-less 1T DRAM is a promising candidate for the substitution of the conventional 1T-1C DRAM, but its poor retention time is one of the critical issues in its commercialization. In the selection of a bias condition for 1T DRAM, however, it is impossible to choose a gate bias condition that is suitable for both the "1" and "0" hold state data. In this paper, a split gate structure and hold bias scheme are proposed for the simultaneous improvement of the "1" and "0" data retention characteristics. It was confirmed through numerical simulation that this structure has a more than 3 sec retention time. A vertical gate-all-around split-gate structure and its fabrication method are also suggested to achieve high density, low cost, a higher sensing margin, and a longer retention time.

In this work, the organic residue and oxide on silicon wafer were treated with UV-excited oxygen and trifluoronitrogen gases as a pre-treatment for silicon homoepitaxy. A typical positive photo resist, AZ 1512, was coated as a model organic residue. UV-O 2 cleaning (UVOC) and UV-NF 3 /H 2 treatment removed the organic residue and native oxide layer, respectively, for silicon epitaxial growth. A study of removal rate showed that the processing temperature is a more critical process parameter than pressure. Besides, hydrogen dilution improves the surface roughness of UV-NF 3 -treated surface as shown in the atomic force microscope images.

In order to decrease the threshold voltage while maintaining the OFF current low, reduction of the subthreshold swing is essential in field effect transistors(FETs). To reduce the subthreshold swing below 60 mV/decade, inter-band tunneling can be used for injection of carriers and the device that utilizes such a mechanism is tunneling field effect transistor (TFET). Silicon(Si) TFETs, which are favored due to their compatibility with currently dominant complementary metal-oxide-semiconductor(CMOS) technology, suffer from low ON current because of the relatively large bandgap of Si. The ON current of Si TFETs can be increased by field and area enhancement in a cylindrical nanowire channel. Numerical analysis has confirmed that the cylindrical channel structure shows significantly higher tunneling rate and wider tunneling area than the double gate structure. Si TFETs with a hemicylindrical nanowire channel are fabricated and characterized, and the effectiveness of nanowire channel approach is demonstrated.

In this work, electrical characteristics of L-shaped tunneling field-effect transistors (TFETs) have been studied and optimized by a commercial device simulator: Synopsys Sentaurus. Unlike our previous study performed by using Silvaco Atlas, there exists a kink phenomenon in a transfer curve which degrades the subthreshold swing (SS) and on-current (lon) of TFETs. According to simulation results, the kink results from abrupt source doping. Rounding the source junction edge with gradual doping profile is helpful to alleviate it. Based on those results, a novel fabrication flow has been proposed to suppress the kink effect induced by source corners. It is predicted that the performance of L-shaped TFETs is improved in terms of SS and Ion under the optimized process condition. Furthremore, the effect of high-k gate dielectric and narrow band gap material on device performance has been examined. Using 2-nm-thick HfO2 for gate dielectric and Si0.7Ge0.3 for intrinsic tunneling region, gate controllability to the channel and tunneling probability have been enhanced. As a result, its threshold voltage (Vth), SS and Ion have been improved by 0.13 V, 16 mV/dec, and 3.62 microA/microm, respectively.

In order to improve the internal quantum efficiency of GaN-based LEDs, a LED structure featuring a p-type trench in the multi-quantum well (MQW) is proposed. This structure has effects on spreading holes into the MQW and reducing the quantum-confined stark effect (QCSE). In addition, two simple fabrication methods using electron-beam (e-beam) lithography or selective wet etching for manufacturing the p-type structure are also proposed. From the measurement results of the manufactured GaN-based LEDs, it is confirmed that the proposed structure using e-beam lithography or selective wet etching shows improved light output power compared to the conventional structure because of more uniform hole distribution. It is also confirmed that the proposed structure formed by e-beam lithography has a significant effect on strain relaxation and reduction in the QCSE from the electro-luminescence measurement.

The threshold voltage (VT) control of gate-all-around (GAA) MOSFETs as an extreme case of multi-gate MOSFETs is studied. After breaking down the components constituting VT into several terms, their relative sizes are compared using TCAD technique and analytical calculation of quantum mechanical problem. As a result, the channel diameter is found to be an important knob to control VT of a GAA MOSFET, which influences on short-channel effect, quantum confinement effect and other effects.

Most of research groups have studied on Tunneling Field-Effect Transistors (TFETs) with assumption that there are no gate/source overlap and abrupt source/channel junction. In this work, we study the electrical characteristics of double-gated thin-body TFET with gate/source overlap and no abrupt source/channel junction. From transfer characteristics, hump phenomenon occurring with increasing gate bias is observed. This phenomenon affects the threshold voltage (VTH), which worsens device matching and also makes it difficult to design logic circuits. The reason why tunneling current is suddenly increased is due to tunneling components in a direction normal to the channel. Theses hump phenomena are not seen in the previous TFET study using unidirectional nonlocal band-to-band tunneling model.

L-shaped tunneling field-effect transistors (TFETs) feature high current drivability and abrupt on-off transition. For further improvement of L-shaped TFETs, tunneling regions become n-type doped in this study. The doping concentration of the tunneling regions is optimized. The proposed novel L-shaped TFETs show higher on-current (I on ) and lower subthreshold swing (SS) than conventional L-shaped TFETs.

In this paper, hump effects of L-shaped tunneling field-effect transistors (TFETs) have been investigated. It turns out that the hump effects are originated from the two different turn-on voltages (V turn-on 's). By using device simulation, the source junction design has been optimized in order to suppress the hump effects.

In this work, process conditions and geometric parameters for high-speed p-i-n silicon photodetector are optimized by device simulation. Efforts were made to build up criteria for device fabrication based on silicon epitaxy. For an optimized silicon photodetector, a bandwidth as wide as 80 GHz was obtained at 1 V. Furthermore, a way of increasing wavelength discriminations by introducing silicon-germanium quantum wells for multiple-wavelength signal processing is exploited.

A silicon nanowire field effect transistor (SiNW FET) was fabricated through the fabrication method compatible with that of MOSFET including back-end process without lift-off process. However, when it is working in an aqueous solution, the SiNW device as well as other transducer devices has various inherent instability problems such as hysteresis characteristics. We observed the hysteresis in DI water (DW) and confirmed that it is caused by mobile ion effect in DW with various experimental results.

Supply voltage (V DD ) scaling has been an important issue as the CMOS scaling down. Scaling of devices induces large leakage current due to Short Channel Effects (SCEs). Also, Subthrehold Swing (SS) value of CMOS devices is theoretically limited to 60 mV/dec. Various structures have been proposed to overcome power dissipation problems, one of which is the TFETs [1–2]. However, TFET has two critical drawbacks such as low on-current level and ambipolar behaviors. To overcome these disadvantages, TFET using hetero-gate dielectric materials has been lately reported [3]. Although this TFET has low SS and high on-current level, it is difficult to control dielectric alignment between high-k material and SiO 2 in the process. Thus, we introduce an improved TFET in terms of fabrication and performance.

As complementary metal oxide semiconductor (CMOS) has been scaled down and supply voltage has been reduced, it becomes important to reduce subthreshold swing (SS) in order to obtain high on/off current ratio. To decrease SS below 60 mV/dec, tunneling field effect transistor (TFET) has been reported and studied recently[1–3]. However, as TFET uses band-to-band tunneling as its current source, it is difficult to obtain high on-current. In order to solve this problem of the conventional TFET and maintain high on-current while lowering SS, novel device using p-n junction gate is proposed in this paper.

While a tunneling field-effect transistor (TFET) is an attractive candidate for sub-20 nm ultra-low-power device, high I ON /I OFF and on-current are rarely reported with the deep-submicron structures. In this study, we propose a practical novel TFET structure with vertical channel and Ge junction, which shows high current ratio, low subthreshold swing and relatively high current even when the minimum device dimension is smaller than 20 nm. To find the optimum design, the off-state injection of a short-channel TFET and optimization of the source-side junction are studied by simulation.

In this study, the influence of sidewall thickness on the threshold voltage and on-current of L-shaped Impact-ionization metal-oxide-semiconductor transistor (I-MOS) is investigated. For the sidewall thickness in the range of 10 nm to 20 nm, the devices of thicker sidewall show lower on-current and higher threshold voltage. This is because the electron concentration between the channel and the most active ionization region rapidly decreases as the sidewall gets thicker. As a result, a precise control of sidewall formation is needed in fabricating L-shaped I-MOS devices. Also, obtaining the required on-current and reliability at the same time, as well as suppressing device variability due to sidewall thickness variation, is expected to be challenging.

The fin type device has been considered as one of the most promising candidates in CMOS scaling because of excellent current drivability and good short-channel effect immunity. It is well known that the fin width should be small for proper short-channel behavior [1]. However, the narrow fin can induce a large parasitic series resistance. Therefore, it is prefered to rebuild the source/drain region. In addition, the large gate-induced drain leakage (GIDL) caused by the field concentration effect at the corner of the fin is the problem of the FinFET structure. Recently, the silicon epitaxial re-growth is used to extend the source/drain fin outside of the gate region [2]. However, there are some issues such as the cost, throughput and process complexity.

Large scale integration and reliability of triple gate FETs (TG-FETs) are investigated. The SRAM chip composed of TG-FETs demonstrated 20Mbits of working cells, and 45/spl deg/ rotated TG-FET is found to be superior from reliability perspective. Future TG-FET design is proposed, utilizing technologies including alternating phase shift mask lithography, local-interconnects and metal gate/undoped channel.

Relationship between mechanical stress engineering and flicker noise are clarified for the first time using a 50nm level CMOS technology. It is found that enhanced mechanical stress degrades flicker noise characteristics. Trap states and dipoles generated by the stress are considered to be the cause of degradation. The transistor performance enhancement with flicker noise reduction by nitrogen profile optimization in gate dielectric is demonstrated as a countermeasure.

In order to overcome the small current drivability of a tunneling field-effect transistor (TFET), we have introduced a TFET with the SiGe body and elevated Si drain region. The proposed TFET features large on-current and lower subthreshold swing (SS) compared with the Si TFET. Also, by using elevated Si drain region, it is expected that ambipolar current can be suppressed. Through the technology computer aided design (TCAD) simulation, the characteristics of the proposed TFET have been investigated to confirm its superiority in performance. The proposed TFET structure enables self-aligned doping process and has a strong immunity to short-channel effects compared with the conventional TFET. In addition, we have confirmed that both n- and p-channel characteristics can be simultaneously improved by using the proposed TFET.

A new design of tunneling field-effect transistor (TFET) focusing on the compatibility to the current Si complementary-metal–oxide–semiconductor (CMOS) technology is proposed. In addition to use of the structural components of the state-of-the-art CMOS technologies, such as Σ-shaped embedded SiGe and the replacement gate techniques, two-step sidewall image transfer gate-patterning and channel recess process are adopted to form highly-scaled nanoscale TFET. Process integration scheme and the expected device characteristics are examined on the basis of technology computer-aided design (TCAD) simulation on 14-nm-gate model devices. Tunability of transfer characteristics with doping around tip region, control of short-channel effect with channel recess, and improvement of current drivaility with SiGe composition are studied. Design of the source region is found to be critical in controlling the current drivability of the device and output characteristics.

In this work, novel L-shaped tunneling field-effect transistors (TFETs) have been proposed. The proposed L-shaped TFETs feature higher on-current (I on) and lower subthreshold swing (SS) than conventional TFETs. It is because L-shaped TFETs have large cross-sectional area of band-to-band tunneling junction which is perpendicular to the channel direction and their tunneling barrier width (W t) is defined by the length of an intrinsic silicon region. As the devices are based on the Si without any other material, it can be fabricated with well-established Si process technology. In addition, it can moderate some issues come from scaling down and enlarging tunneling area due to its mesa structure. Simulation results have confirmed the superiority of L-shaped TFETs over conventional TFETs. Additionally, the effect of some device parameters on device performance has been investigated for the clear verification of its operation mechanism and the optimization.

A structure of a tunneling field-effect transistor (TFET) featuring an extremely thin body, a double-gated vertical channel, and a source design to maximize the drive current is proposed and optimized on the basis of technology computer-aided design (TCAD) simulation. The field-coupling effect at the double-gated thin-body channel and an engineered tunneling barrier are implemented to maximize the operation current of the device. Weak current drivability under a small drain bias and the directionality of current flow are the expected challenges in building logic circuits with TFETs. A co-integration scheme to build vertical-channel TFETs and metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed as the solution. A new low-power design using the co-integration scheme is suggested.

A comprehensive study is done regarding stabilities under simultaneous stress of light and dc-bias in amorphous hafnium-indium-zinc-oxide thin film transistors. The positive threshold voltage (Vth) shift is observed after negative gate bias and light stress, and it is completely different from widely accepted phenomenon which explains that negative-bias stress results in Vth shift in the left direction by bias-induced hole-trapping. Gate current measurement is performed to explain the unusual positive Vth shift under simultaneous application of light and negative gate bias. As a result, it is clearly found that the positive Vth shift is derived from electron injection from gate electrode to gate insulator.

In this paper, we propose a novel fin and recess-channel metal oxide semiconductor field effect transistor (MOSFET) for sub-50 nm dynamic random access memory (DRAM) cell application. Also, it is compared with the recess-channel-array transistor (RCAT). In the proposed device, a silicon fin region is added to the recessed channel MOSFET. Thanks to the additional current path through the silicon fin with the wide source/drain width, the FiReFET shows excellent current drivability. To reduce gate-induced drain leakage (GIDL) current, we adopt an underlapped device structure. As a result, it is found that the optimized underlap structure helps to prevent the OFF state leakage current induced by the increase of the gate work function.