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Grain boundaries between 60° rotated and twinned crystals constitute the dominant type of extended line defects in two-dimensional transition metal dichalcogenides (2D MX2) when grown on a single c...

The integration of graphene, and more broadly two-dimensional materials, into devices and hybrid materials often requires the deposition of thin films on their usually inert surface. As a result, strategies for the introduction of surface reactive sites have been developed but currently pose a dilemma between robustness and preservation of the graphene properties. A method is reported here for covalently modifying graphitic surfaces, introducing functional groups that act as reactive sites for the growth of high quality dielectric layers. Aryl diazonium species containing tri-methoxy groups are covalently bonded (grafted) to highly oriented pyrolytic graphite (HOPG) and graphene, acting as seeding species for atomic layer deposition (ALD) of Al2O3, a high-κ dielectric material. A smooth and uniform dielectric film growth is confirmed by scanning electron microscopy (SEM), atomic force microscopy (AFM) and electrical measurements. Raman spectroscopy showed that the aryl groups gradually detach from the graphitic surface during the Al2O3 ALD process at 150 °C, with the surface reverting back to the original sp2-hybridized state and without damaging the dielectric layer. Thus, the grafted aryl groups can act as a sacrificial seeding layer after healing the defects of the graphitic surface with annealing treatment.

Electron channeling contrast imaging (ECCI) is a powerful technique to characterize the structural defects present in a sample and to obtain relevant statistics about their density. Using ECCI, such defects can only be properly visualized, if the information depth is larger than the depth at which defects reside. Furthermore, a systematic correlation of the features observed by ECCI with the defect nature, confirmed by a complementary technique, is required for defect analysis. Therefore, we present in this paper a site-specific ECCI-scanning transmission electron microscopy (STEM) inspection. Its value is illustrated by the application to a partially relaxed epitaxial Si

The ovonic threshold switch (OTS) selector based on the voltage snapback of amorphous chalcogenides has received tremendous attention as it provides several desirable characteristics such as bidirectional switching, a controllable threshold voltage, high drive currents, and low leakage currents. GeSe is a well-known OTS selector that fulfills all the requirements imposed by future high-density storage class memories. Here, we report on pulsed chemical vapor deposition (CVD) of amorphous GeSe by using GeCl2 center dot C4H8O2 as a Ge source and two different Se sources namely bis-trimethylsilylselenide ((CH3)(3)Si)(2)Se (TMS)(2)Se and bis-triethylsilylselenide ((C2H5)(3)Si)(2)Se (TES)(2)Se. We utilized total reflection X-ray fluorescence (TXRF) to study the kinetics of precursor adsorption on the Si substrate. GeCl2 center dot C4H8O2 precursor adsorption on a 300 mm Si substrate showed under-dosing due to limited precursor supply. On the other hand, the Se precursor adsorption is limited by low reaction efficiency as we learned from a better within-wafer uniformity. Se precursors need Cl sites (from Ge precursor) for precursor ligand exchange reactions. Adsorption of (TMS)(2)Se is found to be much faster than (TES)(2)Se on a precoated GeClx layer. Atomic layer deposition (ALD) tests with GeCl2 center dot C4H8O2 and (TMS)(2)Se revealed that the growth per cycle (GPC) decreases with the introduction of purge steps in the ALD cycle, whereas a higher GPC is obtained in pulsed-CVD mode without purges. Based on this basic understanding of the process, we developed a pulsed CVD growth recipe (GPC = 0.3 angstrom per cycle) of GeSe using GeCl2 center dot C4H8O2 and (TMS)(2)Se at a reactor temperature of 70 degrees C. The 20 nm GeSe layer is amorphous and stoichiometric with traces of chlorine and carbon impurities. The film has a roughness of similar to 0.3 nm and it starts to crystallize at a temperature of similar to 370 degrees C. GeSe grown on 3D test structures showed excellent film conformality.

Double gated WS 2 transistors with gate length down to 18 nm are fabricated in a 300mm Si CMOS fab. By using large statistical data sets and mapping uniformity on full 300mm wafer, we built an integration vehicle where impact of each process step can be understood and developed accordingly to enhance device performance. In-depth analysis of V T variability reveals multiple possible sources at different length scales, with the most prominent one being the channel material. The work presented here paves the way towards industrial adoption of 2D materials.

We show that downscaling the top-contact length to 13nm induces no penalty on the electrical characteristics for CVD MoS 2 FETs. We demonstrate this for devices with different gate-oxides and operating in both channel and contact-limited regimes, thus confirming carrier injection at the edge of the contact metal. Consequently, we have scaled the device footprint achieving an I on =250μA/μm and excellent SS min =80mV/dec for 50nm SiO 2 and 4nm HfO 2 gate oxides, respectively.

Semiconductor heterostructures are at the heart of most nanoelectronic and photonic devices such as advanced transistors, lasers, light emitting diodes, optical modulators and photo-detectors. However, the performance and reliability of the respective devices are often limited by the presence of crystalline defects which arise from plastic relaxation of misfit strain present in these heterogeneous systems. To date, characterizing the nature and distribution of such defects in 3D nanoscale devices precisely and non-destructively remains a critical metrology challenge. In this paper we demonstrate that electron channeling contrast imaging (ECCI) is capable of analyzing individual dislocations and stacking faults in confined 3D nanostructures, thereby fulfilling the aforementioned requirements. For this purpose we imaged the intensity of electrons backscattered from the sample under test under controlled diffraction conditions using a scanning electron microscope (SEM). In contrast to transmission electron microscopy (TEM) analysis, no electron transparent specimens need to be prepared. This enables a significant reduction of the detection limit (i.e. lowest defect density that can be assessed) as our approach facilitates the analysis of large sampling volumes, thereby providing excellent statistics. We applied the methodology to SiGe nanostructures grown by selective area epitaxy to study in detail how the nature and distribution of crystalline defects are affected by the dimensions of the structure. By comparing our observations with the results obtained using X-ray diffraction, TEM and chemical defect etching, we could verify the validity of the method. Our findings firmly establish that ECCI must be considered the method of choice for analyzing the crystalline quality of 3D semiconductor heterostructures with excellent precision even at low defect densities. As such, the technique aids in better understanding of strain relaxation and defect formation mechanisms at the nanoscale and, moreover, facilitates the development and fabrication of next generation nanoelectronic and photonic devices.

© 2018 The Royal Society of Chemistry. SnS2 and SnS are two-dimensional (2D) semiconductors with distinct properties, as they exhibit a different type of conduction. They are of interest for applications in nanoelectronics, optoelectronics and sensors. To enable these applications, the deposition of SnS2 and SnS layers with a well-controlled phase, crystallinity and thickness at the nanometer level is required on large-area substrates. Chemical vapor deposition (CVD) of SnS2 and SnS using SnCl4 and H2S has previously been reported to give micrometer level polycrystalline SnS2 and SnS layers, which were insulating due to the uncontrolled grain orientations. In this work, we investigate the formation mechanism and phase control of nanometer level 2D SnS2 and SnS by SnCl4/H2S CVD. Nanometer level and phase-pure 2D hexagonal SnS2 and orthorhombic SnS layers are obtained. The SnSx phase depends on both the temperature and the H2S/SnCl4 concentration ratio. Compared to the formation of the SnS2 phase, the formation of the SnS phase is favorable at higher temperature and, surprisingly, at a higher H2S/SnCl4 concentration ratio. This is explained by the catalytic decomposition of H2S by SnS2 with the formation of H2, where the as such generated H2 reduces SnS2 to SnS at temperatures equal to or higher than 350 °C. By adjusting the conditions of the CVD process, the product can be tuned to either n-type SnS2 or p-type SnS, as demonstrated by back-gated field effect transistors. ispartof: Journal of Materials Chemistry C vol:6 issue:23 pages:6172-6178 status: Published online

Electron channeling contrast imaging (ECCI) is a powerful technique to characterize the structural defects present in a sample and to obtain relevant statistics about their density. Using ECCI, such defects can only be properly visualized, if the information depth is larger than the depth at which defects reside. Furthermore, a systematic correlation of the features observed by ECCI with the defect nature, confirmed by a complementary technique, is required for defect analysis. Therefore, we present in this paper a site-specific ECCI-scanning transmission electron microscopy (STEM) inspection. Its value is illustrated by the application to a partially relaxed epitaxial Si0.7Ge0.3 on a Si substrate. All experiments including the acquisition of ECCI micrographs, the carbon marking and STEM specimen preparation by focused ion beam, and the in-situ-subsequent-STEM-in-scanning electron microscopy (SEM) characterization were executed in one SEM/FIB-based system, thus significantly improving the analysis efficiency. The ECCI information depth in Si0.7Ge0.3 has been determined through measuring stacking fault widths using different beam energies. ECCI is further utilized to localize the defects for STEM sample preparation and in-situ-subsequent-STEM-in-SEM investigation. This method provides a correlative 2.5D defect analysis from both the surface and cross-section. Using these techniques, the nature of different line-featured defects in epilayers can be classified, as illustrated by our study on Si0.7Ge0.3, which helps to better understand the formation of those detrimental defects.

Summary The crystal and defect structure of SnS crystals grown using chemical vapour deposition for application in electronic devices are investigated. The structural analysis shows the presence of two distinct crystal morphologies, that is thin flakes with lateral sizes up to 50 μm and nanometer scale thickness, and much thicker but smaller crystallites. Both show similar Raman response associated with SnS. The structural analysis with transmission electron microscopy shows that the flakes are single crystals of α-SnS with [010] normal to the substrate. Parallel with the surface of the flakes, lamellae with varying thickness of a new SnS phase are observed. High-resolution transmission electron microscopy (TEM), scanning transmission electron microscopy (STEM), first-principles simulations (DFT) and nanobeam diffraction (NBD) techniques are employed to characterise this phase in detail. DFT results suggest that the phase is a strain stabilised β’ one grown epitaxially on the α-SnS crystals. TEM analysis shows that the crystallites are also α-SnS with generally the [010] direction orthogonal to the substrate. Contrary to the flakes the crystallites consist of two to four grains which are tilted up to 15° relative to the substrate. The various grain boundary structures and twin relations are discussed. Under high-dose electron irradiation, the SnS structure is reduced and β-Sn formed. It is shown that this damage only occurs for SnS in direct contact with SiO2.

A high-Ge-content Si1–yGey/compositionally graded Si1–xGex-stacked structure grown on Si(001) is now considered to be an important platform for the realization of advanced nanometer-scale complementary metal oxide semiconductor devices with high-mobility channel materials, such as III–V materials and Ge, and monolithically integrated photonic modules. The performance of such advanced devices is critically influenced by crystalline inhomogeneity in the stacked structure; therefore, precise characterization of the crystallinity is important. In particular, the development of a characterization method not only for in-plane crystallinity but also for in-depth crystallinity is strongly required. This is because the crystalline quality of the constant composition Si1–yGey is sensitively dependent on that of the compositionally graded Si1–xGex layers underneath. Here, we have demonstrated in-depth tomographic mapping of a high-Ge-content Si1–yGey/compositionally graded Si1–xGex-stacked structure using position-d...

High-quality InxGa1−xAs layers with indium composition between 0.46 and 0.50 have been grown in a 300 mm industrial MOVPE reactor using ≤1 μm thin InxGa1−xAs buffers on 2″ GaAs substrates. Aggressive grading of 3.7 to 3.8% misfit/μm, fast growth rates in the range of 0.2–2.2 nm/s and low growth temperatures of 530 °C and 450 °C were used. AFM reveals a significant difference in root mean square surface roughness of 3.6 nm (530 °C) versus 15.5 nm (450 °C). Cross-section TEM analysis shows that for both temperatures threading dislocations are effectively confined to the buffer region. However, at 450 °C phase separation is observed in the upper part of the structure. From plan-view TEM threading dislocation densities as low as 1×105 cm−2 and 4.5×105 cm−2 are estimated for growth at 530 °C and 450 °C, respectively.

The epitaxial growth of Si layers on Si substrates in the presence of O atoms is generally considered a challenge, as O atoms degrade the epitaxial quality by generating defects. Here, we investigate the growth mechanisms for Si epitaxy on O atomic layers (ALs) with different O-contents and structures. O ALs are deposited by ozone (O3) or oxygen (O2) exposure on H-terminated Si at 50 °C and 300 °C respectively. Epitaxial Si is deposited by chemical vapor deposition using silane (SiH4) at 500 °C. After O3 exposure, the O atoms are uniformly distributed in Si-Si dimer/back bonds. This O layer still allows epitaxial seeding of Si. The epitaxial quality is enhanced by lowering the surface distortions due to O atoms and by decreasing the arrival rate of SiH4 reactants, allowing more time for surface diffusion. After O2 exposure, the O atoms are present in the form of SiOx clusters. Regions of hydrogen-terminated Si remain present between the SiOx clusters. The epitaxial seeding of Si in these structures is realized on H-Si regions, and an epitaxial layer grows by a lateral overgrowth mechanism. A breakdown in the epitaxial ordering occurs at a critical Si thickness, presumably by accumulation of surface roughness.

To keep Moore's law alive, 2D materials are considered as a replacement for Si in advanced nodes due to their atomic thickness, which offers superior performance at nm dimensions. In addition, 2D materials are natural candidates for monolithic integration which opens the door for density scaling along the 3rd dimension at reasonable cost. This paper highlights the obstacles and paths to a scaled 2D CMOS solution. The baseline requirements to challenge the advanced Si nodes are defined both with a physical compact model and TCAD analysis, which allows us to identify the most promising 2D material and device design. For different key challenges, possible integrated solutions are benchmarked and discussed. Finally we report on the learning from our first lab to fab vehicle designed to bridge the lab and IMEC's 300mm pilot line.

© 2018 American Chemical Society. When two-dimensional (2D) group-VI transition metal dichalcogenides such as tungsten disulfide (WS 2 ) are grown by atomic layer deposition (ALD) for atomic growth control at low deposition temperatures (≤450 °C), they often suffer from a nanocrystalline grain structure limiting the carrier mobility. The crystallinity and monolayer thickness control during ALD of 2D materials is determined by the nucleation mechanism, which is currently not well understood. Here, we propose a qualitative model for the WS 2 nucleation behavior on dielectric surfaces during plasma-enhanced (PE-) ALD using tungsten hexafluoride (WF 6 ), dihydrogen (H 2 ) plasma and dihydrogen sulfide (H 2 S) based on analyses of the morphology of the WS 2 crystals. The WS 2 crystal grain size increases from ∼20 to 200 nm by lowering the nucleation density. This is achieved by lowering the precursor adsorption rate on the starting surface using an inherently less reactive starting surface, by decreasing the H 2 plasma reactivity, and by enhancing the mobility of the adsorbed species at higher deposition temperature. Since silicon dioxide (SiO 2 ) is less reactive than aluminum oxide (Al 2 O 3 ), and diffusion and crystal ripening is enhanced at higher deposition temperature, WS 2 nucleates in an anisotropic island-like growth mode with preferential lateral growth from the WS 2 crystal edges. This work emphasizes that increasing the crystal grain size while controlling the basal plane orientation is possible during ALD at low deposition temperatures, based on insight in the nucleation behavior, which is key to advance the field of ALD of 2D materials. Moreover, this work demonstrates the conformal deposition on three-dimensional (3D) structures, with WS 2 retaining the basal plane orientation along topographic structures. ispartof: CHEMISTRY OF MATERIALS vol:30 issue:21 pages:7648-7663 status: published

As semiconductor devices continue to shrink, novel materials (e.g. (Si)Ge, III/V) are being tested and incorporated to boost device performance. Such materials are difficult to grow on Si wafers without forming crystalline defects due to lattice mismatch. Such defects can decrease or compromise device performance. For this reason, non-destructive, high throughput and reliable analytical techniques are required. In this paper Electron Channeling Contrast Imaging (ECCI), large area mapping and defect detection using deep learning are combined in an analytical workflow for the characterization of the defectivity of “beyond Silicon” materials. Such a workflow addresses the requirements for large areas 10-4 cm2 with defect density down to 104 cm-2.

The two-dimensional (2D) semiconducting molybdenum and tungsten disulfide (MoS2 and WS2) hold promise as ultra-scaled metal-oxide-semiconductor (MOS) channel material for low power and/or high-performance logic applications. Manufacturable approaches that develop highly crystalline MX2 layers, tailor the layer number down to the atomic level and remain compatible with temperature sensitive structures, are essential to unlock the desired material functionality. However, fundamental understanding is lacking on how to design chemical deposition processes for 2D MX2, such as chemical vapor deposition (CVD). Therefore, our current research efforts focus on how to control the crystallinity, structure and morphology of WS2 crystals in the first, single layer through understanding the growth behaviour during a metal-organic (MO-)CVD process. WS2 is grown from tungsten hexacarbonyl (W(CO)6) and dihydrogen sulfide (H2S) precursors on 300 mm Si substrates covered with amorphous SiO2 and on single crystalline sapphire templates. A commercial 300 mm state-of-the-art Si and SiGe epitaxial reactor has been modified to deposit MX2 materials. In order to construct a qualitative model for relevant growth processes during WS2 MOCVD, the reaction kinetics are studied. Insight in the growth mechanisms is captured from the evolution in morphology of the WS2 crystals at different stages during the MOCVD process. Based on a statistical and morphological analysis of crystals in the first, single WS2 layer, two figures of merit describing the MOCVD process are extracted: the areal density of WS2 crystals and median lateral growth rate (lateral GR in nm2/(min∙cm2)). The WS2 MOCVD process is a profoundly thermally activated deposition process, with both nucleation rate and lateral GR dependent on deposition temperature. From an Arrhenius graph of WS2 inter-nucleus distance, the activation energy of surface diffusion is 10 kcal/mole. The areal density of WS2 crystals decreases over two orders of magnitude with deposition temperature, from 2x1010 /cm2 at 550 °C to 1x108 /cm2 at 1000 °C. However, it does not vary significantly with W(CO)6 partial pressure nor ratio between chalcogen and metal precursor partial pressure. Hence, the type and areal density of active surface sites of the starting surface determines the areal density of WS2 crystals, rather than the dose of metal precursor supplied to the starting surface. This opens opportunities to further control the areal density of WS2 crystals, for example through surface pretreatment. In contrast, the lateral growth rate of WS2 crystals in first, single layer increases most profoundly with deposition temperature and metal precursor partial pressure, with an activation energy of lateral growth approaching 31 kcal/mole. From the experimentally determined activation energies, the MOCVD process is likely governed by diffusion of reagents and reaction products (e.g., CO) across the boundary layer, and the dissociative physi-sorption of W(CO)6 precursor on starting surface. Based on these insights, the MOCVD process has been optimized and WS2 crystals with a median crystal size of 500 nm have been grown on amorphous SiO2. That learning is also applied to single crystalline sapphire substrates for their epitaxial seeding capability, considered to date the preferred approach to obtain state-of-the-art intrinsic material quality. In contrast to WS2 layers on SiO2, the WS2 crystals on the pretreated sapphire substrate develop a preferential in-plane crystalline orientation. The combination of the epitaxial seeding capability with the control over the areal density of WS2 crystals down to 1.7 x109 /cm2, implies that neighboring crystals can merge without forming a defective grain boundary yielding in principle micrometer-size crystals in the first, single layer.

In this study, an annular multi-segment backscattered electron (BSE) detector is used in back scatter geometry to investigate the influence of the angular distribution of BSE on the crystalline defect contrast in electron channeling contrast imaging (ECCI). The study is carried out on GaAs and Ge layers epitaxially grown on top of silicon (Si) substrates, respectively. The influence of the BSE detection angle and landing energy are studied to identify the optimal ECCI conditions. It is demonstrated that the angular selection of BSEs exhibits strong effects on defect contrast formation with variation of beam energies. In our study, maximum defect contrast can be obtained at BSE detection angles 53–65° for the investigated energies 5, 10 and 20 keV. In addition, it is found that higher beam energy is favorable to reveal defects with stronger contrast whereas lower energy ( ≤ 5 keV) is favorable for revealing crystalline defects as well as with topographic features on the surface. Our study provides optimal ECCI conditions, and therefore enables a precise and fast detection of threading dislocations in lowly defective materials and nanoscale 3D semiconductor structures where signal to noise ratio is especially important. A comparison of ECCI with BSE and secondary electron imaging further demonstrates the strength of ECCI in term of simultaneous detection of defects and morphology features such as terraces with atomic step heights.

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The deposition of ultra-thin tungsten films and their related 2D chalcogen compounds on large area dielectric substrates by gas phase reactions is challenging. The lack of nucleation sites complicates the adsorption of W-related precursors and subsequent sulfurization usually requires high temperatures. We propose here a technique in which a thin solid amorphous silicon film is used as reductant for the gas phase precursor WF6 leading to the conversion to metallic W. The selectivity of the W conversion towards the underlying dielectric surfaces is demonstrated. The role of the Si surface preparation, the conversion temperature, and Si thickness on the formation process is investigated. Further, the in situ conversion of the metallic tungsten into thin stoichiometric WS2 is achieved by a cyclic approach based on WF6 and H2S pulses at the moderate temperature of 450 °C, which is much lower than usual oxide sulfurization processes. ispartof: Journal of Materials Chemistry C vol:6 issue:15 pages:4122-4130 status: published

The structure, crystallinity and properties of as-deposited two-dimensional (2D) transition metal dichalcogenides are determined by nucleation mechanisms in the deposition process. 2D materials grown by atomic layer deposition (ALD) in absence of a template, are polycrystalline or amorphous. Little is known about their nucleation mechanisms. Therefore, we investigate the nucleation behavior of WS2 during plasma enhanced ALD from WF6, H2 plasma and H2S at 300 °C on amorphous ALD Al2O3 starting surface and on monocrystalline, bulk sapphire. Preferential interaction of the precursors with the Al2O3 starting surface promotes fast closure of the WS2 layer. The WS2 layers are fully continuous at WS2 content corresponding to only 1.2 WS2 monolayers. On amorphous Al2O3, (0002) textured and polycrystalline WS2 layers form with grain size of 5 nm to 20 nm due to high nucleation density (~1014 nuclei/cm2). The WS2 growth mode changes from 2D (layer-by-layer) growth on the initial Al2O3 surface to three-dimensional (Volmer-Weber) growth after WS2 layer closure. Further growth proceeds from both WS2 basal planes in register with the underlying WS2 grain, and from or over grain boundaries of the underlying WS2 layer with different in-plane orientation. In contrast, on monocrystalline sapphire, WS2 crystal grains can locally align along a preferred in-plane orientation. Epitaxial seeding occurs locally albeit a large portion of crystals remain randomly oriented, presumably due to the low deposition temperature. The WS2 sheet resistance is 168 MΩµm suggesting that charge transport in the WS2 layers is limited by grain boundaries. ispartof: Journal of Vacuum Science & Technology A, Vacuum, Surfaces and Films vol:36 issue:1 pages:1-11 status: published

aalso at E.E. Dept. KU Leuven, Kasteelpark Arenberg 10, B-3001 Leuven, Belgium Since the 45 nm CMOS node, high-k gate dielectrics and strain engineering go hand in hand to further boost the transistor performance. An example of a so-called global strain platform relies on a thin strained-silicon (sSi) layer on top of a strain-relaxed Si1-xGex buffer (SRB) (Fig. 1). In addition, replacing thermally grown SiO2 by a deposited dielectric opens the door for the implementation of so-called high-mobility channel materials (Ge – pMOS; InxGa1-xAs – nMOS;...), which can be grown hetero-epitaxially on a silicon substrate. Due to the lattice mismatch of most of these materials with silicon, strain relaxation will occur above a certain critical thickness, leading to the introduction of both misfit and threading dislocations (TDs). It is well-known that dislocations introduce a one-dimensional band of states in the band-gap and hence are electrically active [1],[2]. The aim of the present review is to address the impact of such extended defects on the electrical performance of simple devices (p-n junctions, MOSFETs,...) for various high-mobility materials. A first example which will be discussed is the impact of TDs on the current-voltage (I-V) characteristics of p-n junctions fabricated in sSi and relaxed-Ge-on-Si substrates. As can be derived from Fig. 1, the depletion region mainly extends in the SiGe SRB, so that the electrical activity of the dislocations in this layer will be probed. It is clear from Fig. 2 that the reverse current IR of the diodes more or less proportionally increases with the density of TDs [3]. The same applies for the recombination and generation lifetime. Similar studies have been carried out for p-n junctions fabricated in a Si0.2Ge0.8 SRB and in relaxed Ge-on-Si epi layers. Summarizing all these results in Fig. 3, one can observe that the area leakage current density increases proportionally with the density of TDs and exponentially with the Ge content [4]. The latter can be explained by considering the impact on the band gap, yielding an exponential increase of the intrinsic carrier density. Comparing with Fig. 3b, it is clear that there exists a trade-off between leakage current density and epi layer thickness: thinner relaxed Ge layers on silicon will have a higher equilibrium TD density [5] and, hence, leakage current. However, considering a typical SRAM cell design, it can be concluded that for typical TDD values of 107-108 cm-2, the contribution to the off-state leakage is negligible compared with the contribution of the perimeter. A second example investigates the impact of anti-phase boundaries (APBs) on the reverse current of p-n junctions fabricated in GaAs (Fig. 4a) will be discussed. As can be derived from Fig. 4b, there is a modest increase of IRbetween on-axis junctions with a high APB density and off-axis diodes. Overall, it has been concluded that APBs are not so efficient leakage generators in GaAs. Finally, the impact of TDs on other device parameters, like the mobility or the threshold voltage of a MOSFET will be discussed. References [1] W. Schröter and H. Cerva, Solid State Phenomen., 85-86, p. 67 (2002). [2] E. Simoen et al., J. Electrochem. Soc., 158, p. R27 (2011). [3] G. Eneman et al., Appl. Phys. Lett., 87, p. 192112 (2005). [4] E. Simoen et al., J. Electrochem. Soc., 157, p. R1 (2010). [5] G. Wang et al., Appl. Phys. Lett., 94, p. 102115-1 (2009). Figure 1

In this work, we discuss the characteristics of particular island-type features with an amorphous core that are developed during the low temperature epitaxial growth of Ge and GeSn layers by means of chemical vapor deposition with Ge2H6. Although further investigations are needed to unambiguously identify the origin of these features, we suggest that they are originated by the formation of clusters of H and/or contaminants atoms during growth. These would initially cause the formation of pits with crystalline rough facets over them, resulting in ring-shaped islands. Then, when an excess surface energy is overcome, an amorphous phase would nucleate inside the pits and fill them. Reducing the pressure and/or increasing the growth temperature can be effective ways to prevent the formation of these features, likely due to a reduction of the surface passivation from H and/or contaminant atoms.

The ongoing study of {111} planar defects (PDs) in III–V nanowires (NWs) entails a fast and quantitative characterization method beyond transmission electron microscopy (TEM). We report here a simple and reliable method to calculate the PD frequency in InAs NWs using a lab X-ray diffractometer. The fact that the PD distribution is location independent and irrelevant to the NWs diameter in catalyst-free InAs NWs epitaxy makes PD frequency global calculation possible. We demonstrated that the PDs follow a geometric distribution in NWs. As a consequence, applying a 1D disordered layers diffraction model, we relate the diffraction peak angle directly to the PD frequency. The calculated PD frequency values are in good agreement with that extracted from high resolution TEM analysis. As an example, we applied this method to study the influence of growth temperature on PD frequencies in the frame of a 2D nucleation model.

Epitaxial Si-O superlattices consist of alternating periods of crystalline Si layers and atomic layers of oxygen (O) with interesting electronic and optical properties. To understand the fundamentals of Si epitaxy on O atomic layers, we investigate the O surface species that can allow epitaxial Si chemical vapor deposition using silane. The surface reaction of ozone on H-terminated Si(100) is used for the O deposition. The oxygen content is controlled precisely at and near the atomic layer level and has a critical impact on the subsequent Si deposition. There exists only a small window of O-contents, i.e. 0.7–0.9 atomic layers, for which the epitaxial deposition of Si can be realized. At these low O-contents, the O atoms are incorporated in the Si-Si dimers or back bonds (-OSiH), with the surface Si atoms mainly in the 1+ oxidation state, as indicated by infrared spectroscopy. This surface enables epitaxial seeding of Si. For O-contents higher than one atomic layer, the additional O atoms are incorporated in the Si-Si back bonds as well as in the Si-H bonds, where hydroxyl groups (-Si-OH) are created. In this case, the Si deposition thereon becomes completely amorphous.

We demonstrate the impact of reducing agents for Chemical Vapor Deposition (CVD) and Atomic Layer Deposition (ALD) of WS2 from WF6 and H2S precursors. Nanocrystalline WS2 layers with a two-dimensional structure can be obtained at low deposition temperatures (300-450 °C) without using a template or anneal.

For the first time, WS2-based transistors have been successfully integrated in a 300 mm pilot line using production tools. The 2D material was deposited using either area selective chemical vapor deposition (CVD) or atomic layer deposition (ALD). No material transfer was required. The major integration challenges are the limited adhesion and the fragility of the few-monolayer 2D material. These issues are avoided by using a sacrificial Al 2 O 3 capping layer and by encapsulating the edges of the 2D material during wet processing. The WS2 channel is contacted with Ti/TiN side contacts and an industry-standard back end of line (BEOL) flow. This novel low-temperature flow is promising for integration of back-gated 2D transistors in the BEOL.

Ge has been considered as a promising candidate for the active region in optical interconnect applications such as lasers and photodetectors, since its band gap corresponds to a wavelength with less loss in SiO2 waveguides. However, to increase the efficiency of these applications, a direct band gap material is required. Incorporation of Sn into Ge has been considered to obtain a direct band gap material [1,2]. According to theoretical calculations [3], the critical Sn content to achieve the direct transition depends on the strain. When the GeSn layer is fully relaxed, around 11% of Sn is required. On the other hand, when the layer experiences compressive strain, the critical Sn content increases. One option to obtain highly strain-relaxed GeSn with high Sn content is to increase the thickness of the GeSn layer. In addition, the active region of the optical devices has to be thick to obtain a high efficiency. However, it is well known that Sn segregation to the surface easily occurs [4], which results in Sn precipitation/agglomeration on the surface when a thick layer is grown. The Sn agglomeration is the result of the collision among Sn atoms on the surface. Therefore, we focused on the freezing of Sn atoms during GeSn growth. GeSn layers were grown with Ge2H6 and SnCl4 precursors on Ge(001) substrates at 320°C by atmospheric CVD in an Epsilon like equipment from ASM. The target thickness of the GeSn layers is 200 nm. N2 and H2 with different flows ranging from 10 to 40 slm were used as carrier gases to study the impact of the partial pressure of the precursors on Sn agglomeration. It is expected that using low carrier gas flows enhances the Sn freezing due to the higher Ge2H6 and SnCl4 partial pressures. In addition, it is expected that switching the carrier gas from N2 to H2suppresses the Sn migration on the surface due to the resulting surface H-termination. We found opposite tendencies for the surface Sn agglomeration as a function of the H2 and N2 carrier gas flow. A lower N2 suppresses the surface Sn agglomeration. As we expected, a high partial pressure of the precursors enhances the freezing of Sn atoms into the subsurface. On the other hand, when H2 is used as a carrier gas, a higher H2 flow suppresses the surface Sn agglomeration. The growth temperature (320°C) is close to the temperature at which adsorbed H starts to desorb thermally from the Ge surface (340°C) [5, 6]. However, a high H2 partial pressure may suppress the desorption of surface H which is provided by the deposition by Ge2H6. The Sn segregation should be suppressed by the surfactant effect of surface H [6]. The different behavior of these two carrier gases will be discussed in detail. [1] D. W. Jenkins and J. D. Dow, Phys. Rev. B, 36, 7994 (1987). [2] M. R. Bauer, et al., Solid State Commun. 127, 355 (2003). [3] Y. Shimura, et al., J. Appl. Phys. submitted. [4] E. Kasper, et al., Thin Solid Films, 520, 3195 (2012). [5] L. Surnev and M. Tikhov, Surf. Sci. 138, 40 (1984). [6] A. Sakai and T. Tatsumi, Appl. Phys. Lett. 64, 52 (1994).

Band engineered Si/O superlattices are promising channel materials for ultimately scaled complementary metal oxide semiconductor devices. Theoretical calculations have indicated that insertion of O monolayers into Si lattice creates anisotropy in the Si band structure with an enhanced carrier mobility in the channel direction. However, the experimental demonstration of such superlattices is not straightforward, as it requires processes for the deposition of a monolayer of O on Si, and to continue the Si epitaxy thereon. In this work, we investigate processes for the fabrication of Si/O superlattices using the chemical vapor deposition technique. Ozone is used for the O deposition with control of the deposited O content at the monolayer level. The SiH 4 based Si deposition is performed at low temperatures (500 °C–550 °C) in order to obtain a confined O monolayer in the Si superlattice. Si deposited on O layer of 1.2 O monolayers is completely amorphous. This indicates that this O layer is extremely uniform as it prevents any epitaxial ordering with the substrate. Reducing the O content to 0.9 O monolayers in combination with a slower Si deposition favors epitaxial ordering of Si on O/Si. Finally a defect free Si epitaxy is demonstrated on the O monolayer. Such ordering of epitaxial Si on the O layer provides a promising outlook for the growth of superlattices.

We present a method for area selective deposition of 2D WS

The concept of atomically controlled processing for group IV semiconductors is based on atomic-order surface reaction control. This approach is especially important for the epitaxial deposition of very thin (nm) layers. Here, the existences of Ge oxide in the CVD reactor resulting from former Ge deposition and hydrogen termination of the wafer surface is impacting the epitaxial growth essentially. Therefore the evaporation of Ge oxide is suppressed by Si coating the reactor before wafer loading and/or Si capping after Ge growth and/or very low temperature SiH4 treatment after wafer loading. By the use of Si0.5Ge0.5 buffer layer, hydrogen termination of the surface is reduced. As a result, nm-order thick Ge epitaxial growth with very short incubation period and the suppression of surface roughness generation is realized.

Optical transitions in atomically thin MoS2 samples made by sulfidation of a metallic molybdenum layer have been studied by photoreflectance (PR) and photoacoustic (PA) spectroscopy. The obtained spectra are compared with PR and PA spectra of bulk MoS2. It is shown that the absorption edge observed in the PA spectrum shifts to blue when moving from the bulk MoS2 to the atomically thin MoS2 layers, whereas the direct optical transitions at the K point of the Brillouin zone (A and B transitions), which are observed in the PR spectrum, do not shift spectrally in a significant manner. On the other hand, the AH transition, which is related to the direct optical transition at the H point of the Brillouin zone and is typical of bulk MoS2, is not observed for atomically thin MoS2 layers. Moreover, a strong and broad PR resonance related to the band nesting (C transition) is identified in the PR spectra of studied samples. In this case, C and CH transitions are observed for bulk MoS2, while only a C transition is observed for atomically thin MoS2.

Monolayer-thin WS2 with (0002) texture grows by chemical vapor deposition (CVD) from gas-phase precursors WF6 and H2S at a deposition temperature of 450 °C on 300 mm Si wafers covered with an amorphous Al2O3 starting surface. We investigate the growth and nucleation mechanism during the CVD process by analyzing the morphology of the WS2 crystals. The CVD process consists of two distinct growth regimes. During (i) the initial growth regime, a fast and self-limiting reaction of the CVD precursors with the Al2O3 starting surface forms predominantly monolayer-thin WS2 crystals and AlF3 crystals that completely cover the starting surface. During (ii) the steady-state growth regime, a much slower, anisotropic reaction on the bottom, first WS2 layer proceeds with the next WS2 layer growing preferentially in the lateral dimensions. We propose that the precursor adsorption reaction rate strongly diminishes when the precursors have no more access to the Al2O3 surface as soon as the WS2 layer completely covers the Al2O3 surface and that the WS2 crystal basal planes and AlF3 crystals have a low reactivity for WF6 adsorption at 450 °C. Nonetheless, a second layer of WS2 starts to form before the first WS2 layer completely covers the starting surface, albeit the surface coverage of the second layer is low (

We have investigated the three-dimensional configuration of lattice distortions, including lattice plane tilt and twist, in a high-Ge-content constant-composition Silsubg0.3l/subgGelsubg0.7l/subg (CC-SG)/compositionally graded SiGe strain-relaxed buffer (graded SRB)/Si(001) stacked structure. Position-dependent ω-2θ- mapping (or three-dimensional reciprocal space mapping) by synchrotron-based nanobeam X-ray diffraction revealed the in-plane distributions of both local tilt and twist within an area of 10×10 μm on the sample surface. Depth-resolved crystal information was extracted analytically on the basis of structural features in the graded SRB layer. As a result, a series of tomographic maps that show the three-dimensional distributions of tilt and twist around the CC-SG/graded SRB interface were obtained. Tomographic analysis indicates that the orientation of lattice planes in the graded SRB abruptly changes at a specific depth and at a specific interval. The misfit dislocation distribution observed using transmission electron microscopy is not homogeneous but concentrated at a specific depth, which accounts for the abrupt changes of lattice plane tilt and twist. Our tomographic results clearly verify the dislocation morphology in the SiGe stacked structure, which demonstrates that this analysis method can be a powerful tool for quantitative and non-destructive elucidation of a three-dimensional lattice structure with high spatial resolution.

Si cap passivation on Ge shows low border trap response.The Si cap passivation is also suitable for Ge nMOS applications.Low Dit at Ec can be achieved by tuning the amount of Si at the interface.A dry O3 process can be used to control the amount of Si that is oxidized. One route to passivate the Ge/high-? interface is by depositing an epitaxial Si layer on the Ge surface. Subsequently, the Si layer is partially oxidized and a high-? layer is deposited on top. This passivation scheme has proven its efficiency over the last decade for pMOS applications. However, in this paper we demonstrate that this route can also be used for nMOS applications depending on the amount of Si left after the oxidation process. Moreover, the amount of border traps extracted from low frequency capacitance-voltage measurements is low, in contrast to what has been reported on GeO2 passivation. GeO2 passivation results in very low Dit levels at the conduction band edge. Therefore, GeO2 has been put forward as a good candidate for nMOS but it suffers from border traps in the oxide. Si cap passivation can solve both problems: Dit at the interface as well as the border traps in the oxide.

Since the last decade there has been renewed interest in Ge-based technologies for deep submicron CMOS technologies. Whereas good performance data has been reported for p-channel MOSFETs this was not the case for the n-channel counterpart. This manuscript first reviews some key technological aspects for Ge processing, before outlining the status and trends for p-and n-channel Ge MOSFETs in relation to the ITRS specifications. Special attention will be given to GeSn technologies.

The surface chemistry and the interface formation during the initial stages of the atomic layer deposition (ALD) of Al2O3 from trimethylaluminum (TMA) and H2O on InP(100) were studied by synchrotron radiation photoemission spectroscopy and scanning tunneling microscopy. The effect of the ex situ surface cleaning by either H2SO4 or (NH4)2S was examined. It is shown that the native oxide on the InP surface consisted mainly of indium hydrogen phosphates with a P enrichment at the interface with InP. After a (NH4)2S treatment, S was present on the surface as a sulfide in both surface and subsurface sites. Exposure to TMA led to the formation of a thin AlPO4 layer, irrespective of the surface cleaning. The surface Fermi level of p-type InP was found to be pinned close to midgap after H2SO4 cleaning and moved only slightly further toward the conduction band edge upon TMA exposure, indicating that the AlPO4/InP interface was rather defective. (NH4)2S passivation led to a Fermi level position of p-type InP close ...

We used synchrotron radiation photoemission spectroscopy (SR-PES) to investigate the surface of GaAs and other III-V semiconductors after tri-methyl-aluminum (TMA) pulses performed at 250{degree sign}C. We observed the removal of native oxide and the growth of Al-oxide upon measuring the As3d, Ga3d, Al2p and VB spectra. After seven TMA pulses we performed one water pulse. As3d and Ga3d peaks showed almost no lineshape change, but a decrease of intensity due to the water adsorption. The valence band shows a change in the secondary electron cut-off and the decrease of work function. We conclude that water mostly adsorbs molecularly and induces the work function decrease. The molecular absorption of water indicates that the seven TMA pulses produce a passivated surface only partially terminated with OH groups.

Stress implementation in Ge channel is mandatory in order to outperform strained Si hole mobilities in advanced p-MOSFET transistors [1]. The classical buffer layer used to compressively strain Ge is a thick SiGe Strain Relaxed Buffer (SRB). Different groups (LETI [2], intel [3], imec [4], MIT [5]) already reported excellent hole mobility values in strained Ge (s-Ge) channels grown on SiGe SRB. Moreover, the Ge/SiGe valence band offset allows a carrier confinement in the thin Ge Quantum Well (QW) and then reduces OFF current drastically. Only “blanket” approaches are however reported in the literature which does not allow any s-Ge pFET co-integration with either Si or IIIV nFET. In this paper, s-Ge channels on SiGe buffer are selectively grown by Reduced Pressure Chemical Vapor Deposition (RPCVD) in Shallow Trench Isolations (STI) in order to allow such a co-integration. Both planar (wide active trenches) and FinFET (narrow trenches) structures are considered. For planar devices, we considered 600nm wide and 300nm deep active trenches in STI. With such a small depth-width ratio, defects are not expected to be trapped by the oxide sidewalls, as described by Amberwave for narrower trenches [6]. Si STI wafers were chemically cleaned, loaded in the EPI reactor (ASM Epsilon 3200), baked at 850C, and 300nm Si was recessed by HCl vapor etch down to the bottom of the trench. Two approaches were considered for the SiGe growth. First, we stopped Si0.5Ge0.5 growth just below the top of the STI trenches in order to keep the room for continuing the in-situ growth of a thin Ge channel. Many threading dislocations were observed (up to the top of the buffer) in such a thin SiGe layer (Figure 1-top part). Moreover, facets are present whatever the growth conditions used. In a second approach, we overgrew on purpose 1μm thick Si0.5Ge0.5 layers. The overgrown SiGe received a post growth anneal at 850C and a Chemical Mechanical Polishing (CMP) afterwards. Due to such a thick SiGe layer and a post-growth anneal, the relaxation defects can move easily to the SiGe/Si and SiGe/STI interfaces reducing drastically the defects density in the SiGe buffer itself (Figure 1-bottom part). We demonstrated previously on Ge that the epilayer thickness itself is the key parameter in order to reduce strongly the Threading Dislocation Density [7]. Moreover, with this CMP-based approach, no facets are present on the SiGe top surface. After CMP, the Si0.5Ge0.5 was chemically cleaned, loaded again in the EPI reactor and baked in H2. The top 30nm SiGe was recessed in-situ by HCl vapor and strained Ge channels were selectively grown at 350C on the Si0.5Ge0.5 buffer. The thermal budget of the bake and the recess of the SiGe surface was closely investigated in order to both remove the SiGe native oxide and to avoid any Si0.5Ge0.5 surface reflow in the trench. For 5min deposition time, a defect free 24nm strained Ge channel (2.8GPa stress measured in the Ge channel), was grown on the Si0.5Ge0.5 in the active trench (Figure 2). The thermal stability of the strained Ge channel was investigated for different thicknesses with different Si cap passivation processes.

As post-Si era for digital device is incipient, In0.53Ga0.47As is good candidate among n-type active channels with high electron mobility but - unlike Si - it lacks a well-established technology for dielectric gating which may bear aggressive device scaling. Here we propose a viable route for the atomic layer deposition (ALD) of high-κ dielectrics taking advantage from the well-known self-cleaning effect of the trimethylaluminum (TMA) precursor on the III-V compound surfaces. In this respect, the incorporation of Al2O3 cycles both as pre-conditioning surface treatment and inside the ALD growth of a MO2 host matrix (M=Zr, Hf) is here investigated. Al:MO2/In0.53Ga0.47As heterojunctions have been scrutinized by in situ spectroscopic ellipsometry and ex situ chemical depth-profiling analysis which validate a good physical quality of the oxide and elucidate the effect of the pre-conditioning cycles at the interface level. The resulting MOS capacitors have been characterized by means of multifrequency capacitance-voltage measurements and conductance analysis therein yielding a permittivity of 19{plus minus}1 both for Al:HfO2 and Al:ZrO2 and similar electrical quality of the interfaces. On the other hand, Al:HfO2 appears to be electrically more robust against leakage and endowed with a lower frequency dispersion in accumulation.

We report two approaches to integrate high quality III-V templates with low defectivity on Si wafers by epitaxial growth. The first approach is based on blanket, InGaAs-based Strain Relaxed Buffers grown by MOVPE on 200mm Si, and the second on the selective area MOVPE of InP in Shallow Trench Isolation structures patterned on 300mm Si. Both structures are characterized structurally and show the efficient trapping and annihilation of defects propagating from the Si/III-V interface. We believe these two approaches represent viable alternatives towards the realization of CMOS-compatible III-V templates and stacks for high-performance devices monolithically integrated on Si.

In this contribution, we discuss the crystalline properties of strained and strain-relaxed CVD-grown GeSn layers with Sn content in the range 6.4-12.6 at.%. A positive deviation from Vegard's law was observed and a new experimental bowing parameter was extracted for GeSn: bGeSn = 0.041 Å (in excellent agreement with recent theoretical predictions). The GeSn critical thickness for strain relaxation as a function of Sn concentration was determined, resulting in significantly higher values than those predicted by equilibrium models. A composition-dependent strain relaxation mechanism was also found, with the formation of an increasing density of GeSn pyramidal islands in addition to misfit dislocations at lower Sn concentration. © 2013 The Electrochemical Society. ispartof: ECS Journal of Solid State Science and Technology vol:2 issue:4 pages:P134-P137 status: published

Si CMOS technology is currently changing with the introduction of strain and new materials (Ge, III/V) to increase carrier mobility and devicesaturationcurrent.Recently,excellentGe-basedpMOSchannel performance has been demonstrated with intrinsic hole mobilities far above the universal Si mobility curve which is reflected in a clear increase in device current. 1‐4 However, while relaxed Ge exhibits significantly higher intrinsic hole mobilities than relaxed Si, it does not out-perform the current “state of the art” uniaxially strained Si pMOS devices. For Ge channel pMOS devices, compressive uni-axial and/or bi-axial strain implementation seems essential to substantially increase carriers velocity and to outperform current Si- and Si1-yGeybased devices, which is confirmed by theoretical calculations of the carrier mobility and device current. 5‐7 Ge1-xSnx offers schemes to implement the required strain types and levels in the active part of the device. Recent breakthroughs in low temperature hetero-epitaxial Ge1-xSnx and SiyGe1-x-ySnx growth on Si substrates as e.g. reported in references 8‐14 have triggered the assessment of this material system for such electrical device applications. In this contribution we discuss the use of Ge1-xSnx for future (electrical) device applications and its fabrication with a special attention on recent achievements from imec.