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Controlling properties of GaN/dielectric interfaces is crucial for determining the characteristics of MOS-HEMT devices and their stability. Interface properties are largely affected by the techniques and specific conditions of dielectric deposition. In this work, a Taguchi design of experiment was applied to study the effect of plasma parameters during deposition of SiOx by PECVD for passivation of n-GaN. SiOx/GaN MIS capacitors were fabricated and characterized by capacitance measurement at a high probing frequency of 1 MHz. The interface states density, hysteresis and flatband voltage were analyzed and modeled in relation with the flow of SiH4, plasma power, chamber pressure and temperature. Excellent fits could be obtained on a single model including linear terms for all studied parameters and quadratic terms for the flow of SiH4 and temperature. We show that it is possible to obtain some control of the flatband voltage while maintaining a good interface quality. Positive flatband voltages are potentially of interest to enable normally-off operation for MOS-HEMTs and this could be obtained mainly by using a high SiH4/N2O ratio. To the contrary, negative flatband voltage values often ensure the most stable operation of MOS-HEMTs and this was achieved with a low SiH4/N2O and high plasma power. MIS capacitors with near-zero flatband voltage were also obtained with low SiH4/N2O ratio and low plasma power. Hysteresis and interface states density in relation with deposition plasma conditions are also analyzed in order to offer the best trade-offs depending on the end applications of MOS-GaN devices. By demonstrating the great impact of plasma conditions during dielectric deposition on electronic properties of MIS devices, we show that the process of gate insulation can be optimized to simultaneously control the density of defects and fixed charge at the interface.

The industrial drive towards smaller semiconductor devices is at less than 10 nano-meters. In the next few years a three-dimensional quantum confined device structure is expected. We have studied the electronic structure of hydrogen-like donor impurities in Si and Ge quantum dots with varied shape of the confinement potential. These calculations are carried out within the Density-Functional-Effective-Mass Theory (DF-EMT). We have paid particular attention to the electron-electron interaction energy in a negative charge state of the donor impurity. The effect of electron correlation on the binding energy has been explored. In addition to these, we show that the second order correction to the ground state energy obtained through perturbative approach agrees well with the DF-EMT based numerical results, down to very small sizes of the quantum dots when the depth of the confinement is moderate or small. A non-monotonic shallow-deep transition of the binding energy of neutral and charged donors of hydrogen-like impurities is expected to occur with the reduction in the size of the quantum dot. A similar effect is expected for hydrogen-like acceptor impurities as well. Furthermore, the optical gap also shows non-monotonic shallow-deep behaviour with the quantum dot size reduction. Deepening of shallow donor or acceptor level implies that the carriers will freeze out at small sizes of the dot. We believe this is quite important in the context of metal-oxide-semiconductor (MOS) devices beyond 5 nm technologies, based on Si, Ge or a combination (SiGe). We also point out possible variabilities in the binding energy of donors and acceptors if there are variations in the size of host quantum dots in a large assembly of devices in future integrated circuits. This will lead to the variabilities in the characteristics from device to device. These results should be incorporated in the Technology Computer Aided Design (TCAD) simulation of less than or equal to 5 nm MOS devices.

This paper thoroughly analyses the role of drift in the sensitive region in the single-event effect (SEE), with the aim of enhancing the single-particle radiation resistance of N-type metal-oxide semiconductor field-effect transistors (MOSFETs). It proposes a design for a Si-based device structure that extends the lightly doped source–drain region of the N-channel metal-oxide semiconductor (NMOS), thereby moderating the electric field of the sensitive region. This design leads to a 15.69% decrease in the charge collected at the leaky end of the device under the standard irradiation conditions. On this basis, a device structure is further proposed to form a composite metal-oxide semiconductor (MOS) by connecting a pn junction at the lightly doped source–drain end. By adding two charge paths, the leakage collection charge is further reduced by 13.85% under standard irradiation conditions. Moreover, the deterioration of the drive current in the purely growing lightly doped source–drain region can be further improved. Simulations of single-event effects under different irradiation conditions show that the device has good resistance to single-event irradiation, and the composite MOS structure smoothly converges to a 14.65% reduction in drain collection charge between 0.2 pC/ μ m and 1 pC/ μ m Linear Energy Transfer (LET) values. The incidence position at the source-to-channel interface collects the highest charge reduction rate of 28.23%. The collecting charge reduction rate is maximum, at 17.12%, when the incidence is at a 45-degree angle towards the source. [ABSTRACT FROM AUTHOR]

Channel mobility modeling is of great significance for the development and analysis of SiC MOS devices due to complex SiC/SiO2 interface. In the context of the physical understanding of carrier scattering mechanisms, this paper presented an overview of the research progress and limitations of 4H-SiC channel mobility model. The intrinsic and extrinsic factors responsible for the degeneration of SiC channel mobility were extensively investigated to provide theoretical guidance for accurate channel mobility modeling. Furthermore, the electrical characterization methods of SiC channel mobility through current-voltage characteristics and Hall-effect measurement were discussed in detail. A simulation methodology was developed to reproduce experimental data through parameter identification technique, which could achieve piecewise calibration of multiple model parameters for SiC channel mobility and SiC/SiO2 interface characteristics. The comprehensive understanding of SiC channel mobility can provide a great value for simulation modeling and device analysis. [ABSTRACT FROM AUTHOR]

The extraordinary behavior of the oxide charge in SiO2/Si structures processed under the conditions reproducing chemical-vapor-deposition (CVD) growth of thin carbon films is reported. The charge in the SiO2 dielectric layers and the SiO2/Si interface quality in the structures subjected to high-temperature annealing in a CVD reactor were studied using a high-frequency capacitance–voltage technique. It is shown that a huge positive charge is generated in the SiO2 dielectric layers under annealing in an ethanol-containing atmosphere at temperatures of about 600–700°C. The surface density of the induced oxide charge can be as high as 4 × 1012 cm−2 and is expected to strongly influence the parameters and performance of fabricated metal–oxide–semiconductor devices. The positive charge induced in the SiO2 layers is presumably related to carbon diffusion which starts to be effective at 600–700°C. The quality of the SiO2/Si interface significantly degraded after annealing at temperatures higher than 700°C, however, no explicit relationship to a precursor used for CVD growth was found. [ABSTRACT FROM AUTHOR]

In this paper, the transient breakdown voltage (TrBV) of a silicon-on-insulator (SOI) laterally diffused metal-oxide-semiconductor (LDMOS) device was increased by introducing a step P-type doping buried layer (SPBL) below the buried oxide (BOX). Device simulation software MEDICI 0.13.2 was used to investigate the electrical characteristics of the new devices. When the device was turned off, the SPBL could enhance the reduced surface field (RESURF) effect and modulate the lateral electric field in the drift region to ensure that the surface electric field was evenly distributed, thus increasing the lateral breakdown voltage (BVlat). The enhancement of the RESURF effect while maintaining a high doping concentration in the drift region (Nd) in the SPBL SOI LDMOS resulted in a reduction in the substrate doping concentration (Psub) and an expansion of the substrate depletion layer. Therefore, the SPBL both improved the vertical breakdown voltage (BVver) and suppressed an increase in the specific on-resistance (Ron,sp). The results of simulations showed a 14.46% higher TrBV and a 46.25% lower Ron,sp for the SPBL SOI LDMOS compared to those of the SOI LDMOS. As the SPBL optimized the vertical electric field at the drain, the turn-off non-breakdown time (Tnonbv) of the SPBL SOI LDMOS was 65.64% longer than that of the SOI LDMOS. The SPBL SOI LDMOS also demonstrated that TrBV was 10% higher, Ron,sp was 37.74% lower, and Tnonbv was 10% longer than those of the double RESURF SOI LDMOS. [ABSTRACT FROM AUTHOR]

[Display omitted] • The reliable high-κ oxide/diamond interfacial atomic models and detailed band alignments are provided. • High-κ M O x /diamond displays typical electronic character of the "type-II" band configuration, effectively confining holes. • The application potential of high-κ oxide gate dielectrics in diamond MOS devices is evaluated. The ultra-wide bandgap semiconductor diamond represents a promising potential for advancement and innovation in the field of electronic device development. Utilizing first-principles calculations, a thorough investigation has been performed on the structural and electronic characteristics of M O x /diamond (M O x = HfO 2 , ZrO 2 , TiO 2 , Al 2 O 3 , Sc 2 O 3 , Y 2 O 3) heterostructures. The concentration of charge transfer at the high-κ oxide/diamond interfaces leads to obvious interface polarity localization characteristics. The studied M O x /diamond heterojunctions feature insulating interfaces without any gap states. The M O x /diamond supercells exhibit the ability to effectively confine holes on the diamond surface owing to the large band offsets (>1 eV), showing typical electronic properties of "type II" staggered energy band configurations. These findings demonstrate that the high-κ oxide M O x /diamond can serve as highly promising diamond gate dielectrics, and provide theoretical insights into the interfacial engineering of diamond MOS devices. [ABSTRACT FROM AUTHOR]

Electron trapping in HfO 2 -based MOS structures was studied through pulsed capacitance-voltage (C-V) technique. 10 nm HfO 2 layer was deposited by atomic layer deposition over a HF last treated Si substrate. The C-V curves were observed to shift to positive voltages driven by the positive applied voltage along the pulses, consistent with electron trapping due to tunneling transitions between the substrate and pre-existing defects within the oxide and the subsequent lattice relaxation through electron-phonon interaction. The dependences of the voltage shift for a given capacitance value (ΔV C) with stress bias and time, allowed to distinguish two mechanisms. An initial trapping process occurs for times shorter than the microsecond, probably associated with a thin non-stoichiometric SiO x interfacial layer, which is followed by a trapping process that starts after tens of μs and progressively slowed down, associated with traps within the HfO 2 layer. Numerical simulations yield for the HfO 2 traps an energy of 1.3 eV below the conduction band edge, decreasing exponentially with the distance from the Si interface with a characteristic length of 1.7 nm; and phonon and relaxation energies of 50 meV and 1 eV, respectively. These physical parameters are consistent with previous reports of electron trapping in HfO 2 layers deposited on a controlled interfacial layer, suggesting that trapping properties of defects inside the HfO 2 layer are insensitive to the treatment of the Si surface before HfO 2 deposition. On the other hand, the observed large initial trapping suggests that the non-controlled SiO x interfacial region is more defective than a controlled one. [Display omitted] • Electron trapping in HfO 2 layer deposited over HF last treated Si was studied. • A physics-based numerical model was employed to reproduce experimental results. • An initial trapping process is associated with a defective SiO x interfacial layer. • Trapping inside HfO 2 does not depend on the underlying interfacial layer. [ABSTRACT FROM AUTHOR]

[Display omitted] • The rGO:ZnO thin films were successfully coated by spin coating method on the surface of pSi. • The C-V and G-V measurements of the prepared heterojunctions were measured in dark current. • The core shell structure has positively affected the capacitance and dielectric parameters. • The prepared heterojunctions are promising for supercapacitor applications. The study focused on the relaxation and polarisation mechanisms of Al/(rGO:ZnO core–shell)/pSi/Al MOS structures. For this purpose, the rGO:ZnO core–shell structures were synthesised by sol–gel procedures and coated on pSi by spin-coating. The structures were characterized as chemical, morphological and micro-structural using FESEM-EDS, AFM, XRD and Raman analysis. Additionally, the capacitance (C), conductance (G/ω), dielectric permittivity (ε′ and ε″), loss factor(tanδ), electric modulus(M′ and M″) of the samples were successfully examined by DS over the wide range of frequencies (100 Hz-1 MHz) for determining dielectric parameters. Three distinct regions were visible on the C-V and C-ω plots: accumulation (−4 to 0 V), depletion (0 to 2 V), and inversion (2 to 4 V). Two relaxation times (10-4s-10-7s) were obtained in ε′-V and ε′-ω graphs between 1–100 kHz (region 1) and 100 kHz-1 MHz (region 2). The relaxation times were according to the Maxwell-Wagner and dipolar polarisation mechanism. As a result, the capacitive effect was observed and the equivalent RC circuit obtained from the Cole-Cole diagrams allowed the samples to be used in energy storage or different electronic applications. [ABSTRACT FROM AUTHOR]

This paper thoroughly analyses the role of drift in the sensitive region in the single-event effect (SEE), with the aim of enhancing the single-particle radiation resistance of N-type metal-oxide semiconductor field-effect transistors (MOSFETs). It proposes a design for a Si-based device structure that extends the lightly doped source–drain region of the N-channel metal-oxide semiconductor (NMOS), thereby moderating the electric field of the sensitive region. This design leads to a 15.69% decrease in the charge collected at the leaky end of the device under the standard irradiation conditions. On this basis, a device structure is further proposed to form a composite metal-oxide semiconductor (MOS) by connecting a pn junction at the lightly doped source–drain end. By adding two charge paths, the leakage collection charge is further reduced by 13.85% under standard irradiation conditions. Moreover, the deterioration of the drive current in the purely growing lightly doped source–drain region can be further improved. Simulations of single-event effects under different irradiation conditions show that the device has good resistance to single-event irradiation, and the composite MOS structure smoothly converges to a 14.65% reduction in drain collection charge between 0.2 pC/μm and 1 pC/μm Linear Energy Transfer (LET) values. The incidence position at the source-to-channel interface collects the highest charge reduction rate of 28.23%. The collecting charge reduction rate is maximum, at 17.12%, when the incidence is at a 45-degree angle towards the source.

We report the fabrication of novel self-biased high resolution radiation detectors achieved in n-type 4H-SiC metal-oxide-semiconductor (MOS) devices. Vertical MOS structure has been realized by pulsed laser deposition of 40 nm Y2O3 layer on 20 $\mu \text{m}$ n-type 4H-SiC epilayer followed by sputter coating a nickel gate, which revealed a record-high hole diffusion length. The MOS device exhibited a remarkable radiation detection response to 5486 keV alpha particles with a charge collection efficiency of 82% and an energy resolution of 72 keV full width at half maximum (FWHM) at zero applied bias. The hole diffusion length has been calculated to be 56 $\mu \text{m}$ using a drift-diffusion model. Such long hole diffusion length and a flat-band potential of 2.1 V, enabled to attain high efficiency and resolution in the self-biased mode. Band energy calculations indicated that the presence of Y2O3 layer may have neutralized the hole traps usually present in a metal-4H-SiC interface thereby substantially improving the hole transport. Such high performing self-biased radiation detectors fabricated on 4H-SiC are intended for applications in harsh environment space missions, wherein carrying detector power supplies as a payload becomes a critical logistic issue. The present study opens the high potential of other wide bandgap semiconductors as self-biased MOS devices as well. [ABSTRACT FROM AUTHOR]

Advanced indentation techniques have been introduced to study the effects of multiple stresses on the transistor characteristics with using a cylindrical tip with various alignments. Particularly, controlling the cylinder tip orientation relative to the transistor channel direction is proposed to selectively strain the silicon channels in order to induce very different selectively controlled stresses. Several tip alignments allow to shift the stresses from uniaxial towards biaxial stress as well as to induce shear stress. Ring oscillator circuits based on NAND and NOR gates are used to monitor the stress effects on the characteristic circuit frequency as well as on the individual transistors. Finite Element simulations help to identify optimized setup properties for the targeted application. Comparison with previous indentation experiments derives the specific influence of each stress tensor component on the transistor characteristics. [ABSTRACT FROM AUTHOR]

Serial communication buses are used in electronic systems to interconnect sensors and other devices, but two of the most widely used protocols, i.e., interintegrated circuit (I2C) and serial peripheral interface (SPI), are vulnerable to bus-wide failure if even one device on the bus malfunctions. For aerospace applications demanding increasingly more distributed processing and sensing capability, the compounding risk to system reliability as device count scales becomes a limiting factor in mission scope, performance, and lifetime. We propose a simple external circuit to be added to each node on a communication bus that automatically isolates the node in the event of device failure. By automatically isolating failed devices, the integrity of the bus is preserved without requiring additional signals or processing overhead from the host controller. In this article, I2C and SPI isolation circuits are simulated, fabricated, and experimentally verified to be effective at preserving bus integrity in the event of peripheral device failure. The isolation circuits were integrated into three spacecraft for the successful NASA V-R3x mission and found to significantly improve system reliability by eliminating single-point failure modes of the I2C and SPI buses. The developed protection schemes are a valuable tool for decoupling system reliability from serial bus device count and can readily be integrated into the existing aerospace systems. [ABSTRACT FROM AUTHOR]

Velocity picking, a critical step in seismic data processing, has been studied for decades. Although manual picking can produce accurate normal moveout (NMO) velocities from the velocity spectra of prestack gathers, it is time-consuming and becomes infeasible with the emergence of a large amount of seismic data. Numerous automatic velocity picking methods have thus been developed. In recent years, deep learning (DL) methods have produced good results on the seismic data with medium and high signal-to-noise ratios (SNRs). Unfortunately, it still lacks a picking method to automatically generate accurate velocities in situations of low SNR. In this article, we propose a multiinformation fusion network (MIFN) to estimate stacking velocity from the fusion information of velocity spectra and stack gather segments (SGSs). In particular, we transform the velocity picking problem into a semantic segmentation problem based on the velocity spectrum images. Meanwhile, the information provided by SGS is used as a prior in the network to assist segmentation. The experimental results on two field datasets show that the picking results of MIFN are stable and accurate for the scenarios with medium and high SNR, and it also performs well in low SNR scenarios. Code is made publicly available at https://github.com/newbee-ML/MIFN-Velocity-Picking [ABSTRACT FROM AUTHOR]

The total ionizing dose (TID) effect is one of the main causes of the performance degradation/failure of semiconductor devices under high-energy γ-ray irradiation. In special, the concentration of doubly-hydrogenated oxygen vacancy (a case study of VoγH2) in the oxide layer seriously exacerbates the TID effect. Therefore, we developed a dynamic model of mobile particles and fixed defects by solving the rate equations and Poisson’s equation simultaneously, to reveal the contribution and influence mechanisms of VoγH2 on the TID effect of MOS devices. We found that VoγH2 can directly and indirectly promote the formation of Voγ+ and VoγH+, respectively, which can increase the electric field near the Si/SiO2 interface and reduce the threshold voltage of silicon MOS devices accordingly. Controlling VoγH2 with a concentration below 1014 cm−3 can suppress the adverse TID effects. The results are much helpful for analyzing the microscopic mechanisms of the TID effect and designing new MOS devices with high radiation-hardening.

A comprehensive study has been done on the influence of post-deposition annealing temperature on high-k cerium oxide (CeO 2) layer grown on n-type silicon (Si) substrate and its resultant interface states have been studied for Al/CeO 2 /Si metal-oxide-semiconductor (MOS) devices. The high-k CeO 2 thin films were deposited by spin-coating and sintered at different annealing temperatures (T a) in the range of 400–900 °C. The parameters such as fixed charge density (Q eff), dielectric constant (k) of the layers, flat-band voltage (V FB), interface defect density (D it), etc., of the MOS device were evaluated from C V and I-V measurements. A minimum value of flat band shift (∼0.05 V) with lower Q eff (−4.81 × 1011 C/cm2) have been achieved for the T a of 600 °C. The k and D it were evaluated to be 22 and 1.29 × 1012 cm−2, respectively at the T a of 600 °C. In addition, the C V measurements showed a very small hysteresis and very low frequency dispersion for the T a of 600 °C sample. Energy distribution of defect states was evaluated and it was maximum towards the bottom of the conduction band. This shows that the 600 °C is the optimum annealing temperature, which results in high quality interface, and the electron affinity of the corresponding CeO 2 layers was found to be 3.29 eV as evaluated from ultraviolet photoelectron spectroscopy (UPS). Further, a maximum value of minority carrier lifetime (147 μs) has been achieved for the samples annealed at T a of 400 °C, indicating that the post-annealing temperature plays a significant role on the properties of CeO 2 films deposited by sol-gel process. Thus, the present study demonstrates the possibility of sol-gel grown high k-CeO 2 layers suitable for MOS like devices. [Display omitted] • High-k CeO 2 layers were successfully deposited on Si by spin coating method. • Energy distribution of defect states was maximum towards the bottom of the CB. • The electron affinity of the corresponding CeO 2 layers was found to be 3.29 eV. • Maximum minority carrier lifetime (147 μs) has been achieved for 400 °C annealed sample. • The MOS device with 600 °C annealed CeO 2 layer showed a small flat-band shift. [ABSTRACT FROM AUTHOR]

Monolayer HfS2 is promising for an all-2D CMOS platform due to its well-balanced n- and p-type transport properties, and is predicted to show high drive currents into the sub-10-nm channel length regime. However, the OFF-state performance of the ultrascaled HfS2 pMOS device is limited by direct source-drain tunneling (SDT) due to carriers in the degenerate light-hole band. Here we use full-band quantum transport simulations to show that this effect can be mitigated through the use of uniaxial tensile strain, which splits the degeneracy of the valence bands and tunes the effective mass in the transport direction to suppress SDT. Strain of 1-2% applied in the transport direction reduces the subthreshold swing by over 20 mV/dec, which can improve the ON current by over 50% at channel lengths below 7 nm. This approach can be further used to tune the HfS2 pMOS device to match the nMOS characteristics at a similar channel length. [ABSTRACT FROM AUTHOR]

This article presents a 55–63-GHz fundamental multicore voltage-controlled oscillator (VCO) in a 28-nm bulk CMOS process. The single-core VCO utilizes stacking and magnetic coupling of two NMOS-based resonators, which increases the tank energy for phase noise reduction while maintaining low voltage swings for reliability. In the multi-core configuration, the oscillators are coupled in a way that also simplifies LO distribution toward the transmitter and receiver. The potential parasitic modes that occur both in single-core and multi-core configurations are suppressed by design. The implicit common-mode (CM) impedance control is utilized to reduce phase noise without any large extra tail inductor as used in a conventional complementary oscillator. The distributed nature of energy restoring elements in the proposed stacked oscillator also offers robust parasitic mode suppression compared to alternative implementation based on a conventional complementary oscillator. The working range of the prototype is between 55 and 63 GHz corresponding to a tuning range of 13.4% with power consumption varying from 15.3 to 12 mW across the tuning range. The prototype achieves the best phase noise of −95 and −121.7 dBc/Hz at 1- and 10-MHz offsets from the carrier at 55GHz. The corresponding peak figure of merits (FOMs) achieved are 178 and 185 dBc/Hz at 1- and 10-MHz offsets from the carrier. [ABSTRACT FROM AUTHOR]

β-Ga2O3 has become an ultimate choice of emerging new-generation material for its wide range of compelling applications in power electronics. In this review, we have explored the available radiations in the atmosphere and the effects of radiation on the β-Ga2O3 material and devices. The focus in this review summarizes various studies covering different radiation such as swift heavy ions, protons, neutrons, electrons, Gamma, and X-rays to understand the radiation-induced effects on the structure and their reliable performance in harsh environments. In addition, we focused on the various pre-existing defects in β-Ga2O3 and the emergence of radiation-induced defects that provoke a severe concern, especially from the device performance point of view. This review presents the irradiation-induced effects on the devices such as high-power devices such as Schottky barrier diodes (SBDs), field-effect transistors (FETs), metal-oxide-semiconductor (MOS) devices, and photodetectors. Some key studies including the changes in carrier concentration with a removal rate, Schottky barrier height (SBH), ideality factor, defect dynamics dielectric damage, interface charge trapping, a thermally activated recovery mechanism for charge carriers at elevated temperature, and diffusion length of minority charge carriers. These reports show that β-Ga2O3-based devices could be deployable for space or high-radiation terrestrial applications. These results provide/suggest a better device design based on the radiation degradation studies in the state-of-the-art β-Ga2O3 devices. [ABSTRACT FROM AUTHOR]

The operation of a capacitorless (1T) dynamic random access memory (DRAM) can be compromised if the storage region is located near metal–semiconductor junction in a reconfigurable field-effect transistor (RFET). Through subtle modifications, without affecting current drive, capacitance, and reconfigurable features, the present work showcases feasible 1T-DRAM operation in a RFET with an intentionally misaligned polarity gate. Analysis based on device physics and operation, highlights 1T-DRAM for standalone and embedded applications with impressive performance indicators: sense margin $\ge 6~\mu \text{A}/\mu \text{m}$ , retention time ≥16 ms (for embedded), and ≥64 ms (for standalone) at 85 °C, current ratio of ~104 along with a low write (~ 1 ns) and read (~ 2 ns) time. Guidelines in terms of scalability of total length and biases for implementing 1T-DRAM cell are presented. [ABSTRACT FROM AUTHOR]

In this article, a low-power, radiation-hard front-end circuit for monolithic pixel sensors, designed to meet the requirements of low noise and low pixel-to-pixel variability, the key features to achieve high detection efficiencies, is presented. The sensor features a small collection electrode to achieve a small capacitance (<5 fF) and allows full CMOS in-pixel circuitry. The circuit is implemented in the 180-nm CMOS imaging technology from the TowerJazz foundry and integrated into the MALTA2 chip, which is part of a development that targets the specifications of the outer pixel layer of the ATLAS Inner Tracker upgrade at the LHC. One of the main challenges for monolithic sensors is a radiation hardness up to 1015 1-MeV $\text {n}_{\text {eq}}/\text {cm}^{{2}}$ non-ionizing energy loss (NIEL) and 80 Mrad total ionizing dose (TID) required for this application. Tests up to ${3} \cdot {10}^{15}$ 1-MeV $\text {n}_{\text {eq}}/\text {cm}^{{2}}$ and 100 Mrad were performed on the MALTA2 sensor and front-end circuit, which still show good performance even after these levels of irradiation, promising for even more demanding applications such as the future experiments at the high-luminosity large hadron collider (HL-LHC). [ABSTRACT FROM AUTHOR]

This brief presents a 1-tap pre-emphasis transmitter (TX) for a single-ended ground-terminated memory interface with 28 nm complementary metal-oxide-semiconductor (CMOS) technology. By employing a charge pump scheme, a voltage level below ground was used to remove inter-symbol interference (ISI). Encoded with the unit interval (UI) delayed data, the proposed equalization technique increases the vertical voltage margin for the receiver (RX) compared to conventional feed-forward equalization (FFE). In addition, the short current after equalization was removed, and impedance matching for reflection was facilitated. The data rate of the proposed work is 15 Gb/s, and the data path power dissipation for the entire design is 20.3 mW. The measured energy efficiency is 1.35 pJ/bit, and the total area occupation is 0.008 mm2. [ABSTRACT FROM AUTHOR]

A time-interleaved duobinary encoding scheme for the low-power high-bandwidth memory (HBM) I/O interface is proposed with a 65-nm CMOS process. To reduce power consumption in HBM I/O using multiple through-silicon via (TSV) I/Os, a transmitter (TX) that performs duobinary signaling with a voltage-mode driver is proposed. A small area encoder is implemented to generate duobinary output and an edge-boosted pre-driver is proposed to improve the slew rate and the robustness against the process, voltage, and temperature (PVT) variations of the duobinary voltage-mode driver. To convert the duobinary signal into a non-return-to-zero (NRZ) signal, a one-tap decision feedback equalizer (DFE) is used at the receiver (RX). NRZ signal conversion is proposed using one reference voltage and one PMOS switch to reduce the hardware complexity caused by additional reference voltages. An eight-stacked TSV is emulated in the 65-nm CMOS process, and the emulated capacitance of each stack is 100 fF. The energy efficiency of the proposed transceiver chip is 0.373 pJ/b/pF with a 27 – 1 pseudorandom binary sequence at 5 Gb/s. [ABSTRACT FROM AUTHOR]

In this article, a novel voltage divider trigger silicon-controlled rectifier (VDTSCR) with low trigger voltage and low leakage current for electrostatic discharge (ESD) protection applications has been proposed and verified in a 65-nm epitaxial CMOS process. The trigger structure formed by a voltage divider and an nMOS is introduced to the proposed structure. The voltage divider composed of two series capacitors can control the turn-on of the nMOS, and the nMOS current can trigger the silicon-controlled rectifier (SCR) device to reduce the trigger voltage of the proposed device. Such triggering structure is fully embedded in the proposed device for saving area. The measurement results show that the proposed device can achieve a low trigger voltage of 2.88 V, a low leakage current of 120 pA, and the second breakdown current of 4.35 A for a 1.2-V application. Furthermore, the VDTSCR device can be immune from the risk of latch-up and false triggering. Due to the low trigger voltage and low leakage current of the proposed device, it is suitable for low-voltage and low-power applications. [ABSTRACT FROM AUTHOR]

Analog single-event transient (ASET) and total ionizing dose (TID) characterization of a radiation-hardened bandgap voltage reference (BGR) is investigated in a 28-nm commercial bulk CMOS technology. Different radiation hardened by design (RHBD) techniques are used for ASET mitigation in the circuit and layout, and the circuit is optimized to ensure the BGR can still work correctly even using fast nMOS and slow pMOS for TID mitigation. Heavy-ion (linear energy transfer (LET) = 76.3 MeV $\cdot $ cm2/mg) experiments show the maximum amplitude of positive (negative) ASET is just 30 mV (90 mV), and Co60 gamma-ray experiments show the maximum output voltage reduction is just 37 mV after 1.2 Mrad(Si) irradiation, and the final output voltage reduction is just 11 mV after 48 h of annealing. All of the experiments indicate that ASET is significantly mitigated by the RHBD techniques, and the BGR has naturally good TID response due to the design margin. The investigation also indicates that the proposed BGR is a good substitute for space application due to the excellent ASET and TID tolerance capability. [ABSTRACT FROM AUTHOR]

This paper models first snapback ambipolar action in NMOS, when subjected to high current stress across the drain terminal. We analyze 2 − D ambipolar current in Gate Grounded NMOS (GGNMOS) devices close to pinch-off region, which is related with S shaped I-V characteristics under highly injected avalanche generated carriers. Furthermore, the first snap-back phenomenon in GGNMOS owing to surface bipolarity is investigated. Due to ambipolar current flow and barrier lowering at source-body junction a novel model of surface bipolar activity has been presented. An analytical model for the surface electrostatics is provided and further compared with 2 − D TCAD device simulation results. Moreover, the electron and hole coupling is reported through a simplified model for a complex and distributed 2 − D parasitic bipolar transistor. [ABSTRACT FROM AUTHOR]

In this article, we propose a CMOS active balun targeting high linearity up to high voltage swing and over wide bandwidth for direct RF sampling applications. All the blocks of this active balun are derived using a common highly linear building block (HLBB). The HLBB is designed using an inverter with strong source degeneration. To increase the linearity of this HLBB further, its nonlinearity mechanisms are analyzed in detail. A bootstrapping technique is included in the HLBB to reduce the dominant nonlinearity. Furthermore, a pre-distortion technique cancels most of the non-linearity of the output driving stages. All the linearization techniques proposed are robust to process, voltage, and temperature (PVT) changes. The measured results of the active balun realized on-chip in a 22-nm FDSOI CMOS shows $ < -$ 44-dBc third harmonic distortion (HD3) up to 1.5- $\text{V}_{\textrm {p-p}}$ output swing over 0.01–5.4 GHz. The measured gain and phase errors of the balun action are less than 0.5 dB and $\pm 5{^\circ }$ , respectively. The chip is powered from a 5-V supply and dissipates 925 mW. [ABSTRACT FROM AUTHOR]

A new millimeter-wave (mm-wave) fully-integrated 0.18- $\mu \text{m}$ BiCMOS frequency division duplex (FDD) transmit–receive (T/R) front-end module with internal power amplifier (PA) and low noise amplifier (LNA) is reported. It employs an active circuit to cancel the transmitter (TX) signal leaking into the receiver (RX). The T/R module provides 43.6 dB isolation between the PA output and LNA input at 29 GHz and 9.5 dB average noise figure (NF) over 27–29 GHz on the entire RX path. At 29 GHz, the T/R module has 13.8 and 10.6 dB gain on the RX and TX path, respectively. A design methodology is also presented for maximum isolation and optimum NF. It occupies a small area of 2 mm2. [ABSTRACT FROM AUTHOR]

We present the IDeF-X HDBD integrated circuit, our latest 32-channel application specified integrated circuit devoted to semiconductor photon counting X-ray detectors, designed to read charges ranging from −40 to 40 fC. The chip reaches an equivalent noise charge (ENC) floor of 17 electrons rms and is optimized for low input capacitance (< 10 pF). Each channel is based on an optimized charge sensitive amplifier (CSA) followed by a CR-RC2 filter and a peak detector with a power consumption of $850 ~\mu \text{W}$ /channel. Gain and shaping times are tunable. This circuit has been designed with radiation mitigation techniques to meet space application requirements. This ASIC can read either cadmium telluride or silicon detectors for imaging-spectroscopy applications. An energy resolution of 230-eV FHWM at 6 keV and a low-level threshold of 1.2 keV were demonstrated with a single pixel silicon drift detector connected to one channel. [ABSTRACT FROM AUTHOR]

A time-domain jitter estimation methodology considering process-voltage-temperature (PVT) variations of the single-ended ring oscillator (SERO) at an early stage of design is presented for near-threshold voltage (NTV) regime where non-linearities dominates. For the first time, the model accounts for the jitter due to the over/undershoot region which is critical in the NTV regime. Further, the model uses effective drive current, $I_{eff}$ model. The $I_{eff}$ is obtained considering the regions of device operation, instead of using only saturation current for jitter calculation. A time-domain jitter model is developed by considering the change in transition threshold points (TTPs) whose relative values are supply independent and $I_{eff}$ of each region with the PVT variation, design parameters, and with the introduction of noise in the circuit. The model analyzes the effects of random (white noise) and deterministic (supply, substrate) noise in the NTV regime. This approach is physics/topology-based and is valid for different technologies. Post-layout simulations have been performed on parasitic extracted netlist using CADENCE and HSPICE in STM 65nm CMOS Process Design Kit (PDK) to validate the jitter model in the NTV regime. [ABSTRACT FROM AUTHOR]

We propose and demonstrate self-aligned Double Injection Function Thin Film Transistor (DIF-TFT) architecture that mitigates short channel effects in 200 nm channel on non-scaled insulator (100 nm SiO2). In this conceptual design, a combination of ohmic-like injection contact and a high injection-barrier metal allows maintaining the high ON currents while suppressing drain-induced barrier lowering (DIBL) effects. Using an industrial 2-D device simulator (Sentaurus), we propose two methods to realize the DIF concept. We use one of them to demonstrate, experimentally, a DIF-TFT based on solution-processed indium gallium zinc oxide (IGZO). Using molybdenum as the ohmic contact and platinum as the high injection barrier, we compare three transistors’ source-contacts: ohmic, Schottky, and DIF. The fabricated DIF-TFT exhibits saturation at sub 1 V drain bias with only about a factor of 2 loss in ON current compared to the ohmic contact. [ABSTRACT FROM AUTHOR]

In this article, a robust high-holding voltage silicon-controlled rectifier (HHSCR) is implemented and realized in a 0.18- $\mu \text{m}$ BCD process for on-chip electrostatic discharge (ESD) protection. The proposed HHSCR was constructed by embedding a NMOSFET in the p-well of a modified lateral silicon-controlled rectifier (MLSCR). Benefiting from the shunting effect of the embedded NMOSFET path, the proposed HHSCR achieved a high-holding voltage with a relatively high robustness. Transmission line pulse (TLP) test results show that the proposed HHSCR exhibits a high-holding voltage of 11.6 V and a failure current (${I}_{\text {t2}}{)}$ of 1.59 A at a finger width of 50 $\mu \text{m}$. Furthermore, the internal physical mechanism of the proposed HHSCR was explored by technology computer-aided design (TCAD) simulation. [ABSTRACT FROM AUTHOR]

In this paper, the transient breakdown voltage (TrBV) of a silicon-on-insulator (SOI) laterally diffused metal-oxide-semiconductor (LDMOS) device was increased by introducing a step P-type doping buried layer (SPBL) below the buried oxide (BOX). Device simulation software MEDICI 0.13.2 was used to investigate the electrical characteristics of the new devices. When the device was turned off, the SPBL could enhance the reduced surface field (RESURF) effect and modulate the lateral electric field in the drift region to ensure that the surface electric field was evenly distributed, thus increasing the lateral breakdown voltage (BVlat). The enhancement of the RESURF effect while maintaining a high doping concentration in the drift region (Nd) in the SPBL SOI LDMOS resulted in a reduction in the substrate doping concentration (Psub) and an expansion of the substrate depletion layer. Therefore, the SPBL both improved the vertical breakdown voltage (BVver) and suppressed an increase in the specific on-resistance (Ron,sp). The results of simulations showed a 14.46% higher TrBV and a 46.25% lower Ron,sp for the SPBL SOI LDMOS compared to those of the SOI LDMOS. As the SPBL optimized the vertical electric field at the drain, the turn-off non-breakdown time (Tnonbv) of the SPBL SOI LDMOS was 65.64% longer than that of the SOI LDMOS. The SPBL SOI LDMOS also demonstrated that TrBV was 10% higher, Ron,sp was 37.74% lower, and Tnonbv was 10% longer than those of the double RESURF SOI LDMOS.

This brief presents a 20V square-wave output driver in standard bulk CMOS technology powered from a 2.5V supply. The proposed high-voltage driver is based on a bidirectional charge pump architecture which is by default modular, scalable and maintains all device voltage tolerances. Thanks to deep nwell isolation and a new all-nMOS driver stage design, we could extend the voltage range of our 65nm technology from 12 V to 20 V reliably. The driver uses thick-oxide devices readily available at no extra cost and occupies 0.13 mm2 of area. The driver has a 20V swing when driving a $100~\mu \text{A}$ load, fully switches a 50pF capacitive load at 25 kHz, and has a 48 % peak power efficiency. [ABSTRACT FROM AUTHOR]

This brief presents a general technique for achieving the highest possible RO oscillation frequency accompanied by lower phase noise in an enhanced circuit design utilizing novel delay cells. The circuit architecture has the delay cells’ inputs separated by an optimized skew offset. Skew-offset optimization is attained by integrating a pre-charge/discharge auxiliary feed-forward loop into the separately driven delay cells. This technique reduces the transition time when Supply and GND are simultaneously connected/disconnected to the delay cell’s output node. When these delay cells are connected in loops to form a Ring Oscillator, they provide high performance, even/odd multi-phase signals. The proposed methodology is validated in commercial 65nm and 180nm CMOS technologies. The post-layout simulations show that the proposed designs improve the performance by modulating the delay cell output node’s charging and discharging. The operating frequency of the proposed design, e.g., for odd stage 5/7 and even stage 4/8/16 stage, is almost 50%/40%, (80%/30%/20%) higher than that of the MSSRO (Multi-Loop Skew based Single-ended Ring Oscillator) with the same number of stages. Additionally, the designs proposed for the targeted phase noise and center frequency consume around 8–20% (odd stages)/ (6–28%) (Even stages) lesser power, a lower supply sensitivity up to 9%, and lower PVT variability up to 6% compared to its equivalent stages MSSRO (3-stages single-ended RO) counterparts in 180 nm CMOS Technology. [ABSTRACT FROM AUTHOR]

One-time programmable (OTP) memory is essential to the security and gaming industries because of its “write once, read many” capability. This device supports N-metal–oxide–semiconductor polycrystalline-silicon junctionless gate-all-around (GAA) nanowire transistor technology and can perform multistate antifuse. It is capable of functioning in four states instead of in the standard two states (open/short). Furthermore, the states can be read as fully open (0, 0), drain–gate breakdown (0, 1), source–gate breakdown (1, 0), and full breakdown (1, 1) states. The antifuse is formed from the oxide breakdown between the gate and the source or drain (S/D). Moreover, because multiple samples have been successfully produced, its information can be displayed as a chart or table to instantly convey information about the current device’s state to programmers by reading the S/D current. [ABSTRACT FROM AUTHOR]

Single-event transient (SET) glitches can be modified by body-biasing controlling techniques. In this article, a body-biasing configuration is proposed in combinational circuits, which plays no role during devices’ normal operation, but significantly mitigates SET disturbance as ion strike happens. NOR cell chains and NAND cell chains serve as cases to investigate the impact of the proposed configuration on SET vulnerabilities under two groups of heavy-ion experiments. Experimental data illustrate that transistors with body tied to source (BTS) significantly reduce the SET cross section compared with the normal designs. The physical mechanism of the proposed technique is quantitatively analyzed in detail. [ABSTRACT FROM AUTHOR]

In surface active seismic exploration, the near-surface imaging based on reflection signals provides valuable information for mineral exploration and deeper resources. However, the strong noises at near surface and stretching effects at nonzero offsets with conventional seismic data processing method severely damage the seismic reflection signals with low fold at near surface. The innovative method for the enhancement of seismic signals is the seismic interferometry method. However, due to the one-sided illumination, the seismic interferometry is still not suitable for the retrieval of reflection signals in most practical situations. In this article, we present the correlation-based interferometry (CI) method to enhance the reflection signals for near-surface imaging using the first cross correlation to construct virtual reflection signals and the second cross correlation to achieve the interferometric normal move-out (INMO) correction of the seismic reflection events with no stretching, which keeps the high resolution of near-surface reflection signals. Meanwhile, because of constructive interference stack, the CI method can significantly improve the signal-to-noise ratio (SNR) of reflection signals. The synthetic and field seismic data examples illustrate that the data-driven CI method performs better than the conventional stack (CS) method based on the velocity model for the near-surface reflection imaging. [ABSTRACT FROM AUTHOR]

Autonomous-driving features necessitate a fault-tolerant (FT) power-management unit in 48-V automotive applications. This article presents a monolithic single-phase closed-loop masterless FT four-to-one hybrid Dickson converter IC for high-conversion-ratio 48-V automotive multi-phase applications. The chip includes: 1) a mixed-signal droop-based valley-current ON-time quasi-fixed-frequency control, which enables masterless multi-phase operation capability; 2) single-point short-circuit fault and open-circuit fault detection and blocking of any power switches or flying capacitors; 3) an optimized high-voltage (HV) power stage with fully integrated flying-capacitor-sourced gate drivers without any external bootstrap capacitors; 4) a glitch-free cross-coupled bootstrapped HV level shifter; and 5) a dual-leg bidirectional closed-loop current-sensing circuit optimized for the hybrid Dickson topology. The design was fabricated in a 0.13- $\mu \text{m}$ 90-V automotive silicon-on-insulator (SOI) bipolar-CMOS–DMOS (BCD) process. The measured results confirm the operation over 20–60-V input, 3.3-V nominal output, 3-A maximum load, and 320-kHz effective switching frequency within the automotive-grade −40 °C–+125 °C ambient temperature. The design achieves above 90% measured efficiency at maximum conversion ratio and load at room temperature. A three-phase system is used to evaluate and confirm the fault-blocking capability and continuous power delivery upon detection of a fault. [ABSTRACT FROM AUTHOR]

Design technology co-optimization (DTCO) has been a workhorse in optimizing logic technology innovations for a few generations now. With increased complexity associated with each new node and the growing number of technological innovations, it is time to expand the conventional DTCO flows. In this article, we present a novel materials to systems co-optimization (MSCO) platform, expanding the boundaries of traditional DTCO to encompass materials modeling to all the way to system design. To demonstrate the application of our MSCO platform, we discuss various front-end-of-line (FEOL) and middle-of-line (MOL)/back-end-of-line (BEOL) technologies and show their impact on device and circuit performance. [ABSTRACT FROM AUTHOR]

In this article, a new freewheeling circuit with a junction field-effect transistor (JFET) structure is developed to replace the traditional high voltage diode for freewheeling in the high voltage monolithic IC for the first time. The JFET structure has its pinch-off voltage lower than 40 V, and it can sustain the reverse voltage higher than 500 V in off-state. Adopting the new freewheeling circuit, the reverse recovery charge (QRR) and the peak reverse recovery current (IRRM) is decreased boffy about 89.5% and 33.6%, respectively, when the load current is 0.5 A. Based on the proposed freewheeling circuit, a deadtime control circuit is also developed in this article. By employing that control circuit, it is no need to detect the output signal state of the counter channel before controlling the deadtime, therefore the deadtime could be designed as small as possible to decrease the freewheeling loss. In this article, the high voltage monolithic IC is implemented by thick layer silicon on insulator technology. All the new devices and circuits are compatible with the technology for the traditional monolithic IC without any additional process. [ABSTRACT FROM AUTHOR]

To enable passive infrared (PIR) sensors to detect stationary occupants, we recently invented a synchronized low energy electronically chopped PIR (SLEEPIR) sensor consisting of PIR sensor, a polymer dispersed liquid crystal (PDLC) infrared shutter and a driving circuit. By electrically chopping the long-wave infrared (8- $12~\mu \text{m}$) radiation received by the PIR sensor, the SLEEPIR sensor can detection both stationary and moving occupants. In this paper, we developed a theoretic model to better understand the output of the SLEEPIR) sensor, and thus optimize its fabrication process and detection performance. The model indicated that its performance is mainly depending on the effective modulation and response time of the PDLC shutter in addition to the time constants of the PIR sensor. We empirically found that the effective modulation and response time are largely dependent on the frequency and amplitude of the driving signal, as well as the mass ratio, cell gap and cooling rate of the PDLC shutter. In the end we obtained optimized parameters that can produce the maximal SLEEPIR output, and experimentally validated our obtained optimal parameters and fabrication conditions. [ABSTRACT FROM AUTHOR]

Current retinal prostheses (RPs) have not achieved useful vision restoration, as their resolution is limited by power dissipation and complexity of interconnect. This article presents an inductively powered wireless system on a chip (SoC) for an electrically controlled, optically addressed retinal prosthetic system. The SoC interfaces to a co-fabricated nanoengineered photosensitive electrode array using only two wires. To reduce the thermal dissipation near sensitive retinal tissue, the proposed design pushes voltage regulation and charge-balanced stimulation control off the implant via a duty-cycled wireless charge metering technique. A calibration technique compensating for power fluctuation caused by eye movement is also presented. Implemented in 180-nm CMOS and delivering up to $3~\mu \text{C}$ of charge at 20-nC resolution, the SoC achieves 73% RF-to-stimulation power efficiency. [ABSTRACT FROM AUTHOR]

Mixed-cell-height circuits have prevailed in advanced technology to address various design requirements. Along with device scaling, complex minimum-implant-area (MIA) constraints arise as an emerging challenge in modern circuit designs, adding to the difficulties in mixed-cell-height placement. Existing MIA-aware detailed placement with single-row-height standard cells is insufficient for mixed-cell-height designs: 1) filler insertion, typically used to resolve MIA violations, might incur unaffordable area and wirelength overheads and 2) mixed-height-cell perturbation could cause severe inter-row MIA violations. This article addresses the mixed-cell-height detailed placement problem considering both intra- and inter-row MIA constraints. We first fix intrarow violations by clustering violating mixed-height cells of the same threshold voltage, and then perturb each cluster to obtain a desired cell permutation by applying an efficient, optimal dynamic-programming-based algorithm for a special case and Algorithm DLX for general ones, where a provably constant performance ratio for a mixed-cell-height reshaping problem can be achieved. With a network-flow-based formulation, remaining violating cells are placed in appropriate filler-insertion positions to fix cell violations and minimize area. After performing mixed-cell-height detailed placement, we finally fix inter-row violations by shifting violating cells in minimum displacement. Experimental results show that our algorithm can efficiently solve all MIA violations without any extra area overhead. [ABSTRACT FROM AUTHOR]

High electron mobility transistor (HEMT) based on gallium nitride (GaN) is one of the most promising candidates for the future generation of high frequencies and high-power electronic applications. This research work aims at designing and characterization of enhancement-mode or normally-off GaN HEMT. The impact of variations in gate length, mole concentration, barrier variations and other important design parameters on the performance of normally-off GaN HEMT is thoroughly investigated. An increase in the gate length causes a decrease in the drain current and transconductance, while an increase in drain current and transconductance can be achieved by increasing the concentration of aluminium (Al). ForAlmole fractions of 23%, 25%, and 27%, within Al gallium nitride (AlGaN) barrier, the GaN HEMT devices provide a maximum drain current of 347, 408 and 474 mA/µm and a transconductance of 19, 20.2, 21.5 mS/µm, respectively. Whereas, for Al mole fraction of 10% and 15%, within AlGaN buffer, these devices are observed to provide a drain current of 329 and 283 mA/µm, respectively. Furthermore, for a gate length of 2.4, 3.4, and 4.4 µm, the device is observed to exhibit a maximum drain current of 272, 235, and 221 mA/µm and the transconductance of 16.2, 14, and 12.3 mS/µm, respectively. It is established that a maximum drain current of 997 mA/µm can be achieved with an Al concentration of 23%, and the device exhibits a steady drain current with enhanced transconductance. These observations demonstrate tremendous potential for two-dimensional electron gas (2DEG) for securing of the normally-off mode operation. A suitable setting of gate length and other design parameters is critical in preserving the normally-off mode operation while also enhancing the critical performance parameters at the same time. Due to the normallyon depletion-mode nature of GaN HEMT, it is usually not considered as suitable for high power levels, frequencies, and temperature. In such settings, a negative bias is required to enter the blocking condition; however, in the before-mentioned normally-off devices, the negative bias can be avoided and the channel can be depleted without applying a negative bias. [ABSTRACT FROM AUTHOR]

This work proposes an static random access memory (SRAM) with column-based split cell-VSS (CS-CVSS), data-aware write-assist (DAWA), and enhanced read sensing margin in 28-nm FDSOI technology. The proposed CS-CVSS and DAWA techniques improve both half-selected (HS) static noise margin (SNM) and write margin. They also improve HS dynamic noise margin (HS-DNM) by leveraging write through virtual ground with reduced load in the proposed write port. The proposed 3T read port enhances sensing margin by minimizing read bitline leakage through negative gate-to-source voltage regardless of cell data. A 16-kb 9T SRAM test chip demonstrated the minimum operating voltage for write and read operations as 0.47 and 0.25 V, respectively. The minimum energy of 6.72 pJ is achieved at 0.5 V. [ABSTRACT FROM AUTHOR]

This article presents an ultralow power K-band frequency doubler operating under 0.4-V supply voltage. With 0-dBm input signal, the frequency doubler consumes 2.4 mW and achieves −8.4-dB conversion gain (CG). The measured saturated output power is −6 dBm at 23.6 GHz, and the 3-dB bandwidth is from 20.4 to 25.4 GHz. It exhibits up to 39-dB fundamental rejection (FR). The proposed differential frequency doubler operates at an ultralow supply voltage with ultralow power consumption in active frequency doublers. [ABSTRACT FROM AUTHOR]