Tuning of interface quality of Al/CeO2/Si device by post-annealing of sol-gel grown high-k CeO2 layers.

A comprehensive study has been done on the influence of post-deposition annealing temperature on high-k cerium oxide (CeO 2) layer grown on n-type silicon (Si) substrate and its resultant interface states have been studied for Al/CeO 2 /Si metal-oxide-semiconductor (MOS) devices. The high-k CeO 2 thin films were deposited by spin-coating and sintered at different annealing temperatures (T a) in the range of 400–900 °C. The parameters such as fixed charge density (Q eff), dielectric constant (k) of the layers, flat-band voltage (V FB), interface defect density (D it), etc., of the MOS device were evaluated from C V and I-V measurements. A minimum value of flat band shift (∼0.05 V) with lower Q eff (−4.81 × 1011 C/cm2) have been achieved for the T a of 600 °C. The k and D it were evaluated to be 22 and 1.29 × 1012 cm−2, respectively at the T a of 600 °C. In addition, the C V measurements showed a very small hysteresis and very low frequency dispersion for the T a of 600 °C sample. Energy distribution of defect states was evaluated and it was maximum towards the bottom of the conduction band. This shows that the 600 °C is the optimum annealing temperature, which results in high quality interface, and the electron affinity of the corresponding CeO 2 layers was found to be 3.29 eV as evaluated from ultraviolet photoelectron spectroscopy (UPS). Further, a maximum value of minority carrier lifetime (147 μs) has been achieved for the samples annealed at T a of 400 °C, indicating that the post-annealing temperature plays a significant role on the properties of CeO 2 films deposited by sol-gel process. Thus, the present study demonstrates the possibility of sol-gel grown high k-CeO 2 layers suitable for MOS like devices. [Display omitted] • High-k CeO 2 layers were successfully deposited on Si by spin coating method. • Energy distribution of defect states was maximum towards the bottom of the CB. • The electron affinity of the corresponding CeO 2 layers was found to be 3.29 eV. • Maximum minority carrier lifetime (147 μs) has been achieved for 400 °C annealed sample. • The MOS device with 600 °C annealed CeO 2 layer showed a small flat-band shift. [ABSTRACT FROM AUTHOR]