248 results on '"Lafferty, Neal"'
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2. Application-driven optimizations of metal stack and PDN (power delivery network) using machine learning framework
3. A novel flow of full-chip OPC model calibration and verification by utilizing SEM image contours
4. Advanced wafer engineering for minimizing overlay: tailoring and reducing wafer stress and distortion
5. A study of bitline contact process variation on DRAM performance and DVC/BVC failures using virtual fabrication
6. Cloud flight plan for post-tapeout flow jobs
7. A deep learning workflow to generate free-form masks for grayscale lithography
8. A machine learning approach towards SKILL code autocompletion
9. Inverse lithography mask design of displacement Talbot lithography enabled by optimization method
10. Using machine learning method to improve design sampling efficiency for fab applications
11. High accuracy OPC electromagnetic full-chip modeling for curvilinear mask OPC and ILT
12. Full-field correction for stitched double exposure high-NA EUVL processes
13. Improving line edge roughness using virtual fabrication
14. Enhancing lithography printability through deep generative models for layout re-targeting
15. Affordable optical proximity correction runtime for EUV curvilinear mask tape-out flow
16. Advances in full-chip three-dimensional resist modeling for low k1 EUV and DUV lithography
17. Improving OPC model accuracy of dry resist for low k1 EUV patterning
18. Using pattern analysis to improve process window qualification cycle time
19. Open-source differentiable lithography imaging framework
20. Prediction of etch bias using random forest model
21. NIL solutions using computational lithography for semiconductor device manufacturing
22. Tackling data inconsistency and runtime issues in inverse lithography technology (ILT) with comparative convergence study
23. Identification of key aberrations that affect pattern imaging in EUVL
24. Test pattern generation by conditional generative model labeled by image parameters
25. Pre-training CNN for fast EUV lithography simulation including M3D effects
26. Source mask optimization (SMO) study for high-NA EUV lithography to achieve single patterning on random logic metal
27. A fast and accurate PEB simulation through recurrent neural network
28. A transistor sizing method for standard-cell optimization considering lithography effects
29. Advanced device extraction and LVS (layout vs. schematic) with pattern matching applications
30. Synthesizing ILT MB-SRAF using machine learning
31. Investigation of die-cost scaling scenarios in future technologies
32. An artificial intelligence machine learning (AI/ML) approach with cross-technology node learning for multi-layer process defect predictions
33. Impact of mask rule constraints on ideal sraf placement
34. Application of resolution enhancement techniques at high NA EUV for next generation DRAM patterning
35. EUV full-chip curvilinear mask options for logic via and metal patterning
36. Patterning assessment using 0.33NA EUV single mask for next generation DRAM manufacturing
37. Single mask solution to pattern BLP and SNLP using 0.33NA EUV for next-generation DRAM manufacturing
38. Application of resolution enhancement techniques at high NA EUV for next generation DRAM patterning
39. Patterning assessment using 0.33NA EUV single mask for next generation DRAM manufacturing
40. EUV full-chip curvilinear mask options for logic via and metal patterning
41. Simultaneous source-mask-laser spectrum optimization
42. EUV based multi-patterning schemes for advanced DRAM nodes
43. Impact of mask rule constraints on ideal SRAF placement
44. CPU time prediction using machine learning for post-tapeout flow runs
45. Constructing layout hierarchy for high-efficiency OPC flow
46. Co-optimization of optical and resist models in the OPC modeling process using in-house genetic algorithm
47. Computational lithography solutions to support EUV high-NA patterning
48. Physical design level PPA evaluation of buried power rail at 2nm node
49. Lithography hotspot detection based on residual network
50. A geometric model for active contours in inverse lithography
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