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A novel RF switch branch design and layout is proposed to reduce on-state second harmonic nonlinearity. We have demonstrated a 2.5X reduction in the second harmonic power in RF-SOI and SiGe BiCMOS bulk technologies that serve the wireless front-end module market. The method can be easily incorporated into a traditional RF switch branch layout, incurring only a small area penalty.

This paper uses charge deposition by two-photon absorption to present the first investigation of the physical mechanisms underlying the single event transient (SET) response of cascode structures in a 45-nm RF-CMOS/SOI technology, provides the first experimental comparison of SET between 45-nm and 32-nm RF-CMOS/SOI devices, and presents implications for circuit design in both technologies. This work leverages a number of different device types and is supported by calibrated TCAD simulations.

The single-event effect sensitivity of fourth-generation, 90 nm SiGe HBTs is investigated. Inverse-mode, ≥1.0 Gbps SiGe digital logic using standard, unoptimized, fourth-generation SiGe HBTs is demonstrated and the inverse-mode shift register exhibited a reduction in bit-error cross section across all ion-strike LETs. Ion-strike simulations on dc calibrated, 3-D TCAD SiGe HBT models show a reduction in peak current transient magnitude and a reduction in overall transient duration for bulk SiGe HBTs operating in inverse mode. These improvements in device-level SETs are attributed to the electrical isolation of the physical emitter from the subcollector-substrate junction and the high doping in the SiGe HBT base and emitter, suggesting that SiGe BiCMOS technology scaling will drive further improvements in inverse-mode device and circuit-level SEE. Two-photon absorption experiments at NRL support the transient mechanisms described in the device-level TCAD simulations. Fully-coupled mixed-mode simulations predict large improvements in circuit-level SEU for inverse-mode SiGe HBTs in multi-Gbps, inverse-mode digital logic.

We use predictive technology computer-aided design to investigate the device design challenges and optimization issues that will be necessarily encountered in scaling of complementary silicon-germanium (C-SiGe) heterojunction bipolar transistors (HBTs). A fully integrated simulation framework was developed to design and optimize device doping and Ge profiles for any given target performance, using important circuit-relevant figures-of-merit. This methodology was successfully utilized to realize device profiles for multiple C-SiGe technology nodes within the context of a C-SiGe scaling roadmap. A method for optimizing the ac performance of SiGe HBTs geared for both high-performance and low-power applications is also presented. The performance metrics of the optimized profiles presented here are then compared with those of existing fabricated devices reported in the literature.

The single-event effect sensitivity of inverse-mode biased SiGe HBTs in both bulk and SOI technology platforms are investigated, for the first time, using digital circuits and stand-alone device test structures. Comparisons of heavy-ion broad beam data of shift register circuits constructed with forward-mode and inverse-mode biased SiGe HBTs from a first-generation, complementary SOI SiGe BiCMOS process, reveal an improvement in SEU mitigation for the inverse-mode shift register architecture. Full 3D TCAD simulations highlight the differences in transient current origination between forward and inverse-mode biased devices, illustrating the impact of doping profiles on ion-induced shunt duration. To extend the analysis to a bulk platform, new fourth-generation npn , SiGe HBTs were biased in both the forward and inverse-mode and irradiated at NRL using the two photon absorption measurement system. These measurements support the analysis of transient origination using 3D TCAD simulations. Furthermore, the isolation of the output terminal from the sensitive subcollector-substrate junction is experimentally demonstrated for the inverse-mode bias. Fully coupled mixed-mode simulations predict a significant reduction in sensitive area for inverse-mode shift registers built in a bulk SiGe platform.

We study mixed-mode stress degradation in SiGe HBTs using a novel physical TCAD model in which the processes of hot carrier generation within the semiconductor, carrier propagation to the oxide interface, and formation of interface traps are directly modeled. Transient degradation simulations using a calibrated 2-D SiGe HBT model correlate well with measured data. With this novel simulation tool, we investigate the bias dependence and location of interface traps and show that secondary holes produced by impact ionization are the dominant carrier to damage the emitter-base (EB) spacer oxide interface, confirming previously reported results. We also compare in detail trap formation at the EB spacer and shallow-trench-isolation (STI) oxide interfaces as a function of time and stress condition. At the STI oxide interfaces, we find that hot electrons and holes each dominate trap formation in different regions, and the hot carriers that reach the STI predominately originate outside of the selectively implanted collector, revealing the important role played by dopant diffusion from the extrinsic base of quasi-self-aligned SiGe HBTs.

Improvements in foundry RF and mm-wave Si offerings over the last several years have allowed it to take market share from III-V processes for TX / RX applications. The increased RF switch content in handsets is now dominated by RF-SOI which also supports LNA and PA integration. SiGe BiCMOS technologies support the 802.11 FEIC and GPS receiver IC products and may be poised to take a larger share of the cellular PA market in the coming years. Higher-speed, high yielding SiGe BiCMOS is enabling new building blocks such as single-chip 60 GHz phased arrays. Here we review recent improvements in key technology figures of merit and integration that are driving the increased use of RF specialty silicon for high performance wireless and wireline communications.

Single-event transient (SET) simulations of a Gb/s SiGe BiCMOS master/slave D flip-flop circuit are performed, employing both a decoupled current-injection SET modeling technique and a fully-coupled mixed-mode TCAD technique to model heavy-ion strikes to the storage and input cells. New insights are provided into the physical mechanisms underlying the single-event upset (SEU) sensitivity of high-speed SiGe digital latches and shift registers. A close analysis of the transient circuit behavior identifies the limitations of the current-injection approach in predicting SEU in fast SiGe digital logic. Furthermore, the physical ion track linear energy transfer (LET) is varied to establish the threshold LET for SEU using each simulation technique, further highlighting the SEU prediction error inherent to conventional decoupled modeling approaches. Finally, clocked mixed-mode circuit simulations are used to explain the fundamental SEU mechanisms and relate them to corresponding regions of the device-level SET.

SOI processes have become the mainstream technology for wireless front end manufacturing following recent optimization of starting materials and fabrication processes. In this paper, we will describe such RFSOI platform for RF switches, the process optimizations and the devices offering required for efficient FEM design.

Single-event transients (SETs) are modeled in a SiGe voltage reference using compact model and full 3-D mixed-mode TCAD simulations. The effect of bias dependence and circuit loading on device-level transients is examined with regard to the voltage reference circuit. The circuit SET simulation approaches are benchmarked against measured data to assess their effectiveness in accurate modeling of SET in SiGe analog circuits. The mechanisms driving the SET of this voltage reference are then identified for the first time and traced back to the original device transients. These results enable the differences between the simulation results to be explained, providing new insight into best practices for the modeling circuit SET in different circuit topologies and device technologies.

An investigation of the performance and reliability issues associated with operating silicon–germanium (SiGe) devices and circuits at temperatures up to 300 °C is presented, along with a new bypass compensation technique for optimizing bandgap reference performance at these extreme temperatures. In addition to the device-level characterization of a SiGe BiCMOS platform, improved circuit design and a device-level collector–substrate leakage suppression technique are shown to improve the viability of SiGe bandgap reference (BGR) circuits on low-cost, bulk Si wafers for high temperature applications. A shunting technique using various transistors to further improve BGR performance above 200 °C is presented, and optimized compensation designs predict new performance records for a bulk-silicon based technology across temperatures from −200 °C to 300 °C. Finally, a closely-related SiGe temperature sensor circuit is characterized for operating environments up to 300 °C.

Comprehensive 3-D mixed-mode simulations, including accurate modeling of parasitic elements present in the experimental setup, resulted in close agreement between simulated and experimentally-measured heavy-ion-induced transients in first-generation SiGe HBTs. We have identified the key factors affecting previous simulations and observed experimental differences. The approach employed is also applicable to other submicron, high-speed technologies. Furthermore, we present a plausible answer to the previously unexplained issue of higher collector currents in single-transistor SiGe HBT single-event transients under positive collector bias. The new observations and conclusions facilitate improved understanding and potential mitigation options.

We present a measured current-mode logic ring oscillator gate delay of 2.3 ps, a record for digital circuits in silicon-based technologies. This result was achieved in a silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technology operating at 25 K. In addition to higher cutoff frequency and lower collector-base capacitance, lower base resistance is also responsible for the improved switching speed at cryogenic temperatures. The self-heating characteristics of these SiGe HBT circuits are also investigated across temperatures.

We present experimental data and theoretical models that characterize the temperature-dependent behavior of key carrier-transport parameters in a commercial SiGe BiCMOS technology down to cryogenic temperatures and under exposure to ionizing radiation. The theoretical temperature and injection dependencies of Shockley-Read-Hall recombination lifetimes are examined, and experimental measurements of minority carrier lifetime in the substrate are presented. The experimental results are used to develop calibrated theoretical models for use in technology computer-aided design (TCAD). Similarly, the temperature-dependent resistivity is examined, addressing the prevailing theoretical models for both carrier mobility and incomplete ionization of dopants. Experimental measurements of the temperature dependence of resistivity in the p- and n-type regions of a SiGe BiCMOS technology are presented, and calibrated TCAD-relevant models for carrier mobility and incomplete ionization are developed.

Silicon-germanium heterojunction bipolar transistor (SiGe HBT) heavy ion-induced current transients are measured using Sandia National Laboratories' microbeam and high- and low-energy broadbeam sources at the Grand Acce?le?rateur National d'Ions Lourds, Caen, France, and the University of Jyva?skyla?, Finland. The data were captured using a custom broadband IC package and real-time digital phosphor oscilloscopes with at least 16 GHz of analog bandwidth. These data provide detailed insight into the effects of ion strike location, range, and LET.

We investigate the single-event transient (SET) response of bandgap voltage references (BGRs) implemented in SiGe BiCMOS technology through heavy ion microbeam experiments. The SiGe BGR circuit is used to provide the input reference voltage to a voltage regulator. SiGe HBTs in the BGR circuit are struck with 36-MeV oxygen ions, and the subsequent transient responses are captured at the output of the regulator. Sensitive devices responsible for generating transients with large peak magnitudes (more than 5% of the dc output voltage) are identified. To determine the effectiveness of a transistor-layout-based radiation hardened by design (RHBD) technique with respect to immunity to SETs at the circuit level, the BGR circuit implemented with HBTs surrounded by an alternate reverse-biased pn junction (n-ring RHBD) is also bombarded with oxygen ions, and subsequent SETs are captured. Experimental results indicate that the number of events causing transients with peak magnitude more than 5% above the dc level have been reduced in the RHBD version; however, with the inclusion of the n-ring RHBD, new locations for the occurrence of transients (albeit with smaller peak magnitude) are created. Transients at the transistor-level are also independently captured and are presented. It is demonstrated that while the transients are short at the transistor level (ns duration), relatively long transients are obtained at the circuit level (hundreds of nanoseconds). In addition, the impact of the SET response of the BGR on the performance of an ultra-high-speed 3-bit SiGe analog-to-digital converter (ADC) is investigated through simulation. It is shown that ion-induced transients in the reference voltage could eventually lead to data corruption at the output of the ADC.

In this paper, we investigate the physics and modeling of temperature dependence of various parasitic resistances in SiGe heterojunction bipolar transistors down to 30 K. Carrier freezeout is shown to be the dominant contributor to increased resistances at cryogenic temperatures for lightly-doped and moderately-doped regions, whereas the temperature dependence of the mobility is the dominant contributor to the temperature dependence of heavily-doped regions. Two incomplete ionization models, the classic model with a doping dependent activation energy and the recent model of Altermatt , are shown to underestimate and overestimate incomplete ionization rate below 100 K for intrinsic base doping, respectively. Analysis of experimental data shows that the bound state fraction factor is temperature dependent and including this temperature dependence enables compact modeling of resistances from 30 to 300 K for moderately-doped regions. For heavily-doped regions, a dual power law mobility approximation with complete ionization is shown to work well down to 30 K. An alternative approach is also presented for heavily-doped resistors which allows one to use the same model equation for all regions.

We present the first experimental results confirming the increased SEE sensitivity of SiGe digital bipolar logic circuits operating in a 63 MeV proton environment at cryogenic temperatures. A 3× increase in both the error-event and bit-error cross sections is observed as the circuits are cooled from 300 K to 77 K, with error signature analyses indicating corresponding increases in the average number of bits-in-error and error length over data rates ranging from 50 Mbit/s to 4 Gbit/s. Single-bit-errors dominate the proton-induced SEU response at both 300 K and 77 K, as opposed to the multiple-bit-errors seen in the heavy-ion SEU response. Temperature dependent substrate carrier lifetime measurements, when combined with calibrated 2 D DESSIS simulations, suggest that the increased transistor charge collection at low temperature is a mobility driven phenomenon. Circuit-level RHBD techniques are shown to be very efficient in mitigating the proton- induced SEU at both 300 K and 77 K over the data rates tested. These results suggest that the circuit operating temperature must be carefully considered during component qualification for SEE tolerance and indicate the need for broad-beam heavy-ion testing at low temperatures.

We present the first measurement results for silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) and SiGe BiCMOS circuits operating in the sub-1-K regime. Robust transistor operation of a first-generation 0.5 times 2.5 times 4-mum2 SiGe transistor is demonstrated at package temperatures as low as 300 mK. In addition, a SiGe BiCMOS bandgap voltage reference is verified to be fully functional at operating temperatures below 700 mK. The SiGe voltage reference exhibits a temperature coefficient of 160 ppm/degC over the temperature range of 700 mK-300 K.

The total ionizing dose and laser-induced transient response of a new 4th generation 90 nm IBM SiGe 9HP technology are investigated. Total dose testing was performed with 63.3 MeV protons at the Crocker Nuclear Laboratory at the University of California, Davis. Transient testing was performed on the two-photon absorption system at Naval Research Laboratory. Results show that the SiGe HBTs are dose-tolerant up to 3 Mrad(SiO2) and exhibit reduced single event transients compared to earlier SiGe generations.

We investigate, for the first time, predictive TCAD modeling of scaling-induced, reverse-biased emitter-base junction tunneling current in state-of-the-art SiGe HBTs. Different operative tunneling mechanisms are identified, including important factors that determine the accuracy of the simulations. The models for different tunneling mechanisms are applied to multiple generations of SiGe HBTs to examine their validity. Implications of these results and their use in TCAD-based device optimization are discussed. Finally, this study highlights the nature of the emitter-base junction degradation that results from an accelerated stress in the tunneling regime for different generations of SiGe HBTs.

We present here wide temperature range compact modeling of Silicon-Germanium heterojunction bipolar transistors (SiGe HBTs) based on Most EXquisite TRAnsistor Model (Mextram). Various modifications and extensions are made to enable modeling of DC characteristics from 43–393 K, and AC characteristics from 93–393 K.

We investigate the efficacy of mitigating radiation-based single event effects (SEE) within circuits incorporating SiGe heterojunction bipolar transistors (HBTs) built with an N-Ring, a transistor-level layout-based radiation hardened by design (RHBD) technique. Previous work of single-device ion-beam induced charge collection (IBICC) studies has demonstrated significant reductions in peak collector charge collection and sensitive area for charge collection; however, few circuit studies using this technique have been performed. Transient studies performed with Sandia National Laboratory's (SNL) 36 MeV 16O microbeam on voltage references built with N-Ring SiGe HBTs have shown mixed results, with reductions in the number of large voltage disruptions in addition to new sensitive areas of low-level output voltage disturbances. Similar discrepancies between device-level IBICC results and circuit measurements are found for the case of digital shift registers implemented with N-Ring SiGe HBTs irradiated in a broadbeam environment at Texas A&M's Cyclotron Institute. The error cross-section curve of the N-Ring based register is found to be larger at larger ion LETs than the standard SiGe register, which is clearly counter-intuitive. We have worked to resolve the discrepancy between the measured circuit results and the device-level IBICC measurements, by re-measuring single-device N-Ring SiGe HBTs using a time-resolved ion beam induced charge (TRIBIC) set-up that allows direct capture of nodal transients. Coupling these measurements with full 3-D TCAD simulations provides complete insight into the origin of transient currents in an N-Ring SiGe HBT. The detailed structure of these transients and their bias dependencies are discussed, together with the ramifications for the design of space-borne analog and digital circuits using SiGe HBTs.

We investigate the single-event transient (SET) response of T-body and notched-body contacted MOSFETs from a commercial 45 nm SOI RF-CMOS technology. Although body-contacted devices suffer from reduced RF performance compared to floating body devices, previous work on 65 nm and 90 nm MOSFETs has shown that the presence of a body-contact significantly mitigates the total ionizing dose (TID) sensitivity that is exhibited in floating-body SOI MOSFETs. The influence of body-contacting schemes on the single-event effect (SEE) sensitivity is examined here through time-resolved measurements of laser and microbeam-induced transients from T-body and notched-body MOSFETs. Laser-induced transients demonstrate the reduced SEE sensitivity of the notched-body MOSFETs as compared to the T-body MOSFETs; this is evidenced by a uniform reduction in the peak transient magnitudes and collected charge for transients captured at the worst-case bias of VDS = 1.0 V, as well as with all terminals grounded. Microbeam-induced transient data are also presented to support the validity of the laser-induced transient data. Together, these data provide new insight into the RF versus TID versus SEE tradeoffs associated with body contacting schemes in nm-scale MOSFETs, an important concern for emerging space-based electronics applications.

We investigate, for the first time, the electro-thermal stability of 150 GHz SiGe HBTs that were optimized for bulk-Si and then fabricated on SOI substrates to enable a direct comparison. AC, DC and pulsed measurements are used to characterize the devices and study the onset of electro-thermal instabilities. Implications of electro-thermal feedback induced instabilities resulting from self-heating are discussed, along with consequent electrical biasing constraints imposed on the device. Figures-of-merit are proposed as effective tools for comparing devices with strong self-heating effects. TCAD is used to predict the implications for performance scaling and BiCMOS technology development for SiGe on SOI platforms.

A new method for two-dimensional (2-D) regional transit time analysis in SiGe HBTs is presented, using a commercially-available TCAD suite with hydrodynamic device simulations. The quasi-static 2-D transit time analysis is first used to determine the cutoff frequency of a well-calibrated 200 GHz SiGe HBT and then applied to the design of hypothetical SiGe HBTs with peak cutoff frequencies of 375 GHz and 450 GHz. These results are benchmarked against full frequency-domain simulations. The new regional analysis is then demonstrated at each scaling node and used to illuminate the 2-D nature of the onset of the Kirk effect and heterojunction barrier effect. These techniques enable the cutoff frequency and transit time components to be determined at lower computational complexity and in greater detail than traditional frequency-domain simulations, and are very useful for optimized scaling.

We report the hot carrier reliability (HCR) of 45-nm SOI CMOS technology. Body contacted devices are shown to be more reliable than floating-body devices. Two different body-contacting schemes are investigated (T-body and notched T- body). The effects of total dose irradiation on reliability are investigated. Body contacted devices are shown to be more tolerant to radiation than floating-body devices. Asymmetric halo doping devices show less hot carrier degradation than symmetric halo doping devices. In addition, we investigate the dependence of hot carrier reliability on the metal contact spacing of the Source/Drain (S/D) terminals, the PC-PC spacing, and the RF device performance trade-offs that result.

A new method is introduced to investigate electron transport in the collector-base space charge region of SiGe HBTs designed for half-Terahertz speeds. Using commercially-available Monte Carlo and hydrodynamic TCAD tools, one can eliminate the fundamental limitations of hydrodynamic models related to velocity overshoot and impact ionization. The method is verified in a 200-GHz SiGe technology and then applied to hypothetical 350-GHz and half-THz (500 GHz) SiGe HBTs. This new approach requires far less computational complexity than classical Monte Carlo tools.

Complementary bipolar technology (npn + pnp BJTs) has long been considered the “gold-standard” for analog applications requiring high speed, low noise, high bandwidth, large voltage swing, and large output drive [1, 2]. Bandgap-engineered complementary SiGe (C-SiGe) HBTs can provide significant leverage in the multiple tradeoffs involved in designing npn and pnp BJTs with matched performance (e.g., comparable f T ). However, the inherent minority carrier transport issues associated with the pnp SiGe HBT device design need to be carefully addressed in order to successfully scale C-SiGe HBT technology for higher frequency operation [3, 4]. This TCAD-based investigation presents for the first time a comprehensive study of the device design challenges and optimization issues which will be necessarily encountered in scaling C-SiGe HBTs for high-performance analog applications.