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Pulse height measurement is one of the most important step in ionizing radiation spectroscopy . However, the conventional analog and digital peak detection methods may be limited due to their high complexity and cost. In this work, a simple and novel mathematical approach based on Lagrange interpolation has been developed to precisely extract pulse height from a sequence of samples recorded at a low rate (2 MS/s). This has been implemented in an ARM-based micro-controller to construct a full functionality multi-channel analyzer. The results showed that the multi-channel analyzer has a very good integral linearity response (

We have tested two digital spectrometer systems, the DSP 9660 and Lynx ® modules, connected to a HPGe detector. Lynx ® is a fully integrated 32 K channel signal analyzer based on digital signal processing techniques, which offers advanced digital stabilization. The model DSP 9660 digitalizes the signal directly at a very high sampling rate. The evaluated properties were integral nonlinearity, differential linearity, channel profiles, resolution and throughput. We found that the DSP system has slightly inferior resolution and throughput in comparison with the Lynx ® system.

To calibrate the energy response of the ATLAS liquid argon calorimeter, an electronics calibration board has been designed; it delivers a signal whose shape is close to the calorimeter ionization current signal with amplitude up to 100 mA in 50 Ω with 16 bit dynamic range. The amplitude of this signal is designed to be uniform over all calorimeters channels, stable in time and with an integral linearity much better that the electronics readout. The various R&D phases and most of the difficulties met are discussed and illustrated by many measurements. The custom design circuits are described and the layout of the ATLAS calibration board presented. The procedure used to qualify the boards is explained and the performance obtained illustrated: a dynamic range up to 3 TeV in three energy scales with an integral linearity better than 0.1% in each of them, a response uniformity better than 0.2% and a stability better than 0.1%. The performance of the board is well within the ATLAS requirements. Finally, in situ measurements done on the ATLAS calorimeter are shown to validate these performances.

The original digital calibration approach for 1 b/stage and 1.5 b/stage pipeline analog-digital converters produces missing or nonmonotonic digital codes with the device and circuit impairments typical of modern deep submicrometer CMOS technologies. Two digital calibration algorithms are introduced to improve pipeline performance when using low-voltage low-gain nonlinear operational amplifiers and high random dc offset voltage comparators. The first technique computes calibration coefficients for each stage at actual transition points of the residue characteristic to assure converter monotonicity in the presence of random comparator offset voltages. The second augments a conventional pipelined architecture with an input-dependent level-shifting stage and additional digital calibration circuitry to achieve high differential and integral linearity with low-gain nonlinear operational amplifiers.

A compact 10-bit current-steering D/A converter in a 0.35 μm CMOS technology is presented. The DAC is designed for active pixel sensor control of a retinal implant. A new current cell has been used to minimize power consumption and reduce glitching. To guarantee monotonicity and to achieve good dynamic and static performance a segmentation level of 4–6 has been used. A triple common-centroid layout technique has been applied and an active area of 0.7 mm2 has been used. The measured differential and integral linearity errors are less than ± 0.2 LSB and ± 0.3 LSB, respectively.

A new design of a time-to-digital converter (TDC) implemented on an FPGA chip with amorphous antifuse structures is presented. Time coding with 200-ps resolution (LSB), 10-ns range, and very short conversion time is realized by two tapped delay lines working in-a differential mode. Thanks to the local feedback loops, the output from the delay line is obtained directly in "1-out-of-N" code and then converted to 6-bit natural binary. Within the temperature range from 0/spl deg/C to 45/spl deg/C, the time offset at the output is constant, the resolution changes by /spl plusmn/0.02 LSB, and the offset-corrected integral linearity error is less than 1 LSB.

We have developed a new position sensing method that can obtain position information directly from the pulse shape of a position-sensitive proportional counter (PSPC). A digital signal processing technique and a neural network algorithm have been used to recognize the pulse shapes and to obtain position information. The method has been applied to a one-sided read-out type PSPC where the pulse shapes depend strongly on the position of radiation interactions. The neural network can recognize the pulse shapes and provide the proper position even for positions that have not been taught in the learning process. The best relative position resolution is 6.4 × 10 −3 . Fairly good integral linearity has been obtained throughout the effective length of the PSPC.

A low-voltage, high-speed, and high-resolution CMOS D/A converter is implemented using an improved unique switching sequence to reduce integral linearity error (ILE) in the output of current cells, and a novel segmented layout technique to minimize both current asymmetry due to drain current directions and voltage drop due to power line resistance. The D/A converter has been fabricated by using 0.65 /spl mu/m CMOS process. The differential linearity error (DLE) is 0.37 LSB and the ILE is 0.87 LSB. It occupies a die area of 700/spl times/800 /spl mu/m/sup 2/ and operates up to 80 MHz with 3.O V.

A low glitch 10-bit 75-MHz CMOS current-output video digital-to-analog Converter (DAC) for high-definition television (HDTV) applications is described. In order to achieve monotonicity and low glitch, a special segmented antisymmetric switching sequence and an innovative asymmetrical switching buffer have been used. The video DAC has been fabricated by using 0.8 /spl mu/m single-poly double-metal CMOS technology. Experimental results indicated that the conversion rate is above 75 MHz, and nearly 50% of samples have differential and integral linearity errors less than 0.24 LSB and 0.6 LSB, respectively. The glitch has been reduced to be less than 3.9 pV/spl middot/s and the settling time within /spl plusmn/0.1% of the final value is less than 13 ns. The video DAC is operated by a single 5 V power supply and dissipates 1.70 mW at 75 MHz conversion rate (140 mW in the DAC portion). The chip size of video DAC is 1.75 mm/spl times/1.2 mm (1.75 mm/spl times/0.7 mm for the DAC portion). >

This paper describes a 10-b high-speed COMS DAC fabricated by 0.8-/spl mu/m double-poly double-metal CMOS technology. In the DAC, a new current source called the threshold-voltage compensated current source is used in the two-stage current array to reduce the linearity error caused by inevitable current variations of the current sources. In the two-stage weighted current array, only 32 master and 32 slave unit current sources are required. Thus silicon area and stray capacitance can be reduced significantly. Experimental results show that a conversion rate of 125 MHz is achievable with differential and integral linearity errors of 0.21 LSB and 0.23 LSB, respectively. The power consumption is 150 mW for a single 5-V power supply. The rise/fall time is 3 ns and the full-scale settling time to /spl plusmn/1/2 LSB is within 8 ns. The chip area is 1.8 mm/spl times/1.0 mm. >

This paper describes a 5 ns settling time digital-to-analog converter device, which has been designed for use in video speed successive approximation analog to digital converters. The chip includes a precision reference source with a 25 ppm per degree C average temperature coefficient and a high-speed comparator. The successive approximation approach, restricted to low-speed converters until now, has the advantages of low cost and straightforward drive requirements. The achievement of the operating speeds described is dependent both on the circuit techniques used and the process employed. The DAC circuit, unlike most other devices, uses a multiple-matched current source array technique, which leads to a very linear, low glitch output. Without any form of trimming, most functional devices meet a ???? L.S.B. differential and integral linearity specification, and many are ???? L.S.B. or better.

Position-sensitive detectors are a vital research tool in many areas of structural and molecular biology and condensed matter physics. The present review is mainly restricted to structural information obtained by X-ray scattering and diffraction and in DNA sequence analysis using autoradiography. Film has traditionally played the most important role, and for many applications is still the best medium for recording data, but advances in various types of detector technology has made them attractive, and in some cases essential alternatives. The requirements imposed by experiments vary a great deal and can be very demanding in terms of detector performance, e.g. in terms of count rates, particularly for synchrotron radiation, dynamic range, spatial resolution, ability to do time-resolved measurements on a millisecond time scale, differential and integral linearity and resistance to radiation damage. A brief review of detector properties will be presented and how they are matched in different cases with the experimental requirements along with a small selection of recent results and what new developments are needed to cope with the new generation of storage rings now under construction.

A simple, nearly passive circuit for programmable gain control of charge-domain signals is described. The circuit is functionally equivalent to a multiplying digital-to-analog converter (MDAC) and is implemented in a 3- mu m double-poly, double-metal charge-coupled device (CCD) process. Two implementations of the circuit are reported: a single-stage recursive converter, and a ten-stage pipeline converter. The latter occupies 0.4 mm/sup 2/ of chip area and consumes approximately 2 mu W for a 1-kHz conversion rate. The circuit is shown experimentally to have all 8-b equivalent accuracy in both differential and integral linearity and is expected to find application in focal-plane image processing for both detector nonuniformity correction and convolution weighting. >

A 10-b 70-MS/s CMOS D/A converter fabricated in a 1- mu m CMOS technology is described. An integral linearity error caused by error distributions of current sources is reduced by a new switching sequence called hierarchical symmetrical switching. A differential linearity error caused by an off-axis drain-source implantation is reduced by the layout technique of current sources. The D/A converter is fabricated by using a single-polycide double-metal standard digital process. Both the integral and the differential linearity errors are less than +or-0.5 LSB. The settling time to +or-0.1 % is less than 14 ns. The worst-case glitch energy is approximately 60 pV-s. This D/A converter has a single power supply of 5 V and dissipates 170 mW at 70 MS/s. The chip size is 2.02 mm*1.87 mm. >

In this article we present a programmable current source architecture based on nine bits to modulate the charge quantity injected in the cochlear nerve ending. Our architecture is designed from a portable system to cochlear implant. In fact, the proposed architecture must be flexible and allows a transparency via the stimulation algorithms in order to satisfy the different pathological cases. The architecture which based on thermometer digital to analog converter presents a good linearity. As well, it is capable to generate a maximum current about 1 mA through a 1 KOmega [1, 2] load, which is around the typical nerve impedance. The DAC currents sources have been seized to minimize power consumption, to reduce silicon occupation and to offer a worse case error around 0.08LSB differential linearity error and 0.4LSB integral linearity. This device is designed with a 0.35mum CMOS technology.

A 1.8 V, 10-Bit, 40-MS/s pipeline analog-to-digital converter designed using 0.18-mum CMOS technology is presented. The new structure of the A/D converter is based on double sampling and averaging techniques. By the first technique, all the stage amplifiers are active at the both sampling and holding cycles. Averaging as the second technique minimizes the capacitance mismatch and exchanges the priority of input-referred noise and capacitance mismatch in the selection of the stage caps. The converter achieved a peak spurious-free-dynamic-range of 61 dB, maximum differential nonlinearity 0.5 of least significant bit (LSB), maximum integral linearity of 0.9 LSB, and power consumption of 5 mW

A novel, on-chip transfer function calibration scheme is introduced to the classical resistor string DAC architecture. A 16-bit, quad channel, resistor string DAC with exceptional accuracy is fabricated on an ultra-low-cost, 0.5mum, 5V CMOS process. Monotonicity is achieved by voltage interpolation and absolute accuracy errors are improved by 100times using full transfer function calibration at final test. An on-chip arithmetic logic unit (ALU) linearly interpolates calibration coefficients saving memory, and a high-effective-resolution cal-DAC preserves differential linearity (DNL) performance while correcting integral linearity errors. Separate cal-DACs correct for offset and gain errors. Each DAC channel occupies 4mm2 die area, consumes 750muA, and settles in 10mus, while offering up to +/- 500muV absolute accuracy across its transfer curve. The chip has built-in DFT and uses one time programmable memory with read-back. The device can be calibrated and tested with a single insertion at final test. This paper discusses the architecture, testing, calibration and optimization details

This paper presents a 10-bit programmable biphasic current-source, which is based on a digital to analog converter (DAC). In order to achieve high accuracy, a current-cell matrix configuration and a switching sequence in a code thermometer have introduced. To minimise the area of the DAC, a two matrix of a same current-cell are used. In this case an only 62 same current-cell are used instead to 1023 for a 10-bit thermometer-code-based DAC architecture. The simulation results have shown that the differential and the integral linearity errors are respectively 0.21 LSB and 0.35 LSB. The biphasic current sources present a good linearity and are capable of generating a maximum current of 1.050 mA through a 1 K/spl Omega/ load, which is around the typical nerve impedance. This device is designed in a 0.35-/spl mu/m CMOS technology. The maximum power consumption is 38 mW and the chip size is 175/spl times/290 /spl mu/m/sup 2/.

An opto-coupling circuit based on the Siemens IL300 linear optocoupler and the methods to assess its static and dynamic performances are presented. It is shown that IL300, due to its built-in linearizing feedback photodiode, makes it possible to build coupling schemes that associate good linearity with the inherent properties of optical devices, as true galvanic isolation, high isolation voltage and transmission down to DC. The integral linearity, 0.029%, obtained on the coupling of typical nuclear spectroscopy pulses makes us believe that traditional capacitive coupling used in nuclear spectroscopy circuits can be replaced by optical coupling in the near future.

As the performance of Analog-to-Digital Converters continues to improve, it is becoming more challenging and costly to develop sufficiently fast and low-drift signal generators that are adequately more linear than the ADC for the purpose of linearity testing. This work relaxes the linearity requirements on the signal generators used for ADC testing by alternatively employing multiple non-linear inputs. Assuming minimal prior knowledge of the input non-linearity, a testing methodology is introduced that is based upon first identifying and computationally removing the source non-linearity and then accurately estimating the ADC linearity. Production test hardware is used for validating the performance of this testing methodology using a high performance 16-bit SAR ADC as a test vehicle. Integral linearity error readings are identified to well within the +/-2 LSB range of the device specification by using only 8-bit linear inputs. This approach provides an enabling technology for costeffective full-code testing of high performance ADCs in production test and for a cost-effective implementation of built-in self-test (BIST).

A hybrid GaAs 3-gigasample-per-second (Gs/s) digital-to-analog converter (DAC) is presented. Five-bit 1-Gs/s operation and peak operating speeds of 3 Gs/s are demonstrated. DC differential and integral linearity are shown to be consistent with 6-bit operation. Sub-500-ps settling times are demonstrated at operating speeds of 1-3 Gs/s. The device has ECL (emitter-coupled logic) level differential inputs and is capable of producing a 1-V output when driven into 50 Omega . The hybrid DAC is implemented with thin-film resistors and commercially available GaAs MESFETs. Power dissipation is approximately 1.5 W. The device has applications in telecommunications, microwave digitally programmable waveform generation, and very-high-resolution graphics display systems. >

A 10-b video CMOS D/A converter for low supply voltage has been developed. Nonsaturating transistors and a new switching scheme are introduced to current sources in the D/A converter, which operates at 50 MS/s with a 2.7 V power supply. Integral linearity error and differential linearity error are less than 0.5 LSB and 0.25 LSB, respectively. The dependence of the linearity error on full-scale voltage is plotted. Device characteristics are summarized. >

The methodology of analog-to-digital (ADC) testing is different from that of digital-to-analog converter (DAC) testing. Understanding a general, all purpose ADC can help us understand all testing requirements. In a 3-bit ADC transfer diagram, there are eight output codes. This chapter illustrates the various procedures of offset measurement. The linearity test overview is explained with the help of various parameters like differential linearity and integral linearity. When the digital output codes have gaps, they are said to have a “missing code.” A histogram can also be used to test DC linearity. It has been noticed that there is a direct correlation between the numbers of events in a histogram and the amount of differential nonlinearity (DNL) error seen for that bit. Different kinds of waveforms are used for the histogram test method. The “segmented ramp” technique is also used along with the histogram test method. In testing, understanding the conversion time is also important. Harmonic distortion tests are used to test the impact of errors. Effective number of bits (ENOBS) presents a way of calculating the ratio of the signal energy to the noise energy.

A compact, low power (2 W) electronic system which delivers all the high voltages required for portable gas proportional scintillation counters and has an optically coupled amplification output stage is described in detail. Its measured integral linearity is better than 0.0175% (rms). X-ray spectra demonstrating the performance of system are presented.

One of the most significant types of error in Digital Signal Processing (DSP) systems working with wideband signals is the error introduced by the Analog-to-Digital Converter (ADC). This paper investigates an accurate, simple and low cost method, which can be used for calibrating, testing and quick monitoring ADC. The proposed method analyzes the deviation of a value of the converted signal, which is similar to the ADC working signal, from its true value. The deviation represents the tested ADC error evaluated for both frequency and voltage ranges of ADC operations using statistical data processing. It gives the only necessary ADC accuracy characteristic to a user leaving the rest to the designer. Comparisons between the proposed ADC testing approach and the known techniques are provided. The errors incurred by the method are analyzed. A special source of random signal with controlled statistical parameters and its calibration technique are also described.

Mixed signals IC test generally requires the accurate analog measurement and/or the controlled interaction of digital function and analog measurement. The advanced mixed signals tester must provide the capability to control various test resources with synchronized/asynchronized timing in a real-time manner. This architectural concept contributes the accurate and repeatable testing of mixed signals IC with fast test throughput. For example, the integral linearity test of high resolution ADC is demonstrated by the sophisticated code measurement technique 10 times faster than the traditional analog measurement method by u-processor based control. Furthermore, the real-time DSP capability by the localized processors on the test resources under the sequence and timing control enables tester to emulate the complex mixed signals action such as communication devices. This makes the complex mixed signals testing much easier, more accurate and much faster for the following test using the DSP programming test condition, bit error rate test of modem, the 2B1Q Signal Generation with the specified jitter, and the vector error test, and so on. >

Peak extractor circuits are an important link in most pulse-height analysis systems. A novel architecture with performance exceeding previous state-of-the-art designs is presented. A droop rate ranging from 125 mu V/ mu s and a charge injection of 5 mV are reported along with a 2.2 MHz bandwidth, a 38 V/ mu s slew rate, and integral nonlinearity of 50 PPM. The low droop rate allows temporary storage of the signal in an analog FIFO (first-in first-out) with minimal peak broadening, suitable for high-resolution low-energy X-ray analysis. This configuration has been implemented in an analog-to-digital converter system using the peak-detect and hold circuit architecture. The complete system had a differential linearity of 1.5% at 64 K conversion gain, an integral linearity of +or-0.016%, and an effective conversion time of 1.9 mu s for a count rate of 210000 C/s to the input of a pulse processor producing 3- mu s-wide pulses. >

A 12-b switched-capacitor (SC) pipelined A/D converter has been developed in the framework of the CERN LAA project for particle physics detector R&D. The integral linearity of the converter is improved by an autocalibration cycle compensating the ratio error between two nominally identical capacitors. The circuit has been manufactured using a low-voltage 3- mu m CMOS technology. The active chip area including registers and clocking circuitry is 5.25 mm/sup 2/. Experimental results indicate 11-b resolution for 1-MHz sampling frequency, with only 6-mW power consumption. >

An innovative dual-input multichannel analyzer purposely designed for the diagnosis of cardiac and pulmonary diseases using the dual isotope technique has been realized and tested. Its main features are: two independent inputs; medium (1024 channels) resolution, large onboard memory so that up to 128 spectral pairs can be stored, small size and weight, programmable measure and wait times, programmable HV or bias supply for the detectors, local and remote programmability and large autonomy with the on board battery. The instrument is based upon a microcontroller with a multiplexed A/D converter with 10-bit resolution. The integral and differential linearity and the conversion time were proved to be adequate for the application by comparing the recorded spectra with the output of a research grade multichannel analyzer. In order to show the feasibility of the dual isotope technique, spectra from different radioactive sources and detectors are reported.

Many scientific instruments utilise multiple element detectors, e.g. CCD's or photodiode arrays, to monitor the change in a position of an optical pattern. For example. instruments for affinity biosensing based on surface plasmon resonance (SPR) or resonant mirror are equipped with such detectors. An important and desired property of these bioanalytical instruments is that the calculation of the movement or change in shape follows the true change. This is often not the case and it may lead to linearity errors, and to sensitivity errors. The sensitivity is normally defined as the slope of the calibration curve. A new parameter is introduced to account for the linearity errors, the sensitivity deviation, defined as the deviation from the undistorted slope of the calibration curve. The linearity error and the sensitivity deviation are intimately related and the sensitivity deviation may lead to misinterpretation of kinetic data, mass transport limitations and concentration analyses. Because the linearity errors are small (e.g. 10 pg/mm2 of biomolecules on the sensor surface) with regard to the dynamic range (e.g. 30,000 pg/mm2), they can be difficult to discover. However, the linearity errors are often not negligible with regard to a typical response (e.g. 0-100 pg/mm2). and may therefore cause serious problems. A method for detecting linearity errors is outlined. Further on, this paper demonstrates how integral linearity errors of less than 1% can result in a sensitivity deviation of 10%, a value that in our opinion cannot be ignored in biospecific interaction analysis (BIA). It should also be stressed out that this phenomenon also occurs in other instruments using array detectors.

A fast bipolar monolithic charge sensitive preamplifier (CSP), implemented in the monolithic; 2 mu m BiCMOS technology (called HF2CMOS) was designed and built in a quad monolitic chip. Studies of radiation effects in the CSP performance, from non-irradiated and up to neutron irradiation of 5.3 x 10(14) n/cm(2), have cofirmed that the use of bipolar npn transistors is suitable for the radiation level of the future LHC collider environment. The CSP presents a new circuit solution for obtaining adequate slew rate performances which results in an integral linearity better than 0.8% on 5 V at 20 ns of shaping time, regardless of the bias current selected for the CSP. This way the bias current of the CSP can be set for optimizing the power dissipation with respect to series and parallel noise, especially useful when the CSP is put in a radiation environment. A prototype test with a novel monolithic 20 ns time constant RC-CR shaper, capable to sum up four inputs has been also realized, featuring good integral linearity. (C) 1999 Elsevier Science B.V. All rights reserved

A four-channel analog-to-digital converter (ADC) for data acquisition in nuclear physics experiments has been developed on a VME board. The circuit architecture is a multistretcher configuration based on a fast conversion module. The board can operate either in sampling or in autotrigger mode with an input range of 4.096 or 8.192 V; the risetime protection can vary from 1 to 32 mu s. Many functions are software selectable; the most significant are: the linear gate trigger mode, the risetime protection, and the ability to set of the low and high thresholds independently for each channel. The conversion module is based on a two-step concept: an overall resolution of 12 b, with a conversion time lower than 1 mu s, is obtained by means of two 8-b flash ADCs and a sliding-scale compensation technique is used to improve the differential linearity. The differential linearity error is less than 1%, while the integral linearity error is 0.023% over the 98% of the dynamic range. >

A low-voltage, High-speed and High-resolution CMOS D/A converter is implemented using improved Unique Switching Sequence to reduce the error in the current cells output and Novel Segmented Layout Technique to minimize asymmeby and voltage drop due to power line resistance. The D!A converter has been fabricated by using 0.65um standard CMOS process. The differential linearity error is 0.37LSB and the integral linearity error is 0.87LSB. It occupies die area of 700*800& and operates up to 8OMHz with 3.0V. I. Introduction Low-voltage, High-speed and High-resolution CMOS D/A converters are necessaxy to enhance the performance of video applications. Especially in HDTV (high definition TV) and next generation camcorders, D/A converters of more than lObit and above 8OMHz are needed[ 11. This paper describes a 10-bit 8OMHz 3.0V CMOS D/A converter. In section 2, the architecture and operations of D/A converter are discussed. The experimental results are described in section 3, and the conclusion are discussed in section 4. a. Design of a D/A Converter Fig. 1 shows the block diagram of the D/A converter. The D/A converter is based on a current cell matrix that can drive a resistive load without any output buffer. The currents of lower 5 bits are generated by binary weighted current sources, and the currents of upper 5 bits are segmented into 31 unit-current sources. Each current sources for upper 5 bits has an output current 32 times that of the least significant bit(LSd). This architecture allows a reasonable mismatch between transistors for a maximum target differential lineiirity error(DLE) of half the LSB. To reduce the integral linearity error(lLE) caused by voltage drop along power lines, thermal distribution inside the chip and channel length modulation, the MSRs segmented 31 nonweighted current sources are arranged with regular pattem using a improved Unique Switching Sequence. To minimize asymmetry and voltage drop due to the power line resistance, A Novel Segmented Layout Technique has been developed. The layout technique exploited in the D/A converter uses unit current source, such that current source of 2 times, 4 times, 8 times, 16 times of the unit source are made multiple of the unit current source. Thus, the total number of segmented current sources are 31, the upper 5 bits of the MSB also consist of 31 current sources The MSB current source consists of two parts, each made of 16 unit current sources, and the unit current sources are placed between the 16 unit current sources. The 31 unit sources placed between the MSB source are placed in the order of DO in the middle and D1, D2, D3, D4 placed in between like, a pyramid structure. In this structure the current direction in the unit sources is most important. For example, by setting the currents to flow the opposite direction in the two D1 cells, it can minimize the effect of unit current mismatch caused by current directions. And also the matching is optimized to achieve DLE. m. Experimental Results

We propose a novel position-sensing method using slow and fast components in an output signal observed at one end of a resistive anode wire in a proportional counter in which the other end of the anode wire was grounded through a capacitor. Fairly sufficient characteristics in position resolution and an integral linearity were obtained. This method will extend the application field of a position-sensitive detector.

An ADC is described, which is of the successive approximation type and makes use of Gatti's sliding scale principle 1 ) for channel width averaging. The use of commercially available modular converters for both the ADC and the averager DAC resulted in a very simple and reliable construction of high stability. Conversion time is 15 μs. Differential linearity is better than 0.2%. Integral linearity is less than 0.01% and gain stability is in the order of 10 ppm/°C. A mapping of the channel profile is given for both “averager off” and “averager on”. No significant degradation of the channel profile due to the averager action could be found because of the good initial differential linearity of the ADC module.

A new type of ADC is being developed to satisfy the requirements of the HEAO high spectral resolution gamma ray spectrometer. This 13 bit design utilizes a double successive approximation technique that overcomes the usual differential linearity problem. Stability of a few ppm/°C, differential linearity of 2% and integral linearity of 0.05% have been demonstrated.

Describes a fully monolithic 16-bit digital-analog converter (DAC) which is fabricated with dielectric isolation and thin film nichrome resistors. The design uses a straightforward extension of techniques successfully used in lower resolution DACs. To achieve the greater accuracy needed for a 16-bit DAC, special layout techniques are used. An auxiliary R-2R ladder is introduced to provide a ground current cancellation scheme. The experimental results show that 16-bit resolution is possible with a typical settling time of 1 /spl mu/s. Improved performance over a temperature range of 0/spl deg/C-75/spl deg/C is observed with units exhibiting one-half an LSB differential and integral linearity of 14-bit resolution. The initial 16-bit accuracy approaches that of expensive hybrid modules, while the accuracy over wide temperature ranges surpasses anything presently reported.

A new type of two-dimensional neutron scintillation detector with high spatial resolution based on a position-sensitive photomultiplier has been investigated. With a 6Li glass scintillator a spatial resolution of 1.0 mm was measured. The integral linearity over the detection area of 55 × 45 mm2 is ⩽1.5 mm. The detector homogeneity is within 10% at a discriminator level at 60% of the average peak height. The spatial resolution is expressed by a geometrical parameter which could be evaluated from light experiments and by the number of photoelectrons per neutron capture.

A 6-b weighted-current-sink video digital-to-analog converter (DAC) with 10-90% rise/fall time of 4 ns, integrated with a double-metal 3- mu m CMOS technology, is described. Current-source matching, glitch reduction, and differential switch driving aspects are considered. A circuit solution and a nonconventional layout technique yield a high conversion rate with a standard CMOS technology. Experimental results show that a conversion rate of 100 MHz is achievable. The power consumption is 150 mW and the active chip area is 0.5*1.0 mm/sup 2/. The differential of 0.1 LSB demonstrates that 8 b of accuracy can be achieved. The integral linearity is 0.5 LSB. >

A new pulse-height store is described. Suitable contrivances improve integral linearity and reduce the differential errors that generally occur at signal amplitudes near the lower threshold. No degradations appear at high rates of input events. The electrical specifications of the pulse-height store are determined through a series of measurements described in the final part of the paper. In order to test the circuit in the most significant way, it has been connected to a fast successive-approximation conversion module which uses the sliding-scale technique for channel width equalisation, thus implementing a complete analog-to-digital converter (ADC) for nuclear spectrometry. The performances of the pulse-height store have been deduced from the behavior of the whole system.

An analysis on the linearity of a charge-division type position-sensing system is described. The method to obtain the total charge signal for division operation has been discussed in detail and criteria to design the position-sensing system with charge-division type proportional counters are shown. The previous result is confirmed theoretically, which shows experimentally that a long (⩾ 1 m) single-wire position-sensitive proportional counter can be designed to have a position non-linearity of less than 0.1%.

This paper describes a new instrument that very accurately transforms the peak height of repetitive waveforms into a dc voltage. Used in conjunction with a precision pulse generator, this instrument provides an improved method for establishing the integral linearity of pulse amplifiers. A measured overall accuracy of 0.005% for pulses with a nominal 1.0 μs peaking time has been achieved. This method is particularly useful with very fast amplifiers in the 5–100 ns range. The results of linearity measurements on several typical amplifiers are presented.

A high-speed 8-bit D/A converter has been fabricated in a 2-/spl mu/m CMOS technology. In order to achieve high accuracy, a current-cell matrix configuration and a switching sequence called symmetrical switching have been used. The mismatch problem of small-size transistors has been relaxed by this matrix configuration. The linearity error caused by an undesirable current distribution of the current sources has been reduced by symmetrical switching. A high-speed decoding circuit and a fast-setting current source have been developed. The experimental results show that the maximum conversion rate is 80 MHz, a typical DC integral linearity error is 0.38 LSB, a typical DC differential linearity error is 0.22 LSB, and the maximum power consumption is 145 mW. The chip size is 1.85 mm/spl times/2.05 mm.

The pulse amplitude divider and multiplier described in this article uses as the main element the Field Effect-Transistor (FET) working in the region before the pinch-off voltage. The integral linearity of the divider, with input changes of 1:20 and 1:10 respectively at the two inputs (1:200 ratio), is better than ±1.5% with a minimum pulse width of 2.5 μs. For the multiplier, the integral linearity for input changes of 1:20 at both inputs (output ratio 1:400) is better than ±1% with a minimum pulse width of 0.5 μs. The circuits are analog and with slight changes the pulse mode can be converted to a mode for continuous waveform.

An ADC with the following specifications has been designed and constructed: 8192 channels, amplitude range 0.05 to 10 V, positive, conversion time 12 μsec, max. integral linearity better than ± 2.5 × 10 −4 , stability of channel-width 0.5%. In a modification of the linear capacitor discharge a coarse and a fine measurement is executed subsequently, combined of a fast discharge and an interpolation with a slow discharge. The address oscillator works at 20 MHz, the address register is advanced during the coarse measurement in steps of 64 channels and during the fine measurement channel by channel. The discharge current generators are switched in exact synchronism with the pulses of the address oscillator; a two-step-synchronizing circuit is used. Special circuits have been developed for the pulsestretcher, the current-generators, current-switches and the discriminator. The high degree of stability and linearity is achieved through the proper use of field-effect-transistors, linear integrated circuits and fast digital intergrated circuits (emitter-coupled logic). Details of the tests performed and the testing methods are given.

A circuit is described for a digital pulse-height analyzer constructed wholly from commercially available computer logic and pulse-handling modules. The design combines the reproducible discrimination techniques of conventional analyzers for good differential linearity with a self-correcting successive approximation analog-to-digital converter for high speed and integral linearity.