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Field-programmable-gate-array-based time-to-digital converter with 200-ps resolution
- Source :
- IEEE Transactions on Instrumentation and Measurement. 46:51-55
- Publication Year :
- 1997
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 1997.
-
Abstract
- A new design of a time-to-digital converter (TDC) implemented on an FPGA chip with amorphous antifuse structures is presented. Time coding with 200-ps resolution (LSB), 10-ns range, and very short conversion time is realized by two tapped delay lines working in-a differential mode. Thanks to the local feedback loops, the output from the delay line is obtained directly in "1-out-of-N" code and then converted to 6-bit natural binary. Within the temperature range from 0/spl deg/C to 45/spl deg/C, the time offset at the output is constant, the resolution changes by /spl plusmn/0.02 LSB, and the offset-corrected integral linearity error is less than 1 LSB.
Details
- ISSN :
- 00189456
- Volume :
- 46
- Database :
- OpenAIRE
- Journal :
- IEEE Transactions on Instrumentation and Measurement
- Accession number :
- edsair.doi...........c39130ce08d639fd5ddd682329094d77