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A 10-b 125-MHz CMOS digital-to-analog converter (DAC) with threshold-voltage compensated current sources
- Source :
- IEEE Journal of Solid-State Circuits. 29:1374-1380
- Publication Year :
- 1994
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 1994.
-
Abstract
- This paper describes a 10-b high-speed COMS DAC fabricated by 0.8-/spl mu/m double-poly double-metal CMOS technology. In the DAC, a new current source called the threshold-voltage compensated current source is used in the two-stage current array to reduce the linearity error caused by inevitable current variations of the current sources. In the two-stage weighted current array, only 32 master and 32 slave unit current sources are required. Thus silicon area and stray capacitance can be reduced significantly. Experimental results show that a conversion rate of 125 MHz is achievable with differential and integral linearity errors of 0.21 LSB and 0.23 LSB, respectively. The power consumption is 150 mW for a single 5-V power supply. The rise/fall time is 3 ns and the full-scale settling time to /spl plusmn/1/2 LSB is within 8 ns. The chip area is 1.8 mm/spl times/1.0 mm. >
Details
- ISSN :
- 00189200
- Volume :
- 29
- Database :
- OpenAIRE
- Journal :
- IEEE Journal of Solid-State Circuits
- Accession number :
- edsair.doi...........c3317878365a603a93c6c8afe08cfa76