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The high peak mobility of 509 cm2/ $\text {V}\cdot \text {s}$ of the chemical vapor deposition -grown GeSn pMOSFETs is obtained using 1-nm Ge cap. The Ge cap on GeSn can reduce the scattering of oxide/interface charges and surface roughness for the holes in the GeSn quantum wells. However, the thick cap induces holes in the Ge cap itself, leading lower mobility than GeSn channels. The on current is enhanced by external stress due to the effective mass reduction. The normalized noise power density of the GeSn devices decreases with increasing Ge cap thickness, indicating the carrier number fluctuation and correlated mobility fluctuation are suppressed when the holes are away from interface.

The electron mobility in junctionless (JL) Ge nanowire nFETs with the $\langle 110\rangle $ channel direction is calculated and compared with experimental data. The calculation of the electron mobility is based on the Kubo–Greenwood formula. The wave functions are obtained by solving the self-consistent Poisson–Schrodinger equation. Phonon scattering, surface roughness scattering, and Coulomb scattering (CS) by interface charges and channel charges are considered. Carrier screening on Coulomb charges is calculated using Lindhard’s screening theory. At low electron densities, the JL channels have lower electron mobility than inversion-mode (IM) channels due to CS from channel charges. At high electron densities, CS in JL channels is effectively reduced by screening, resulting in mobility comparable with the IM channels. The L4 electrons have higher mobility than $\text{L}4^\prime $ electrons. Applying uniaxial tensile strain along the channel can lower the energy of L4 valleys to enhance the channel mobility.

The dependence of effective mass on Sn content, pseudomorphic strain, cap layer thickness, and substrate orientation is theoretically studied for Ge-cap/Ge1-x Sn x /Ge substrate p-channel MOSFETs through six-band k·p method. The Luttinger-like and deformation potential parameters were obtained from the fit of Ge1-x Sn x band structures by the empirical pseudopotential method. The valence band alignment is theoretically determined by the empirical pseudopotential method and the model-solid theory. The high Sn content and thin Ge-cap layer both result the small effective mass at zone center along channel direction of the first subband.

The channel cross section geometry and size dependence of the electron mobility in Ge nanowire nFETs is studied by theoretical calculations for devices beyond the 7nm node. circular channels have the highest mobility for wide channels (width>7nm) operating at high overdrive voltage (>0.5V). While diamond-shaped channels have the highest mobility for wide channels operating at low overdrive voltage (

The performance variation caused by the stress field near a through-silicon via (TSV) is measured using 28-nm node devices across 12-in wafers. The TSV is fabricated by a via-last process. The back-end-of-line dielectrics on TSV cause the asymmetric stress field, i.e., the absolute value of radial stress ( $\vert \sigma _{r}\vert )$ does not equal to that of tangential stress ( $\vert \sigma _{\theta }\vert )$ on silicon and leads to the asymmetric keep-out zone (KOZ), different from previously reported. A modified KOZ model with the asymmetric radial and tangential stress field is proposed and verified by 3-D finite-element analysis simulation and experiment data. The physics behind the asymmetry is also described. Comparable KOZ size for nFETs and pFETs is observed.

The hole mobility of relaxed Ge channel, and strained Ge channel on relaxed Si0.6Ge0.4 substrate were simulated and compared to our experimental work (Al2O3/GeO2 gate stack) and previous data. The rougher interface at GeO2/Ge than SiO2/Si makes a faster roll-off of Ge hole mobility at high field. For SiO2/Ge interface, the Ge hole mobility has a similar roll-off as Si universal mobility. Ge has higher mobility enhancement than Si under uniaxial compressive stress along [110] direction. For composite uniaxial compressive stress (-3GPa) and biaxial compressive strain (2.4%) on Ge p-MOSFETs, Ge mobility enhancement can reach as high as 23 times of Si mobility. The mass reduction of Ge is mainly responsible for the mobility enhancement.

It is the first time that CVD-grown GeSn channels with low thermal budget of 400°C significantly outperforms the Ge channel processed at high thermal budget of 550°C. Low thermal budget is necessary to prevent the Sn loss during the process. Note that only MBE-grown GeSn had large mobility reportedly in the past. Even with high Sn content (9%), the strong photoluminescence is observed from GeSn layers on Ge buffer on 300mm Si (001), indicating the high crystalline quality by CVD epitaxy. Ge cap with significant Δ Ev at Ge/GeSn interface can ensure the gate stack quality, and reduce the scattering of holes in the GeSn quantum wells by oxide/interface charges and surface roughness. However, the mobility is degraded by thick cap due to low hole population in the GeSn wells. The ∼7% mobility enhancement on channel direction is observed using external transverse uniaxial tensile strain of ∼0.11% due to the reduction of effective mass. The mobility of GeSn QW p-MOSFETs increases with decreasing temperature at both high and low inversion carrier density, indicating that the mobility is dominated by phonon scattering. On the contrary, Ge channels are dominated by Coulomb scattering at low inversion carrier density, which has decreasing mobility with decreasing temperature. The normalized noise power density of GeSn p-MOSFETs decreases with increasing Ge cap thickness, reportedly for the first time, indicating that the carrier number fluctuation and correlated mobility fluctuation can be reduced when the carriers are away from interface.

The low channel doping concentrations of 1.2×1019 cm−3 to deplete the channel and the high S/D doping of 1.2×1020 cm−3 to reduce the S/D resistance are achieved simultaneously by selective laser annealing on the same CVD P-doped epi-Ge on SOI without ion implantation. The device with Wfin down to 7 nm, EOT = 2.2 nm, and Lch = 60 nm has Ion = 1146 μA/pm, Ion/Ioff = 2×106, and SS = 95 mV/dec. The Ion can be further boost to 1235 μA/μm with external uniaxial tensile strain of 0.16%. The self-heating effect is responsible in part for such high Ion, because the high device temperature can reduce the dominant impurity scattering in the channel. The increasing mobility with increasing temperature indicates the impurity scattering is dominant. The lower low frequency noise is observed with junctionless (JL) gate-all-around (GAA) FETs than planar inversion mode (INV) devices due to the bulk conduction nature of JL FETs.

Pseudomorphic Ge 0.91 Sn 0.09 on Ge on Si with strong photoluminescence and low defect density is used for p-MOSFET channels. The mobility of Ge 0.91 Sn 0.09 Quantum Well p-MOSFETs are higher than control Ge p-MOSFETs due to hole population in the GeSn wells. The 7.5% mobility enhancement on channel direction is observed using external transverse uniaxial tensile strain (∼0.11%). The highest [Sn] of 9% in the channels grown by CVD, Pt SB S/D, high I on /I off ratio, and strain-enhanced mobility are obtained in this work.

Impact of via-last through-silicon via (TSV) on 28nm node devices is investigated. The stress field of TSV is affected by the back-end-of-line (BEOL) dielectrics. The absolute value of radial stress (|σr|) is different from that of tangential stress (|σθ|) on silicon, which leads to the asymmetric keep-out zone (KOZ). The physics behind the asymmetry is also described. A modified KOZ model considering the asymmetric stress field is proposed and verified by experiment data.

A Ge/GeSn/Ge single quantum well with 5% Sn content was grown by chemical vapor deposition on a Si substrate using Ge2H6 and SnCl4 precursors. External biaxial tensile strain was mechanically applied to the Ge/Ge0.95Sn0.05/Ge quantum well for the photoluminescence measurement. Note that the Ge0.95Sn0.05 layer is still under compressive strain due to the large internal compressive strain of the GeSn, although the external bending produces the tensile strain. The direct emission of tensily strained Ge buffer shifts toward lower energy, while the direct emission of pseudomorphic Ge0.95Sn0.05 quantum well does not have significant shift. The strain-induced energy changes of heavy holes and light holes in the Γ valley are extracted by fitting the photoluminescence spectra. Based on the nonlocal empirical pseudopotential method and the model-solid theory, a type-I band alignment is used for the fitting of photoluminescence spectra. The experimentally extracted band edge shifts from the photoluminescence measurement have good agreement with theoretical calculation.

In-situ CVD doping and laser anneal can reach [P] and tensile strain as high as 2×1020 cm−3 and 0.34%, respectively, in Ge on SOI with low defect density and high activation rate (nearly 100% near the surface), and enables high performance of the junctionless (JL) Ge gate-all-around (GAA) nFETs. The device with the W fin of 13 nm, EOT of 10 nm, and nominal L G of 280 nm has I on = 350 µA/µm, I on /I off = 3×106, SS = 185 mV/dec, and DIBL = 16 mV/V. The device with the W fin of 9 nm and EOT of ∼ 0.8 nm achieves the record high I on of 828 µA/µm at V GS - V T = 1.5 V and V DS = 2 V with DIBL = 54 mV/V, I on /I off = 1×105 and SS = 150 mV/dec. Besides the epitaxial tensile strain (0.34%) generated by laser anneal due to the misfit of thermal expansion coefficients between Ge and Si, the enhanced tensile strain by the microbridge structure is also beneficial for I on . The drain current enhancement of ∼40% is achieved under the mechanical uniaxial tensile strain of ∼0.25% due to sub-band splitting and carrier repopulation into the L4 valleys with the small conductive effective mass. The non-uniform shape of Ge channel with a minimum width at the center leads to enhanced I on as compared to uniform channel. The extracted mobility of JL devices increases with increasing temperature, indicating the domination of impurity scattering. The threshold voltage of JL devices has the negative temperature coefficient and EOT scaling reduces the temperature dependence.

The indirect-direct transition of Ge 1−x Sn x at Sn content 6.5% is simulated by nonlocal empirical pseudopotential method. The non-parabolicity band of Γ valley is considered for confined mass, density of state, and conductivity mass for the electron ballistic current calculation of Ge 1−x Sn x FinFETs. The integration of alloying Sn content and applying external stress enhances the ballistic current due to carriers transferring from indirect L valleys with small injection velocity to direct Γ valley and other indirect L valleys with high injection velocity.

Type-I, type-II, reverse type-I, and reverse type-II band alignments are found theoretically in strained Ge1−x Sn x (0 ≤ x ≤ 0.3) grown on relaxed Ge1−y Sn y substrates (0 ≤ y ≤ 0.3) using the model-solid theory. The prerequisite bandgaps, and energy difference between the top valence band edge and the average valence band position of GeSn are obtained by the nonlocal empirical pseudopotential method. For the indirect-gap (L valleys) Ge1−x Sn x on relaxed Ge1−y Sn y , the band alignments are type-I and reverse type-I under biaxial compressive strain (x > y) and biaxial tensile strain (x < y), respectively. For the direct-gap (Γ valley) Ge1−x Sn x on relaxed Ge1−y Sn y , the biaxial compressive strain yields type-I and type-II alignment, while the biaxial tensile strain yields reverse type-I and reverse type-II alignments.

The band structure of Ge in the lonsdaleite phase is calculated using first principles. Lonsdaleite Ge has a direct band gap at the Γ point. For the conduction band, the Γ valley is anisotropic with the low transverse effective mass on the hexagonal plane and the large longitudinal effective mass along the c axis. For the valence band, both heavy-hole and light-hole effective masses are anisotropic at the Γ point. The in-plane electron effective mass also becomes anisotropic under uniaxial tensile strain. The strain response of the heavy-hole mass is opposite to the light hole.

0.39-nm ultrathin EOT ZrO 2 having κ value as high as ∼43 without an interfacial layer (IL) is demonstrated on Ge substrates. The EOT and gate leakage are much lower than the recent reported data [1]. In situ NH 3 /H 2 remote plasma treatment (RPT) after RTO-grown ultrathin ( 2 /Ge and prior to PEALD ZrO 2 leads to the formation of tetragonal phase ZrO 2 and the inhibition of GeO x IL regrowth. As the number of RPT cycles increases, it is observed that not only higher [N] but more GeO 2 component formed on Ge surface. GeO diffuses into ZrO 2 layer via the interface reaction (Ge+GeO 2 → 2GeO) and stabilize the tetragonal phase ZrO 2 . The gate dielectric has a leakage current ∼104X lower than other reported dielectrics in this EOT region. Ge (001) pMOSFET has low SS of 85 mV/dec and high I on /I off of ∼6×105 at V d = −1V, while nMOSFET has SS of 90 mV/dec and I on /I off of ∼1×105 at V d =1V. The peak electron mobility is determined by the remote phonon scattering stemming from the high-κ value. The biaxial tensile strain of ∼0.04% applied on Ge (111) nMOSFET with an EOT=0.78nm produces a 4.8% drain current enhancement along the channel.

The record high peak mobility of ∼1050 cm2/V-s on (001) Ge substrate is demonstrated in NFET. High-quality Ge/GeO 2 interface is ensured by rapid thermal oxidation (RTO) and remote ozone plasma treatment. The best achieved subthreshold swing is 150mV/dec and the on/off ratio is 2×104. The low defective n+/p junction produced a record high on/off ratio of 2×105, an ideality factor of 1.05 and strong electroluminescence. For the first time, it is reported that the uniaxial tensile strain (0.08%) on channel direction gives the best mobility enhancement (12%) among the different strain configurations, consistent with theoretical calculation.

The electron mobility of n-channel metal-oxide-semiconductor field-effect transistors using Ge/GeO2/Al2O3 gate stack on (001) Ge substrates is analyzed theoretically and experimentally. Phonon scattering, Coulomb scattering, and interface roughness scattering are taken into account. The Ge peak mobility exceeding Si universal in our device by a factor of 1.3 is due to the reduction of Coulomb scattering of the interface states. As compared to Si, the faster roll-off of the Ge mobility at the effective field larger than 0.3 MV/cm is due to larger interface roughness scattering.

Well-behaved Ge n-channel metal-oxide-semiconductor field-effect transistors on (001) substrates with dispersion-free, high on/off ratio, and high peak mobility are demonstrated. The interface trap density is effectively reduced down to 5 × 1011 cm−2 eV−1 near midgap by GeO2 passivation using rapid thermal oxidation, resulting in high peak mobility of ∼1050 cm2/Vs. The fast roll-off of the mobility at high electric field is probably due to the large surface roughness scattering. By applying uniaxial 〈110〉 tensile strain (0.08%) on 〈110〉 channel direction, the best mobility enhancement (12%) can be achieved. The calculated strain responses with proper stress configurations are consistent with experimental results.