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A p-type (DiketoPyrroloPyrrole as organic semiconductor) Dual Gate OFET based biosensor is proposed for the detection of biomolecules in the nanocavity provided at the source end underlapping the region of the structure both at the top and at the bottom. Various biomolecules have been investigated for their effect on Drain current, ID which is a measure of sensitivity of the device. This device is then compared with different organic p-type semiconductor materials such as pentacene and tetracene based OFET biosensor. Drain current and sensitivity of these devices have also been calculated which shows that DPP (DiketoPyrroloPyrrole) based OFET biosensor has higher sensitivity of 3.0 x 10³ as compared to pentacene and tetracene based OFET biosensors. Simulation of these devices has been done in SILVACO ATLAS TCAD tool. The simulation results also show that the proposed device even shows higher sensitivity for high-k dielectrics such as HfO2, Ta2O5, TiO2. [ABSTRACT FROM AUTHOR]

Abstract This paper proposes and investigates a novel 4H‐SiC trench MOSFET (TMOS) with integrated high‐K deep trench and gate dielectric (INHK‐TMOS). The integrated high‐K (INHK) consists of a high‐K gate dielectric and an extended high‐K deep trench dielectric in the drift region. Firstly, the high‐K gate dielectric together with the metal‐forming high‐K metal gate structure, which increases the gate oxide capacitance (COX), reduces the threshold voltage (VTH) and the specific on‐resistance (Ron,sp). Secondly, the extended high‐K deep trench dielectric not only modulates the electric field in the drift region by introducing a new electric field peak at the bottom of the high‐K deep trench dielectric, thereby enhancing the breakdown voltage (BV), but also improves the doping concentration (ND) of the drift region by the assist depletion effect of the high‐K dielectric, further optimizing the forward conduction characteristics. Simulation results demonstrate that when compared to the conventional TMOS, the INHK‐TMOS using HfO2 exhibits a 52.6% reduction in VTH, a 52.1% reduction in Ron,sp, a 20.3% increasement in BV and a 202.3% improvement in figure of merit.

We report insights into the interface carrier-confinement-assisted dielectric and electrical properties in atomic-layer-deposited Al2O3/TiO2 nanolaminates (NLs). With progressive thinning of the sublayers down to ∼0.48 nm, the dielectric constant, polarization voltage, bang gap, and interfacial two-dimensional electron gas density of NLs improved due to the enhanced Maxwell–Wagner interfacial polarization and size-dependent quantum confinement effect. The typical current vs voltage (I–V) characteristics of NLs revealed an inherent nanobattery effect and quantum tunneling transport due to the electrical inhomogeneity and carrier confinement across sublayers, respectively. These tunable properties make these NLs a highly suitable dielectric material for various nanoelectronic applications. [ABSTRACT FROM AUTHOR]

The conditions for the growth of n-type Ge layers with the parameters required to create a Ge-MISFET with an induced p-type channel using the hot wire chemical vapor deposition (HW CVD) method are determined. The conditions for deposition using electron beam deposition and subsequent annealing of the subgate high-k dielectric ZrO2:Y2O3 layers are optimized, allowing us to achieve a leakage current value of 5 × 10–6 A/cm2. For the developed device structure, some parameters of the Ge-MISFET are calculated, such as the channel length, maximum voltage between the sink and source, and breakdown voltage. [ABSTRACT FROM AUTHOR]

This paper proposes and investigates a novel 4H‐SiC trench MOSFET (TMOS) with integrated high‐K deep trench and gate dielectric (INHK‐TMOS). The integrated high‐K (INHK) consists of a high‐K gate dielectric and an extended high‐K deep trench dielectric in the drift region. Firstly, the high‐K gate dielectric together with the metal‐forming high‐K metal gate structure, which increases the gate oxide capacitance (COX), reduces the threshold voltage (VTH) and the specific on‐resistance (Ron,sp). Secondly, the extended high‐K deep trench dielectric not only modulates the electric field in the drift region by introducing a new electric field peak at the bottom of the high‐K deep trench dielectric, thereby enhancing the breakdown voltage (BV), but also improves the doping concentration (ND) of the drift region by the assist depletion effect of the high‐K dielectric, further optimizing the forward conduction characteristics. Simulation results demonstrate that when compared to the conventional TMOS, the INHK‐TMOS using HfO2 exhibits a 52.6% reduction in VTH, a 52.1% reduction in Ron,sp, a 20.3% increasement in BV and a 202.3% improvement in figure of merit. [ABSTRACT FROM AUTHOR]

High dielectric constant materials are of technological importance as they lead to the miniaturization of electronic devices. The permittivity of a material determines the relative speed that an electrical signal can travel in that material. The dielectric properties of pure ZnO are developed due to the defects of zinc excess at the interstitial position and the lack of oxidation. Fe and Li co-doping in ZnO are envisaged here to develop high dielectric materials by converting the material into a p-type semiconductor without creating stoichiometric oxygen defects in the lattice and making it robust against the oxidizing atmosphere. The formation of single-phase Fe and Fe/Li co-doped wurtzite ZnO samples is confirmed by X-ray diffraction analysis. The Fe and Fe/Li doping depresses the concentration of the intrinsic donor and impedes the conduction mechanism resulting in the highest dielectric constant (ɛr′) equivalent to 612 and 90,000 are found for bulk pristine Zn0.9Fe0.1O and Zn0.8Li0.1Fe0.1O at 400oC with 1000 ​Hz applied frequency. Also with an increase in frequency, the dielectric constant and dielectric loss are found to decrease. This behavior is attributed to different hopping mechanisms and defects formed during synthesis.

In this study, low-temperature deuterium annealing (LTDA) at 300 °C is proposed to enhance both the performance and reliability of silicon-based high-k metal gate (HKMG) MOSFETs. A comparative study with hydrogen (H2) annealing under identical conditions is conducted to evaluate the specific impact of deuterium (D2). Comprehensive DC characterizations and evaluations of stress immunity under hot-carrier injection (HCI) and positive bias stress (PBS) conditions, are performed. The results confirm that even at a low temperature of 300 °C, D2 has a more substantial effect on device performance and reliability compared to H2. This study provides a guideline for reducing the annealing temperature in the fabrication of HKMG MOSFETs.

By using a simple device architecture along with a simple process design and a low thermal-budget of a maximum of 100 °C for passivating metal/semiconductor interfaces, a Schottky barrier MOSFET device with a low subthreshold slope of 70 mV dec−1 could be developed. This device is enabled after passivation of the metal/silicon interface (found at the source/drain regions) with ultra-thin SiO x films, followed by the e-beam evaporation of high- quality aluminum and by using atomic-layer deposition for HfO2 as a gate oxide. All of these fabrication steps were designed in a sequential process so that a gate-last recipe could minimize the defect density at the aluminum/silicon and HfO2/silicon interfaces, thus preserving the Schottky barrier height and ultimately, the outstanding performance of the transistor. This device is fully integrated into silicon after standard CMOS-compatible processing, so that it could be easily adopted into front-end-of-line or even in back-end-of-line stages of an integrated circuit, where low thermal budget is required and where its functionality could be increased by developing additional and fast logic. [ABSTRACT FROM AUTHOR]

This work discusses a junction-less nanowire tunnel field effect transistor (JLN-TFET) that combines the advantages of a junction-less field effect transistor (JLFET) and a tunnel field effect transistor (TFET). With a hetero-structure device made of silicon (Si) and germanium (Ge), an amalgamation of gate engineering and channel engineering is investigated. To eliminate junctions in the structure, a uniformly high dosage of doping (1019cm-3) has been employed throughout. In contrast to the source work function, which is set at 5.93 eV, the gate work function is set at 4.5 eV. When compared to junction less nanowire tunnel FET (JLTFET), the modified gate-all-around hetero junction less nanowire tunnel field effect transistor (GAA-H-JLNTFET) performs better. The proposed structure GAA-H-JLNTFET exhibits the ON current (ION) 6.5 × 10−5µA/m, the off current (IOFF) measures 2.97 × 10−20µA/m, the subthreshold slope (SS) is 12mV/Dec, and ION/IOFFis ≈ 1015which makes them immune to short channel effect and suitable for low power application in Nano regime. Further, in this work, the proposed structure is utilized to implement the dielectric modulated low-power biosensor. The drain current is taken as the sensitivity parameter. Five different biomolecules sensitivity are measured and found better than the previous published results. For the simulation and analysis, the Silvaco Atlas 2D simulator with non-local band-to-band tunneling is used. [ABSTRACT FROM AUTHOR]

NdON, HfON, and their mixtures (NdxHf(1−x)ON) with different Hf contents are adopted as the gate dielectrics of pentacene organic thin‐film transistors (OTFTs). Their capacitance–voltage characteristics reveal that the Hf incorporation generates negative fixed charges in the dielectric for assisting the applied gate voltage, thus achieving a low threshold voltage for the OTFT. X‐ray photoelectron spectroscopy (XPS) and atomic force microscopy (AFM) results indicate that Hf can suppress the hygroscopicity of Nd oxide while Nd can passivate the carrier traps (e.g., oxygen vacancies) of Hf oxide, both of which can contribute to a smoother dielectric surface for the growth of larger pentacene grains on the dielectric surface. As a result, among the samples with different Hf contents, the OTFT with Nd0.85Hf0.15ON can achieve the highest carrier mobility of 1.95 cm2 V−1 s−1 due to least Coulomb scattering (associated with lowest interface‐trap density of 5.9 × 1012 cm−2 eV−1 and smallest hysteresis of 0.26 V) and least grain‐boundary scattering (associated with largest pentacene grains). [ABSTRACT FROM AUTHOR]

The Electro-optic (EO) modulator is one of the most important devices for optical communication. Lithium niobate on insulator (LNOI) platform has matured over the last few years and has resulted in some excellent EO modulators with very low voltages, low optical losses, and high bandwidth. In this paper, we proposed a novel EO modulator based on the LNOI platform where a cladding material of very high dielectric constant i.e., barium titanate (BTO) is used around an etched lithium niobate (LN) waveguide. Lumerical Mode and Device simulations have been used to optimize a Mach-Zehnder interferometer (MZI) based EO modulator that shows a half-wave-voltage-length product as low as $\sim$1.36 V.cm maintaining the optical loss due to metal absorption of $\sim$1 dB/cm. The 3 dB EO bandwidth of $\sim$132 GHz has been estimated using the data generated by the microwave simulations carried out in CST Studio Suite.

In this study, we investigate the deposition of high-k dielectric materials, namely Al2O3 and HfO2, using atomic layer deposition for 4H-SiC metal-oxide-semiconductor applications. C-V measurements reveal that the HfO2/SiO2/Al2O3/4H-SiC structure exhibits lower interface state density (Dit) and a reduced number of fixed interface trap charges (Neff) than the HfO2/Al2O3/SiO2/4H-SiC structure. Furthermore, we observe significant degradation of the interface properties when annealing at 400 °C compared with 300 °C, as evidenced by atomic force microscopy images. Transmission electron microscopy analysis shows that the SiO2/SiC surface is inhomogeneous and contains carbon clusters, while the Al2O3/SiC interface displays a more uniform structure. The I-V curves demonstrate a reduced leakage current for the high-k dielectric stacked structure to (10−11 A/cm2), and the breakdown electric field of the HfO2/SiO2/Al2O3/4H-SiC structure reaches 9.6 MV/cm.

Atomic layer deposition of HfO2 from TDMAH and water or ammonia water at different temperatures below 400 °C is studied. Growth per cycle (GPC) has been recorded in the range of 1.2–1.6 Å. At low temperatures (≤100 °C), the films grew faster and are structurally more disordered, amorphous and/or polycrystalline with crystal sizes up to 29 nm, compared to the films grown at higher temperatures. At high temperatures of 240 °C, the films are better crystallized with crystal sizes of 38–40 nm but grew slower. GPC, dielectric constant, and crystalline structure are improved by depositing at temperatures above 300 °C. The dielectric constant value and the roughness of the films have been determined for monoclinic HfO2, a mixture of orthorhombic and monoclinic, as well as for amorphous HfO2. Moreover, the present study shows that the increase in the dielectric constant of the films can be achieved by using ammonia water as an oxygen precursor in the ALD growth. The detailed investigations of the relationship between HfO2 properties and growth parameters presented here have not been reported so far, and the possibilities of fine-tuning and controlling the structure and performance of these layers are still being sought. [ABSTRACT FROM AUTHOR]

Being an important semiconductor material for high power applications, silicon carbide (SiC) faces the problems while used as a gate oxygen layer in traditional Si MOS devices. In view of this, an innovative approach was adopted in the present work to replace the conventional SiO _2 with a high-k material (ZrO _2 ) as the gate oxygen layer to investigate its effect on the electrical characteristics of the devices. In particular ZrO _2 films were deposited on Si and SiC substrates by atomic layer deposition (ALD), and Al was used as the electrode. The atomic force microscopy (AFM) microregion scan revealed a highly flat surface with R _q < 1 nm after the ALD growth of ZrO _2 layer. The sample surface analysis via x-ray photoelectron spectroscopy (XPS) suggested the presence of a small amount of ZrO _x components. According to the electron energy loss spectrum (EELS), the band gap width (E _g ) of this ALD ZrO _2 dielectric was 5.45 eV, which met the requirements for high-quality 4H-SiC-related MOS devices. The electrical properties of the samples were then studied, and the maximum breakdown voltage of the Al/ZrO _2 /SiC/Al MOS structure was obtained to be 23 V, i.e., nearly twice that of the Si substrate. As for the oxide layer, the interface defect density (D _it ) near the conduction band of the Al/ZrO _2 /SiC/Al MOS structure was only 10 ^12 eV ^−1 cm ^−2 orders of magnitude. The N _eff value (the movable charge) of the structure was also controlled at 10 ^12 cm ^−2 . Therefore, the overall performance of the ZrO _2 /SiC structure in terms of electrical properties exceeded that of the ZrO _2 /Si structure and previously reported counterparts. In this respect, the ZrO _2 /SiC MOS capacitor structure has great research potential.

The current commercially viable light detection and ranging systems demand continuous, full-scene, and dynamic two-dimensional point scanning, while featuring large aperture size to ensure long distance operation. However, the biasing architecture of large-area arrays with numerous individually controlled tunable elements is substantially complicated. Herein, inverse design of a perimeter-controlled active metasurface for two-dimensional dynamic beam steering at mid-infrared regime is theoretically presented. The perimeter-control approach simplifies biasing architecture by allowing column-row addressing of the elements. The metasurface consists of a periodic array of plasmonic patch nanoantennas in a metal-insulator-metal configuration, wherein two active layers of indium arsenide are incorporated into its building block. The metasurface profile facilitates wide phase modulation of ≈355°$\approx 355^{\circ} $ on the reflected light at the individual element level through applying independent voltages to its respective columns and rows. The multi-objective genetic algorithm (GA) for optimizing user-defined metrics toward shaping desired far-zone radiation pattern is implemented. It is demonstrated that multi-objective GA yields better results for directivity and spatial resolution of perimeter-controlled metasurface by identifying the design tradeoffs inherent to the system, compared to the single-objective optimizer. A high directivity and continuous beam scanning with full and wide field-of-view along the azimuth and elevation angles are respectively maintained.

The continuous scale-down of dynamic random-access memory (DRAM) requires shrinkage of high aspect ratio metal-insulator-metal (MIM) capacitance along with the successful suppression of its leakage current to maintain desired levels of charge storage and retention. As the dimensions of stacked insulating dielectric and metal electrodes in the MIM capacitor are currently

Among several types of innovative bio-sensing technologies, label free dielectric modulated field-effect transistor (DM-FET) based biosensors, stand out because of their appealing properties, including ultra-sensitivity detection, mass-production capacity, low-cost manufacturing, and batch testing facility. This work investigates the Dielectric Modulated Tunnel Field Effect Transistor (DM-TFET) biosensor for low power applications and performance characterization. ATLAS TCAD simulator tool from SILVACO is used to simulate and characterise the biosensor. In this work we proposed and compared three different types of double gate (DG) TFET based biosensors, i.e., both side cavity (DG_BSC_TFET), drain side cavity (DG_DSC_TFET) and full both side cavity (DG_FBSC_TFET). The proposed biosensors are differentiated on the basis of the exposed area to trap the biomolecules. In particular, we focused on the sensitivity and ambipolarity of tunnel field-effect sensors. Further, we analysed the effect of biosensor performance on sensing surface properties, including electric field strength, transfer characteristics, Ion/Ioff ratio, and various other related parameters. The critical difficulties of device design and practical limits have been addressed. The simulated results show that the ambipolar current sensitivity of the proposed structure shows comparative better results than other published data, and it is observed that the sensitivity of the DG-FBSC-TFET-based biosensor is twofold more than the DG_BSC_TFET and DG_DSC_TFET. Due to the higher surface to volume ratio in DG_FBSC_TFET, a greater number of biomolecules are immobilised on the surface of the biosensor, which makes it a capable candidate for future low power label free biosensors. [ABSTRACT FROM AUTHOR]

In this paper, N-type and P-Type low power SiGe Silicon on Insulator Vertical TFET (SOI-VTFETs) are designed and then their drain current is investigated. The designed structures are calibrated with the reported structures considering the same model's environment for the validation of the design. Here, several advantages of SOI have been incorporated so that the low-voltage with low power (LVLP) VLSI designs digital circuits can be easily realized. Gate staking of high k -dielectric (HfO2) material with SiO2 was used to prevent the loss of the Lattice misfit structure using the equivalent oxide thickness approach. The proposed device's highest ON current and largest ON/OFF current are claimed to be (3.62 × 10−4 A/m) and (1013), respectively. Then the designed device is used to implement the full adder and the Infinite Impulse Response (IIR) filters. It is found that the performance of IIR filters is much enhanced over Finite Impulse Response (FIR) filters to keep flat response for altogether trial rates. The total delay of the IIR decimation filter via Merged Delay Transformation (MDT) is 0.181 ns with a Power Delay Product (PDP) of 3.5767. The current method employs the Routh Hurwitz Array method's advantages to derive the reduced-order denominator polynomial, and the reduced order numerator is obtained based on the resultant denominator polynomial. This order reduction technique is incorporated to reduce the number of delay units of the IIR filter and modified architecture offering a PDP of 0.22563, with its flat response initiated by SOI VTFET. The current model is productive in lowering area, power consumption, and stability over a specific sample rate or frequency. [ABSTRACT FROM AUTHOR]

InGaAs/Ge complementary FinFET technology has been considered as an alternative channel material for CMOS technology, useful for next-generation digital VLSI circuits. The soft errors in these C-FinFETs are dominated by the ion strike at the InGaAs n-channel FinFET due to its high charge collection efficiency, low ionization energy and high mass density. In this paper, a physics-based model of single-event transients (SET) in an InGaAs FinFET is proposed which captures the dependence of device, radiation and circuit parameters on the transient current. The electrostatic potential and the drain current models are developed considering the additional electron density due to the ion strike in the InGaAs n-channel FinFET with high-k dielectric material as the oxide layer. The SET current obtained from the model is validated using TCAD simulations for different device dimensions, dielectric materials, linear energy transfer (LET), strike positions and voltage bias. The developed model is integrated into the Cadence circuit simulator, and the output voltage perturbations are analyzed for different load capacitances and LETs. [ABSTRACT FROM AUTHOR]

Electrohydrodynamic (EHD) jet printing is known as a versatile method to print a wide viscosity range of materials that are impossible to print by conventional inkjet printing. Hence, with the understanding of the benefits of EHD jet printing, solution-based MoS2 and a high-viscosity Ag paste were EHD jet-printed for electronic applications in this work. In particular, printed MoS2 TFTs with a patterned Ag source and drain were successfully fabricated with low-k silica (SiO2) and high-k alumina (Al2O3) gate dielectrics, respectively. Eventually, the devices based on Al2O3 exhibited much better electrical properties compared to the ones based on SiO2. Interestingly, an improvement of around one order of magnitude in hysteresis was achieved for devices after changing the gate insulator from SiO2 to Al2O3. In effect, the results of this work for the printed MoS2 and the printed Ag source and drains for TFTs demonstrate a new approach for jet printing in the fabrication of electronic devices. [ABSTRACT FROM AUTHOR]

• Sputter-deposited copper iodide (CuI) p-type thin film transistor(TFT) with a high-κ dielectric, field-effect channel mobility of ~2.1 cm2/Vs, and <5 V low-voltage operation. • Morphology of CuI stabilized by passivation with Al 2 O 3. • I on /I off ratio improves to ~250 after forming gas anneal. This paper reports on a back-gated p-type thin film transistor (TFT) with copper iodide (CuI) as the channel material, a HfO 2 gate dielectric layer, and Al 2 O 3 passivation. The γ-CuI channel was deposited from a CuI target using DC magnetron sputtering at room temperature. Our TFT can be fully shut off by V G = 4 V, with a field-effect channel hole mobility μ h ∼ 1.5–2 cm2 V−1 s−1. An anneal in forming gas was performed twice, once at 200 °C, then at 250 °C to improve gate control, yielding a final I on /I off current ratio of ∼ 250. The anneal served two purposes: to reduce the oxygen acceptor density in the CuI channel and reduce the concentration of interface states between the CuI, Al 2 O 3 passivation, and HfO 2. A model of the device was built in an industrial TCAD simulator, which reproduces the measured characteristics and allows an estimation of interface state densities and channel doping. [ABSTRACT FROM AUTHOR]

Tunable metasurfaces can change the optical properties of incident light at will such as amplitude, phase, and polarization in a time-dependent fashion. Ultrafast switching speed and the ability for the pixel size reduction of the tunable metasurface can allow various applications such as light detection and ranging, interferometric sensors, and free space optical communications, to name a few. Although there have been successful demonstrations of the wavefront shaping using the tunable metasurface, the implementation of the two-dimensional metasurface pixel array that can be individually addressed in the optical frequency regime still remains challenging. Here, we present the experimental demonstration of the two-dimensional beam steering with the metasurface array by the binary phase grating in the infrared regime. The metasurface unit cell is composed of metal–dielectric–oxide structure with the indium tin oxide as an active layer, which is modulated by using the top fan-out electrodes. The metasurface array is two-dimensionally pixelated and has the phase change above 137° in the infrared regime.

Nowadays, the junctionless (JL) multigate (MG) metal-oxide-semiconductor field-effect transistors (MOSFETs) are the pacesetter within the emerging nanodevices because of their improved gate controlling nature [J J Kim and K Roy, IEEE Trans. Electron Devices51(9), 1468 (2004)] at 20 nm channel node. Here multiple gates are simultaneously controlling the channel. On the other hand, the alignment of the top and bottom gates is a source of worry during fabrication since its effects are detrimental to the performance of the device. Furthermore, with multiple gate-designed DG MOSFETs, the problem of top-to-bottom gate alignment becomes highly significant for the performance of the device. This paper is about an N-doped SiGe DG-JL-MOSFET where a high electron mobility III–V compound GaSb is employed at the source regime. To generate more on-current and low leakage current, SiGe is used for the channel and the drain. Material having high permittivity (HfO2) is used as the gate oxide to enhance the gate controllability at the 20 nm channel node. In this work, the impact of gate misalignment on DC and RF properties of asymmetric double-gate junctionless (ADGJ) and symmetric double-gate junctionless (SDGJ) MOSFETs at 20 nm channel is studied using simulations. The influence of gate underlap and overlap on several DC and RF characteristics such as IdVg, IdVd, gm, gd, intrinsic gain, Cgs, Cgd and fT are discussed in this manuscript, and it is observed that the DG-JL-MOSFET shows a better response to DC and RF characteristics for 50% of the gate misalignment towards the source. In the proposed structure, an improvement in drain current is observed during the misalignment of the front gate towards the source. The value of Ion / Ioff is also more in the case of the proposed heterostructure device than the earlier Si-based JLFET. [ABSTRACT FROM AUTHOR]

In this paper a detailed investigation is carried out upon doping less tunnel field effect transistor (DLTFET) under symmetric and asymmetric conditions. For this purpose, a range for back gate metal work function (ɸBG) from 4.1 eV to 4.8 eV and the back gate oxide thickness (tox) from 3 to 6 nm have been considered by keeping the front gate work function (ɸFG) fixed with 4.5 eV and EOT (Equivalent oxide thickness) of 0.8 nm respectively. Analysis with respect to analog parameters such as transconductance (gm), total gate capacitance (Cgg) and cut-off frequency (fT) has been made and compared with the range of symmetric and asymmetric conditions. It is observed from simulation results that the DLTFET has an optimum performance at ɸBG of 4.5 eV and tox of 0.8 nm EOT. Later the device is then utilised to implement common source amplifier circuit. A range of variations with respect to load resistor (RL) and drain resistor (RD) were made to check for the circuit's performance at gain's perspective. [ABSTRACT FROM AUTHOR]

Two-dimensional (2D) analytical model for the subthreshold characteristics like Surface potential, threshold voltage, subthreshold current and swing of uniformly doped, high-k gate stack double-gate (DG) metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed in this paper. The minimum surface potential obtained by solving the 2D Poisson's equation using evanescent mode analysis has been utilized to model the threshold voltage, subthreshold current and subthreshold swing. The effects of various parameters on these parameters have also been presented. The results show excellent matching with the numerical simulation data obtained by ATLAS™, a 2D device simulator from SILVACO. [ABSTRACT FROM AUTHOR]

The channel modulated junctionless gate all around (CM-JL-GAA) MOSFET improves the SCE's with high graded doping of the channel region. Temperature effects on electrostatic and analog/RF performance of channel modulated junctionless gate all around (CM-JL-GAA) MOSFETs have been explored in this work throughout a temperature range of 200 K to 500 K. The channel length, gate oxide thickness, and gate oxide material of CM-JL-GAA MOSFET has been varied to understand the impact of process parameters on device performance using Silvaco 3D device simulator. The electrostatic and analog/RF parameters have been figure out for the specified temperature range with process parameter variation. When the temperature of CM-JL-GAA MOSFETs is increased from 200 K to 500 K, the analog/RF performance is marginally affected. The intrinsic gain (AV) is negligibly affected (~3 dB) with raised in temperature. The adoption of a high-k gate dielectric improves electrostatic performance such as DIBL, SS and Ion/Ioff and marginal deterioration in the analog/RF performance of CM-JL-GAA MOSFETs, according to this study. With temperature changes, the high-k dielectric has a minor impact on the analog/RF performance of CM-JL-GAA MOSFETs. Hence, the CM-JL-GAA MOSFETs device have better analog/RF performance at higher temperature with high-frequency applications. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model has been developed for a single gate tunnel FET, introduced with a highly doped pocket in the vicinity of the source-channel junction and the bottom oxide layer being distributed between SiO2 and a high-k material such as HfO2. Introduction of the pocket region modifies the energy band diagram of the device thereby augmenting the electron tunneling from the source valence band to the channel conduction band in the band to band tunneling (BTBT) process of conduction. The proposed model results into an improvement in the surface potential, electric field profile and finally in the on state current Ion. Comparison of surface potential, electric fields for various Vgs has been made. Comparisons of the surface potential for various pocket widths, with and without the pocket & with & without the high-k dielectric material have also been made to show improvements in the proposed structure. Finally, drain current is computed and a comparison is made with & without the high-k dielectric material used in buried oxide. [ABSTRACT FROM AUTHOR]

ZnO has been extensively used as oxide in the thin film electronics industry because of its performance advantages such as electrical and optical properties. This study represents the design and optimization of the ZnO thin film transistor (TFT). The characteristics of the device are studied using the software Silvaco TCAD ATLAS. The improvement in the performance of the device has been observed in optimizing dielectric layer thickness ( T ox ). Further SiO2 oxide layer is replaced with the high- k dielectric to improve its performance. The use of high- k dielectric gives the concept of equivalent oxide thickness (EOT) in which physical thickness (PT) of the dielectric layer is increased without increasing electric thickness (effective thickness), which improves the reliability of the device. The electrical parameters extracted for the low- k SiO2 (K = 3. 9) at thickness (TSiO2) 50 nm are I on = 2. 1 3 × 1 0 − 5 A, I off = 1. 4 1 × 1 0 − 1 2 A, I on ∕ I off = 1 0 7 , SS = 0. 0 7 7 V/decade, VTH = 0. 2 7 V. The high performance of the device has been achieved using Al2O3 and HfO2 as the dielectric material. This study presents the design and optimization of the ZnO thin film transistor. The characteristics of the device are studied using the software Silvaco TCAD ATLAS. The improvement in the performance of the device has been observed in optimizing dielectric layer thickness (Tox). Further SiO2 oxide layer is replaced with the high-k dielectric to improve its performance. [ABSTRACT FROM AUTHOR]

As electronic circuit integration intensifies, there is a rising demand for dielectric insulators that provide both superior insulation and high dielectric constants. This study focuses on developing high-k dielectric insulators by controlling the phase of the Hf 0.5 Zr 0.5 O 2 (HZO) film with additional doping, utilizing yttrium (Y), tantalum (Ta), gallium (Ga), silicon (Si), and aluminum (Al) as dopants. Doping changes the ratio of tetragonal to monoclinic phases in doped HZO films, and Y-doped HZO (Y:HZO) films specifically exhibit a high tetragonal phase ratio and a dielectric constant of 40.9, indicating superior insulating properties compared to undoped HZO films. To clarify the fundamental mechanism driving the enhancement in dielectric properties, we have carried out various analyses combined with density functional theory (DFT) calculations. Through the optimization of the post-deposition annealing (PDA) process and the heterojunction structure with Al 2 O 3 , an Al 2 O 3 /Y:HZO heterojunction with a high dielectric constant and even lower leakage current compared to a single layer was developed. The thin-film transistor (TFT) with the Au/Ti/amorphous InGaZnO 4 (a-IGZO)/Al 2 O 3 /YHZO/TiN heterojunction structure exhibits low subthreshold swing (SS) values within a narrow gate-source voltage ( V ) range. This study advances knowledge on how the controlled-phase doped HZO films affect the dielectric constant and leakage current and will contribute to semiconductor technology advancements by overcoming the limitations of conventional high-k dielectric insulators.sg ) range. This study advances knowledge on how the controlled-phase doped HZO films affect the dielectric constant and leakage current and will contribute to semiconductor technology advancements by overcoming the limitations of conventional high-k dielectric insulators.

The continuous scale-down of dynamic random-access memory (DRAM) requires shrinkage of high aspect ratio metal-insulator-metal (MIM) capacitance along with the successful suppression of its leakage current to maintain desired levels of charge storage and retention. As the dimensions of stacked insulating dielectric and metal electrodes in the MIM capacitor are currently <10 nm, interfacial mixing has a large impact on the reliability of the capacitor. This is because defects and secondary interface oxides significantly alter the physicochemical properties of MIM capacitors. The methodology required to characterize ultrathin interfaces in relation to the performance of MIM devices is highly challenging due to its physical and chemical complexities of interface between dielectric and electrode. In this study, a ZrO2-based dielectric film and its interface (with an ultrathin TiO2/Al2O3 buffer layer) are analyzed using angle-resolved X-ray photoelectron spectroscopy (ARXPS), spectroscopic ellipsometry (SE), and temperature dependent I–V analysis for a DRAM MIM capacitor. The composite dielectric layer included either Al2O3 on the bottom or Al2O3/TiO2 between the TiN electrode and ZrO2. This study suggests an effective metrology approach to characterize ultrathin MIM capacitors and the important role of interfacial stabilization using a buffer layer for the effective control of leakage current. [ABSTRACT FROM AUTHOR]

In this study, MIS structures In/Al2O3/InSb and In/SiOx/anodic oxide/InSb were characterized. The A2O3 insulator layer were formed by the atomic layer deposition method. For second sample, we applied combination of insulators, which include anodic oxide film and SiOx layer deposited by the resistive evaporation method. For both structures, we mapped a fixed charge and interface trap level over 2-inch InSb wafers. The average value of the fixed charge level, NF, for MIS-structures In/Al2O3/InSb and In/SiOx/anodic oxide/InSb were 1.4 × 1011 cm–2 and 2.9 × 1011 cm2, respectively. The spread of Dit values over the wafer in the In/Al2O3/InSb MIS structure did not exceed 9% that confirms feasibility Al2O3 insulators films deposited by ALD as a passivation coating for InSb-based photodiode arrays.. [ABSTRACT FROM AUTHOR]

Two-dimensional (2D) transition-metal dichalcogenides have promising optoelectronic applications. However, most reported MoS2-based photodetectors are based on MoS2 flakes, dozens of microns in size, prepared by mechanical exfoliation or chemical vapor deposition, which limits their practical applications. In this study, a wafer-scale, continuous, and uniform multilayer MoS2 nanosheet was grown on an insulating single-crystal sapphire substrate by atomic layer deposition (ALD), with MoCl5 and hexamethyldisilathiane as precursors, because of the smaller lattice mismatch between crystalline sapphire and hexagonally arranged MoS2 compared with polycrystalline substrates. Then, large-area MoS2 nanosheets with high uniformity and homogeneity were obtained on Al2O3/Si and SiO2/Si substrates via large-scale peeling and vacuum stacking transfer. Subsequently, MoS2 photodetectors were fabricated on both substrates with ALD-MoS2 as a photosensitive channel material and high-k Al2O3 or SiO2 as a dielectric layer, which resulted in gate control with relatively low and high voltages, respectively. A high photoresponsivity (R) of 577.4 A W–1 was achieved for the MoS2 photodetector fabricated on the Al2O3/Si substrate at an illumination power density (Pin) of 5.01 μW cm–2 (λ = 500 nm). In addition, the MoS2 photodetectors exhibited a light response over a wide wavelength range (400–700 nm). Moreover, a MoS2 photodetector array containing 4 × 3 photodetectors with a uniform photoelectric response was demonstrated. These results will facilitate future applications of 2D materials in large-scale, high-performance photoelectronic devices and circuits. [ABSTRACT FROM AUTHOR]

In present days, the improved performance in nanoscale dimensions is of enormous need than conventional CMOS devices. This paper presents an insight into Trigate FinFET in 5 nm technology using ATLAS 2D simulator. The drain current model based on surface potential calculation is shown to study the performance of tri gate FinFET. The 2D Poisson's equation is solved for both the gates of tri gate FinFET which results in effects of gate voltage in performance parameters. Different high-K dielectric materials are used in the proposed device and corresponding parameters are calculated to study its behavior in drain current characteristics, electrical parameters, and analog parameters. The On current is increased by 150 % then the existing architectures. The net electric field is increased by a factor of 2. There is a significant increase in Transconductance of the device. The simulated models are verified using Silvaco TCAD in ATLAS simulator. [ABSTRACT FROM AUTHOR]