Search

Two types of gradient index liquid crystal micro lens array (LC MLA) are reported for the light-field camera application. The LC MLAs enabled us to capture both of compound-eye images to be refocused on the various positions with its depth information and clear 2D images without reconstruction.

We have developed a microlens array (MLA) that utilizes liquid crystal (LC) for switching between light field and normal picturing modes in the camera application. The gradient index (GRIN) profile in an LC layer was obtained by applying the electric field distribution between a pair of molded-and-buried concave and planar electrodes. The concave array was formed by the imprinting method with ultraviolet curing resin. An indium tin oxide layer was deposited on the concave array to make the transparent electrode, which was then buried and flattened with the same resin. The transparency and flatness of the electrodes and resin keep the image quality high without applied voltage in the normal mode, and the electrode in the concave shape causes the LC layer to have a GRIN profile that acts as a MLA when voltage is applied in the light-field mode. The fabricated MLA showed suitable mode-switching operations by applying (for light-field mode) or not applying (for normal mode) a voltage of ±4 V.

A pseudo-SoC technology incorporating heterogeneous devices has been developed by applying a wafer-level system integration technology. The pseudo-SoC is set up to realize one microchip with heterogeneous devices made by using individual processes for epoxy resin, insulating layer and redistribution layer, respectively. The individual heterogeneous devices are embedded in the epoxy resin to reconfigure the integration wafer. As the insulating layer and redistribution layer are formed by semiconductor wafer process without interposer substrate, the pseudo-SoC enables integration density and signal transmission speed as identical to that of SoC. Also, as the commercial LSI devices and peripheral passive components are able to use for the system integration, the pseudo-SoC enables reduction of time-to-market as identical that of SiP. This paper describes the heterogeneous devices integration technologies and focuses on the pseudo-SoC that overcomes the limitation of system integration and provides the complementary advantages of SiP and SoC with various applications.

We propose a new detecting method of vacuum pressure utilizing reference cells with the similar structure as pixels in the IR(infrared radiation) image sensor of which the sensitivity is greatly depended on the vacuum pressure in the sensor package. This method showed the excellent correlation between the vacuum pressure and output voltage without any additional pirani gauge requiring readout circuit which is generally utilized to detect the vacuum pressure. The proposed method is understood to realize the detection of the package vacuum pressure with detecting infrared radiation as an IR image sensor.

We have analyzed the dominant noise sources in the driving circuit of an uncooled infrared radiation focal plane array fabricated on a silicon-on-insulator (SOI) substrate by 0.35µm CMOS technology and bulk- micromachining. We found no noise property of SOI-MOSFET inferior compared to those of NMOSs formed on SOI and bulk substrate, respectively. In addition, we reduced the total noise of the sensor chip by designing the current source NMOS sufficiently large, and optimized the operating current of pixel pn-junctions.

We have been developing the pseudo-SOC technology for one-chip module integration of heterogeneous devices that realizes high electrical performance and high density of devices embodying the advantages of both SOC technology and SIP technology. Especially, this technology is available for MEMS-LSI integration. We developed a 0.2mm-thickness one-chip module integrating a MEMS shock sensor and a sensing amplifier LSI by applying this technology. The MEMS shock sensor and the sensing amplifier LSI were connected by high-rigidity epoxy resin optimized the material constants to reduce the stress and the warpage resulting from resin shrinkage due to curing. Then the planar insulating layer and the redistributed conducting layer were formed on it for the global layer. The MEMS shock sensor was preformed to be modularized with a glass cap. Electrical contacts were achieved by bonding of Au bumps on the MEMS fixed electrodes and via holes filled with Ag paste of the glass cap. Functional performance was confirmed by obtaining signal corresponding to the reference signal of the pick-up sensor. Furthermore, stress analysis was performed using the FEM model simulation considering the resin shrinkage.

We have developed a micro local heating device for bio applications using micro-electro-mechanical systems (MEMS) technology. The device has a two-dimensional microdish array, which contains a series of diodes. The microdish array is fabricated by means of a combination of complementary metal–oxide–semiconductor (CMOS) technology and MEMS post-processing. The microdish array has a miniature cavity for thermal separation from substrate. These microdish arrays can be generated by a large forward current based on Joule heating. In this paper, we describe the direct heating of the whole microdish array and just an arbitrary portion of the microdish consisting of the device by Joule heating. In the localized selective heating, the highest temperature, 62.6 °C, from all the dishes was confirmed. More than twice the heat effect was achieved in heating an arbitrary portion compared with heating the whole microdish.

This paper reports the implementation of a silicon-based infrared (IR) multiband pass filter (BPF) on an uncooled microbolometer IR focal plane array (IR-FPA), both of which are fabricated by the standard CMOS process. IR spectroscopy has been widely used as a sample identification technique, exploiting the fact that each molecule structure has a unique spectral feature. Using IR-BPF and IR-FPA, a low-cost and compact IR-spectral imaging system is realized. The microbolometer IR-FPA exhibits broad spectral response sufficient to cover the IR-region from the mid-infrared (3 µm) to far-infrared (8 µm∼), which is broader than the coverage of conventional non-silicon-based photodetectors such as mercury cadmium telluride. Single-band images of invisible gases such as ethanol vapor and CO2 in breath are obtained with the IR-FPA. For multiband imaging, a guided-mode resonance IR filter is fabricated by patterning aluminum (Al) layer of 100 nm thickness on a silicon-on-insulator wafer. Measured peak transmittance wavelengths (λc) of square and hexagonal Al array are compared with results of rigorous coupled-wave analysis, as a function of the Al pattern period. The λc of 3.3, 3.9, and 4.4 µm are obtained at the pattern period of 1.8, 2.4, and 2.8 µm for the square array. In all cases, the λc slightly decreases for the hexagonal array. The full-width at halfmaximum (FWHM) of each filter is approximately 200 nm for the λc of 4.4 µm, 400 nm for λc of 3.3 µm.

A new optical microphone was developed based on complementary metal–oxide–semiconductor (CMOS)—microelectromechanical systems (MEMS) micromachining techniques. One of the outstanding features of this microphone is that the output signal is obtained as a vibration of diffraction pattern from the grating diaphragm which is electrostatically actuated. The electronic signal actuates the diaphragm at an arbitrary frequency by electrostatic force and simultaneously detects sound using light waves. From the verification experiment, this microphone was able to perform advanced functions, such as the frequency selection and the detection of the sound wave phase information. Based on the theoretical model, experimental data are discussed and potential applications of this microphone are also proposed.

We have developed a low-cost uncooled infrared radiation focal plane array (FPA) requiring no thermoelectric cooler (TEC), which has 320 x 240 detection pixels with 22 um pitch. The silicon single-crystal series p-n junction diodes and the low-noise readout circuit on the same SOI wafer fabricated by 0.13 um CMOS technology were utilized for infrared (IR) detection. The temperature dependence in the readout circuit was eliminated by correlated double sampling (CDS) operation with reference pixel that was insensitive to infrared radiation. In order to reduce the temperature dependence, we improved the reference pixel and the readout circuit. Although the reference pixels should be completely insensitive to IR radiation, prior reference pixels showed measurable sensitivity. The improved reference pixel was formed by partially releasing with bulk-micromachining and was verified to be insensitive to IR radiation by an object of 400°C. The readout circuit had a differential amplifier instead of a singletransistor amplifier and an analog-to-digital converter (ADC). In each portion, CDS was applied to reduce temperature dependence. The first CDS operation was used for eliminating the pixel output variation and the second operation was used for canceling the variation of the differential amplifier. The output variation referred to input was reduced to 1/30 compared with that of the prior circuit. Moreover, the residual variation of output voltage was reduced by CDS operation in ADC and stable output data was obtained with ambient temperature variation. With these improvements, the sensitivity variation of the FPA was improved to 10% in the range of -30 degrees to 80 degrees and noise equivalent temperature difference (NETD) of 40 mK was achieved.

We have developed an uncooled infrared radiation focal plane array (IR-FPA) with 22 μm pitch and 320 × 240 pixels utilizing silicon p-n junction diodes, which were fabricated by 0.13 μm CMOS technology and bulk-micromachining. The thermal time response of cells was lowered to be 16msec by reduction of thermal capacity of cells. In addition to increase the sensitivity of cells by extending the length of supporting beams, p-n junction diode was scaled down as small as 20% in area compared to previous one. Micro-holes were formed in the cell to reduce only thermal capacity, which were negligibly small compared to incident IR wavelength. This method needs no additional process step and is considered as suitable for low cost and mass-productive IR-FPA.

A flexible pseudo-SoC which integrates electrostaticMEMS and its driver CMOS-LSI for mobile electronics device applications has been developed. From the experiments, the pseudo-SoC process has succeeded to form a fine-pitch on-chip global layer on the MEMS and CMOS-LSI embedded in the epoxy resin and to realize total thickness of 100µm. This paper reports the pseudo-SoC that overcomes the limitation of system integration and provides the complementary advantages of SiP and SoC within the results of a highly-integrated flexible pseudo-SoC incorporating electrostatic MEMS and its driver CMOS-LSI for mobile electronics applications.

We have developed a 22um pitch and 320 × 240 pixel uncooled infrared radiation focal plane array on the silicon-oninsulator (SOI) substrate by means of 0.35um CMOS technology and bulk-micromachining. For IR detection, we use silicon single-crystal series p-n junctions that can realize high uniformity of sensitivity and low voltage drift. The supporting beam shrinkage enabled the pixel pitch shrinkage from 32um to 22um and 320 × 240 pixel number without deteriorating NETD. We also developed a SOI low-noise CMOS readout circuit that can calibrate chip temperature and introduced a noise canceling digital algorithm to cancel the reset noise generated in the readout circuit. The dominant noise source, SOI MOSFET noise, was decreased by optimizing the gate design. Finally the FPA has realized noise equivalent temperature difference (NETD) of 0.12K and requires no thermo-electric cooler (TEC) and is mounted on a low-cost standard ceramic package.

The MEMS-LSI integration technologies that have been reported are mainly implemented for monolithic integrated System on Chip (SoC) by applying the advantages of process compatibility between MEMS and CMOS LSI [1]. However, it has been impossible to integrate them in the case that MEMS and standard CMOS processes are incompatible. Furthermore, many MEMS-LSI integration technologies applying System in Package (SiP) technology with the interposer substrate to realize electronics devices have been reported. However, using SiP technology, it has not been possible to achieve high integration density comparable to that of monolithic integrated SoC because the interposer substrate occupies a large area in SiP. Accordingly, development of an advanced MEMS-LSI integration technology to realizing highly integrated SoC incorporating MEMS devices is required [2].

We have developed a 32 μm pitch and 160 × 120 pixel uncooled infrared radiation focal plane array (IRFPA) on SOI by 0.35 μm CMOS technology and bulk-micromachining. For IR detection, we use silicon single crystal series p-n junctions which can realize high uniformity of temperature coefficient and low voltage drift. We have also developed a low-noise CMOS readout circuit on the same SOI which can calibrate the substrate temperature variation in every frame period, comparing two types of pixels, a bulk-micromachined infrared detection pixel and a non-micromachined reference pixel. Then the FPA requires no thermo-electric cooler (TEC) and is mounted on a low-cost standard ceramic package for the consumer products market.

We report monolithic integration of MEMS (micro electro mechanical systems)actuators and high-voltage driver circuits into a silicon chip. Driver circuits of up to 40 V were prepared on an 8-mum thick SOI (silicon-on-insulator) wafer by the DMOS (double-diffused metal oxide semiconductor) processes, after which MEMS electrostatic actuators were integrated into the identical SOI layer by post-processing using DRIE (deep reactive ion etching). This technique opens up a new way of high-voltage ASIC (application specific integrated circuit)for MEMS designer. We investigated the process compatibility between the integrated circuits and MEMS. Studies are made on (1) the design and fabrication of the MEMS-circuit electrical interconnection and (2) the effect of dry-etching plasma on the circuit characteristics in MEMS DRIE process.

This paper presents a pitch tunable grating light valve integrated with high-voltage (40 V) driver circuits that target for image projection display devices. In our work, optical light angle is modulated by changing the period of the MEMS grating pixel by means of electrostatic actuation. In addition, we developed a MEMS grating light valve with a skewed angle for elimination of the inter-spot crosstalk. The skewed gratings were found to spread the +/- 1st order diffraction off the axis. Optical diffraction angles of 6.6 degrees (OFF-state) and 3.3 degrees (ON-state) were obtained.

We present a newly developed technology platform for monolithically integrating high voltage DMOS (double-diffused metal oxide semiconductor) circuits upwards of 40 V with bulk-micromachined actuators (XY-stage) using both the top and the bottom surfaces of an SOI (silicon-on-insulator) wafer. Driver circuits were pre-fabricated on an 8-mum-thick SOI wafer by the DMOS processes, after which MEMS electrostatic actuators were integrated into the identical SOI layer as well as the substrate by post-processing using DRIE (deep reactive ion etching). Thanks to this monolithic integration technique, multi-layered high-aspect-ratio structures were produced.

This paper presents a monolithic integration technique of MEMS grating light valves with high-voltage (40 V) driver circuits that target for image projection display devices. Driver circuits were prepared on an 8-mum-thick SOI (Silicon-on- Insulator) wafer by the DMO S (Double-diffused Metal Oxide Semiconductor) processes, after which the MEMS grating were integrated in the identical SOI layer by post-processing using the DRIE (Deep Reactive Ion Etching). In our work, optical light angle is modulated by changing the period of the MEMS grating pixel by means of electrostatic actuation. Optical diffraction angles of 6.6deg (OFF-state) and 3.3 deg (ON-State) were obtained with drive voltage of 0 V and 40 V, respectively.

This article consists of a collection of slides from the author's conference presentation on micro manipulator arrays for nano-bioelectronic applications. Some of the specific topics discussed include: the special features of a micro manipulator array using a novel MEMS-based structures; the demonstration of direct physical control of the interaction between yeast cells and silica particles in liquid for the first time; the adsorption of the particle to the cell was demonstrated using vibrational energy; and Joule heating energy according to external excitation. These results of these tests show a potential impact in medical fields such as physical antibiotics and cell treatments and next generation bio-electronics schemes.

In this paper we proposed a method by which nanoparticles can be selectively injected based on mechanical vibrations, thermal heating, and electromagnetic waves. We have developed a nanoparticle manipulator using a MEMS based structure. We also demonstrated direct physical control of the interaction between yeast cells and nanoparticles in liquid for the first time. In this research, our aim is to develop human clinical devices designed to obtain personal data in order to select the suitable types of nanoparticles for tailor-made medical treatments. These results can have a potential impact in medical fields such as physical antibiotics and cell treatments

Quantitative gene expression analysis, based on an electrochemical DNA-detection method uses immobilized DNA probes on Au electrodes with diameters from 200mum to 2mum. Cyclic voltammetry is used to measure anodic current from the intercalators. The 25times3mm2 IC, fabricated in 1mum 2M CMOS, contains 40 electrodes, 1600 transistors and dissipates 150mW at plusmn3.3V

In this paper, we report monolithic integration of MEMS (micro electro mechanical systems) actuators and high-voltage driver circuits into a silicon chip. Driver circuits of up to 40 V were prepared on an 8-/spl mu/m-thick SOI (silicon-on-insulator) wafer by the DMOS (double-diffused metal oxide semiconductor) processes, after which MEMS electrostatic actuators were integrated into an identical SOI layer by post-processing using DRIE (deep reactive ion etching). This technique opens up a new way of high-voltage ASIC (application specific integrated circuit) for MEMS designer. As a prototype application model, we have developed microlens optical scanners and other elementary MEMS electrostatic actuators with multi-channel driver circuits.

We present a new conceptual active optical microphone based on complementary metal-oxide semiconductor (CMOS) - micro electro mechanical systems (MEMS) micromachining techniques. The diaphragm of the microphone has a diffracting grating fabricated by the CMOS process with only a small number of post-processes. The active microphone actuates the diaphragm on an arbitrary frequency by electrostatic force, and detects sound waves by the light waves. From the verification experiment result, this active microphone was able to perform advanced functions, such as the amplifier effect and the detection of phase information of sound waves.

This paper reports, for the first time, the development of 500 V, 3 A single chip inverter ICs. The chip size of the IC is 7.1/spl times/5.2 mm/sup 2/, which is only 30% larger than that of 500 A, 1 A inverter ICs. The chip size reduction has been realized by 35% improvement in lateral IGBT on-resistance and an optimized layout of LIGBT unit cells and bonding pads.

The breakdown voltage of a conventional SOI device is limited because it requires a thicker buried oxide as well as a thicker silicon layer. A new SOI device structure and its substrate are proposed to break through these constraints. The proposed new SOI is characterized by a SIPOS (Semi-Insulating POly-crystalline Silicon) layer inserted between the silicon layer and the buried oxide. Since the SIPOS layer effectively shields the influence of the substrate bias, 600 V breakdown voltage SOI diodes and lateral IGBTs were successfully realized using a 0.8 /spl mu/m SIPOS layer and 0.8 /spl mu/m buried oxide.

This paper reports, for the first time, the experimentally obtained electrical characteristics of lateral injection enhanced insulated gate bipolar transistors (LIEGTs) on SOI. It is shown that optimized LIEGTs have twice as large a current capability as LIGBTs and attain the same turn-off characteristics. These results show that LIEGTs are attractive for the output devices of high voltage power ICs.

A high voltage lateral MOS thyristor cascode switch on SOI was proposed. It consists of a high voltage MOS thyristor, a low voltage MOSFET and a pn diode. Excellent on-state and switching characteristics were numerically and experimentally obtained. The safe operating area (SOA) of SOI-Resurf devices were discussed.

In this paper, we have experimentally obtained, for the first time, 1200 V lateral diodes and MOSFETs on SOI. The SOI structure is characterized by a SIPOS layer inserted between the silicon layer and the buried oxide. It was found that the new SOI diode breakdown voltage is determined by the conventional bulk p-n junction theory and not by the resurf (reduced surface field) principle.

This paper compares, for the first time, the maximum controllable current, or SOA of three different diode structures with low efficiency emitters. Low anode emitter efficiency is achieved either by introducing n/sup +/ diffusions in the p-type anode region (n/sup +//p/sup +/ diodes), or by adopting a low surface concentration anode (p/sup -//p/sup +/ diodes), or by shallow p diffusion (shallow p/p/sup +/ diodes). It was found that the n/sup +//p/sup +/ diode was easily destroyed in the reverse recovery transient at a high temperature of 150/spl deg/C because of a parasitic n-p-n transistor action. The best optimization was found in p/sup -//p/sup +/ diodes. Shallow p/p/sup +/ diodes exhibited the same ruggedness, if the dose of the shallow p layer was optimized.

We report, for the first time, the development of 5 ampere multi-channel lateral IGBTs on SOI. The new LIGBTs are characterized by a plural number of parallel stripe poly-silicon gates and resultant plural number of channels, which enhances electron injection and attains a large current capability. The developed LIGBTs conduct current density over 120 A/cm/sup 2/ at the drain voltage of 3 V and simultaneously achieve a fall-time below 300 ns. The LIGBTs have excellent current capability and short circuit withstanding capability of DC 300 V with 500 A/cm/sup 2/ of drain current even at 200/spl deg/C.

Trench isolated 60 V BiCDMOS processes on bonded 2 /spl mu/m thick SOI, capable of integrating 60 V low on-resistance lateral DMOS, vertical npn and pnp, and an MPU have been developed. 200/spl deg/C high temperature operation has been demonstrated. The processes are completely compatible with the conventional 0.8 /spl mu/m rule CMOS processes, and are capable of integrating any existing library of MPUs, logic and analog circuits together with 6O V DMOS H bridges.

To promote the widespread use of light-field computational cameras, downsizing of the system is essential. This paper presents an 8.5 mm × 8.5 mm × 6.0 mm tiny compound-eye camera module based on the light field. The camera module is composed of a single-lens unit of a 63° field-of-view (FOV) diagonal, a microlens array (MLA) glued on an 8-Mpix color CMOS sensor (1/3.2” format), and a read-out substrate. The captured raw MLA image is capable of constructing a 26 000-resolution depth image and refocused 2-Mpix 2D RGB images. We also demonstrated that our “image height calibration” and “optical scoring” improved the accuracy of the measured depth and revealed it to be effective for wide-angle FOV optics, such as the lens unit used in our tiny camera module that has the potential for widespread application. Analysis of the depth accuracy proved that the measured depth accuracy with our camera was higher than 90% in the depth range from 5 to 50 cm at the image center.

We have developed a 22 µm pitch and 320 × 240 pixel uncooled IR (infrared) image sensor. For IR detection, we utilized single crystal silicon series p–n junctions, which were fabricated on a SOI (silicon on insulator) wafer utilizing 8 inch CMOS technology and MEMS processes. The p–n junctions were passivated with buried and laminated oxide layers from wet crystalline etching of the silicon substrate. The oxide layers were also utilized to absorb the IR radiation and to form supporting beams. The partially released pixels were utilized as thermal black pixels (TBs) instead of optical black pixels (OBs) for correlated double sampling. The IR image sensor utilizing TBs obtained a thermal image of the human body stably without the smearing phenomenon.

In this paper, we present a new directional acoustic transducer using complementary metal oxide semiconductor (CMOS)-micro electro mechanical system (MEMS) micromachining techniques. The diaphragm of the acoustic transducer has a diffraction grating fabricated by the CMOS process requiring only a small number of post processes. The MEMS-based optical acoustic transducer transfers the displacement signal of the diaphragm with a grating pattern to a photodetector, which detects the vibrational displacement of the diaphragm based on changes in optical intensity. The same space conditions for the front and rear surfaces of the diaphragm can be achieved easily in this optical acoustic transducer. This arrangement allows a high directionality without sensitivity for side-on sounds, because the front and rear pressures of the diaphragm are in phase. The directional characteristics of our prototype acoustic transducer were measured, and a high directivity (6 dB attenuation at 30 deg) was confirmed.

In the present paper, we propose high voltage lateral power metal-oxide-semiconductor field effect transistor (MOSFET) on silicon on insulator (SOI), using the pure 0.8 µm complementary metal-oxide-semiconductor (CMOS) processes without diffusion self-alignment. The measured specific on-resistance of the developed lateral power n-channel MOSFET (NMOSFET) was 100 m Ω·mm2 and breakdown voltage was 60 V. The fabricated device attains its on-resistance comparable to that of diffusion self-align MOSFET (DMOSFET). It also achieves high side switch operation by a reasonable cost, and can be integrated with Bipolar CMOS (BiCMOS) circuits and micro processing unit (MPU). Compatibility of the developed MOSFET to these low voltage circuits are demonstrated. Furthermore, we show that the MPUs and BiCMOS analog circuit on SOI is suitable for high temperature operation.