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High voltage BiCDMOS technology on bonded 2 μm SOI integrating vertical npn pnp, 60 V-LDMOS and MPU, capable of 200°C operation

Authors :
H. Mochizuki
Hideyuki Funaki
Akio C O Patent Divis Nakagawa
Y. Terazaki
Yoshihiro Yamaguchi
Yusuke Kawaguchi
Source :
Proceedings of International Electron Devices Meeting.
Publication Year :
2002
Publisher :
IEEE, 2002.

Abstract

Trench isolated 60 V BiCDMOS processes on bonded 2 /spl mu/m thick SOI, capable of integrating 60 V low on-resistance lateral DMOS, vertical npn and pnp, and an MPU have been developed. 200/spl deg/C high temperature operation has been demonstrated. The processes are completely compatible with the conventional 0.8 /spl mu/m rule CMOS processes, and are capable of integrating any existing library of MPUs, logic and analog circuits together with 6O V DMOS H bridges.

Details

Database :
OpenAIRE
Journal :
Proceedings of International Electron Devices Meeting
Accession number :
edsair.doi...........049e5d527ac1e7d662bd66c0c829d346
Full Text :
https://doi.org/10.1109/iedm.1995.499377