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Binary multiplication continues to be one of the essential arithmetic operations in digital circuits. Even though field-programmable gate arrays (FPGAs) are becoming more and more powerful these days, the vendors cannot avoid implementing multiplications with high word-lengths using embedded blocks instead of configurable logic. But on the other hand, the circuit's efficiency decreases if the provided word-length of the hard-wired multipliers exceeds the precision requirements of the algorithm mapped into the FPGA. Thus it is beneficial to use multiplier blocks with configurable word-length, optimized for area, speed and power dissipation, e.g. regarding digital signal processing (DSP) applications. In this contribution, we present different approaches and structures for the realization of a multiplication with variable precision and perform an objective comparison. This includes one approach based on a modified Baugh and Wooley algorithm and three structures using Booth's arithmetic operand recoding with different array structures. All modules have the option to compute signed two's complement fix-point numbers either as an individual computing unit or interconnected to a superior array. Therefore, a high throughput at low precision through parallelism, or a high precision through concatenation can be achieved.

The current technology in micro-and nano-electronics is insufficient to meet future demands for several applications. Most state-of-the-art solutions rely on so-called embedded technologies, which are both expensive and complex. One solution to the problem of integrating mixed technologies is the concept of 3D stacking. Our approach implements an epitaxial etch-stop layer for thickness control of the thinning process. Using this etch-stop layer, we can create a precise alignment of back-side vias to the landing pads in the first metal layer of the active CMOS, resulting in small via diameters and high connection densities between individual-layers of the 3D stack. Furthermore, we can use other materials, like GaAs (gallium arsenide), in combination with an epitaxial lift-off process. We use a copper-tin soldering process based on the solid-liquid interdiffusion (solid) process to create the electrical and mechanical connection between the single chip layers. Using this process, we created true multilayer stacks and tested them with respect to the static electrical properties of ohmic contacts and interchip vias. We directly incorporated these results in the design of test circuits that create tests for stuck-at failures of the interchip connections after stack assembly. This article presents a technology overview of how to achieve the goal in a 3D fabrication process. It also shows measurements for characterizing interconnects.

Implementing arithmetic-heavy applications such as filters or neural networks in FPGAs relies to a great extent on the realization of efficient multipliers. However, implementing high-precision multipliers only with configurable logic leads to a large lookup-table usage and considerable routing efforts. Thus, hard-wired multiplier blocks are embedded in modern FPGA devices in order to relieve the resources, but their word-length is still fixed to e.g. 18x18-bit in the Xilinx Virtex-IV DSP48 slices. In this paper, we describe our approach of creating configurable blocks suitable for multi-precision multiplication with a word-length that can be changed at runtime. We present a novel block-serial design that shows a 60 % area advantage over a fully parallel multiplier and also a larger structure that can be partitioned into several fully functional smaller multipliers working simultaneously in different configurations.

In this paper, a reconflgurable multi-precision Radix-4 Booth multiplier structure is presented. The reconfig- urable 8 x 8 bit multiplier unit can be cascaded to form a multiplier that can adapt to variable input precision requirements. The number of bits can be extended by concatenating more stages together. For example, four 8 x8 bit units can be used to build a 16 x 16 bit Booth multiplier. In our proposed architecture, the multiplier adapts to different bit-lengths by using external control signals. The performance of our reconflgurable multiplier are compared with a parallel array multiplier and a conventional Booth multiplier. The comparison is based on synthesis results obtained by synthesizing all multiplier architectures targeting a Xilinx FPGA. The overhead resulting from our reconfiguration scheme are also evaluated and compared to a conventional Booth and array multipliers.

Mask programmable gate arrays (MPGAs) are an attractive solution to reduce design cost and turnaround time in ultra-deep submicron technologies. Several design methodologies have been proposed in the recent years for converting an evaluated field-programmable gate-array (FPGA) prototype design into an MPGA. In this paper, we investigate a predefined regular routing architecture of an MPGA. The routing architecture is easily scalable. A simple model for the MPGA interconnect is presented which facilitates static timing analysis. We explain the difference of this interconnect with the FPGA interconnect. The resulting MPGA is implemented in 130nm. Circuit level simulations show that our model is accurate in terms of delay. The study presents tradeoffs with the placement and routing to reach timing closure. A special MPGA routing tool is used. The study shows that high number of tracks in the MPGA is area prohibitive, but with better timing closure.

Mask programmable gate arrays (MPGAs) see a growing importance because of the increase of design cost and turnaround times in ultra-deep submicron technologies which mostly impact ASICs. Several design methodologies have been proposed in recent years for converting an evaluated field-programmable gate-array (FPGA) prototype-design into an MPGA. An automatic conversion flow is essential to success. In this paper, we present a conversion flow for a look-up table-based (LUT-based) MPGA without applying re-synthesis but preserving the gate-level netlist and reusing the placement. The resulting flow has a special routing tool and buffer insertion algorithm for timing integrity. The experimental investigations use a commercial FPGA and industrial benchmarks.

In this paper, a comprehensive pharmacokinetic model for different insulin formulations including insulin Glargine is developed based on the model proposed by Trajanoski et al. (1993). Current models show limitations for insulin Glargine due to the appearance of an uncharacteristic peak in the concentration-time evolution of plasma insulin that does not coincide with real experimental data. This important limitation has been solved in this paper by introducing a new virtual insulin state called the bound state, in addition to the dimeric and hexameric ones. Trying to describe the retarded action of insulin Glargine, the modeling idea behind this approach is that immediately after the subcutaneous injection all the insulin resides in the bound state, and only then small amounts of insulin in the hexameric form disengage from the bound state. For the model evaluation different simulation results are compared. Using experimental data published by Lepore et al. (2000), the developed model turned out to be capable of at least qualitatively predicting the concentration-time profile of plasma insulin. Both exogenous insulin flow simulations and spatial diffusion simulations show the plausibility and correct implementation of the derived model. Considering all these simulation results, the here presented new pharmacokinetic model demonstrates to be able to reproduce real patient behavior simulating even complete insulin regimes including long-acting, intermediate and short-acting insulin formulations.

For high performance chips power noise issues become more prominent. In this paper power supply noise is damped with additional resistors in the impedance path between the package and the on-chip power distribution. Therefore, this path is split into several paths with different resistors. A distributed 2D signal line on-chip model in a simulated annealing schedule is utilized to find the appropriate resistors. The amount of noise reduction and the necessary voltage offset to overcome the additional IR drop has been investigated in several simulations. Further, the influence of splitting the power supply path only into very few different paths has been investigated.

In this paper a 2D signal line model is used to simulate the power distribution network (PDN). The proposed method uses an admittance function to model the frequency-dependent resistance and inductance in each direction. This admittance function can be gained directly by model order reduction from a partial element equivalent circuit (PEEC) model. Hence, it is possible to efficiently calculate the model parameters even for irregular PDNs. A fast transient simulation algorithm closely related to the finite-difference time-domain (FDTD) schemes is presented. The alternating-direction-implicit (ADI) method relaxes the time step for the simulation, because it is not limited by a stability criterion.

An analytical model is derived for capacitive coupled on-chip interconnect buses. If an estimation of the wire length is available, the driver output can be estimated using the load model and take coupling effects on the interconnect tree into account. The load is modeled as /spl pi/-network which depends on the first three moments of the exact admittance function of the bus system. Simulations with specterS have shown, that the model represents a good approximation for the driver load of a distributed interconnect bus tree. It is proven mathematically that the model remains passive.

Frequency synthesisers are the key to precise time, frequency and phase in communications transmitters and receivers as well as in radar pulse compression. Digital implementations such as direct digital synthesis (DDS) are frequently selected because of their inherent advantages. Limiting factors are the spurious frequencies, which are generated due to quantisation effects and an output frequency limited to less than half of the sampling frequency according to the sampling theorem and taking into account a realisable anti-image filter. The fundamental part of any DDS architecture is a periodically overflowing phase-accumulator generating linearly increasing phase values. In this paper we review an efficient self-timed highly-pipelined accumulator architecture implemented in GaAs MESFET technology.

Type-I diabetes mellitus patients can not produce the hormone insulin endogenously. As this hormone is necessary to control the blood sugar level, which is raised by eating, insulin must be delivered exogeneously. Delivering insulin exogeneously demands correct dosage to avoid an extremely high or low blood glucose level. Most patients are not able to administer the adequate insulin dose because they are not able to predict the evolution of their own glucose level after a meal. Therefore, a model of the glucose metabolism is of crucial interest to help patients to determine correct insulin doses. These models shall be capable of predicting the course of the blood glucose level for a couple of hours with reasonable precision. In this paper a computer aided assistance system for diabetes patients running on a mobile handheld device is presented. This assistance system mainly consists of a model of the glucose metabolism, implemented by a modified Elman net. The training is performed through the BPTT algorithm where the training data were generated with an analytical non-linear glucose metabolism model that is quite realistic but cannot be adapted to every single patient. The glucose metabolism process is defined by two inputs, injected insulin and ingested glucose, and one output, namely the blood glucose. Due to the fact that metabolic processes in general have large time constants this process is characterized by the fact that the current net output, that is the blood glucose level, heavily depends on data that are not present in the current input layer any more. The Elman net's context-layer is capable of storing this information. Simulation results demonstrate that the output of this type of neural network closely follows the reference.

Code division multiple access (CDMA) will be an important part of 3rd generation mobile communication systems worldwide. Besides its many advantages, CDMA has the disadvantage that CDMA systems are interference limited. However, this limitation can be overcome by proper multiuser detection (MUD). We propose a MUD based on recurrent neural networks (RNN). This algorithm provides a performance which is close to the optimum MUD, while keeping the computational complexity low. Furthermore, the regular structure of the algorithm facilitates a hardware (HW) implementation utilizing distributed computation. The HW platform we target at are field programmable gate arrays (FPGA). Compared to application specific integrated circuits, FPGAs allow a much faster and more flexible hardware implementation. We have implemented the algorithm with a fixed point arithmetic and investigated the minimum number of binary digits required so that the performance of the algorithm does not degrade substantially. Furthermore an efficient implementation of the tanh nonlinearity is presented.

The efficiency of self-timed design styles is evaluated for semi-systolic carry-save architectures. After a classification of the various design options a comparison is carried out for a multiplier considering throughput rate, area consumption and power dissipation. Among the design styles that are investigated in detail is a new pipeline scheme for self-timed circuits. In the sequel it is referred to as four-phase micropipeline with one operation per cycle. It turns out, that the highest throughput rates are obtained for this scheme. For the comparison an optimization procedure has been applied for the choice of the transistor widths in the control logic. The procedure is described briefly. Optimization results for different loads and cycle-times are used to derive rules for the design of micropipelines.

A figure of merit for the comparison of different types of logic circuits on the basis of inverters is presented. This figure of merit-the minimum energy per logic operation-is equal to the product of the time period necessary for carrying out a logic operation times the power which is fed into the inverter during this time period. Methods for the determination of these terms by ring oscillator measurements and model calculations are considered. In contrast to the so-called `delay-power' product, these newly defined terms are independent of the kind of measurement, as for example the number of stages of the ring oscillator. Thus the minimum energy per logic operation is an intrinsic figure of merit which allows a qualitative comparison of different types of logic circuits on a physical basis.

Todays CMOS technology is reviewed with respect to process architecture, acquired CMOS specific device know-how, design and applications. The process and device related problems of further miniaturization are discussed. Trends of innovative device design and technology concepts able to overcome these problems are summarized. Finally examples are given for future CMOS applications.

A new solution for a linear imager with antiblooming is presented. The overload-generated charge spills over a potential barrier into a CCD, called overflow CCD, wherein that charge is transferred to an output and eliminated. The information charge, integrated under the sensor electrodes, is transferred across this overflow CCD into a second CCD, called the readout CCD. The principle of the operation of this imager is explained and preliminary experimental results are given.

A technique affording recognition of all stuck-at faults and shorts within a PLA will be presented; each matrix transistor is addressed via shift registers. PLA specific problems of high fan-in are solved with an area overhead of less than 20%.

Good agreement between theory and measurements is obtained for the spectral density of transfer noise which is the dominant noise source in a SCCD. Within a frequencyband small compared to the baseband of the CCD the achievable signal-to-noise ratio S/N is limited by the noise power in that small frequency range and not by the mean square value. Our considerations show that the spectral density of noise power of a CCD is inverse proportional to the clock frequency f C . Therefore increasing f C improves the S/N-ratio and enhances the performance of the CCD in band-limited analog communication systems.

If a CCD low-pass filter is used for antialiasing, a higher data rate is necessary at the input compared to the output. This difference in the data rate is used to increase the signal-to-noise ratio. By adding a given number of consecutive charge packets at the output stage, the output data rate can be reduced until the Nyquist theorem for the output signal is violated. By summing up those charge packets, the signal is added arithmetically whereas the noise, not being correlated, is added geometrically. This results in an improvement of the S/N ratio equal to the number of charge packets added.

A new principle for a c.c.d. transversal filter with parallel inputs is shown. Using this approach, no differential output amplifier is necessary. Design considerations of a device successfully tested are reported and the first measured results are compared with theoretical predictions.

The influence of transfer inefficiency on the spatial resolution of linear c.c.d. imagers is discussed. For a new imager concept, the quadrilinear imager which was reported elsewhere, this m.t.f. is derived and compared with that of already known imagers.

ISBN: 07298-0610-3; The purpose of this paper is to propose a design technique for improving the resistance of the Quasi Delay Insensitive (QDI) Asynchronous logic against Differential Power Analysis Attacks. This new design method exploits the properties of the QDI circuit acknowledgement signals to introduce temporal noises which enable to randomly desynchronize the data processing time. The efficiency, in terms of DPA resistance, of this design technique is formally presented and analyzed. Electrical simulations performed on a DES crypto-processor in order to evaluate the relevancy of the approach, shows a drastic reduction of the DPA peaks, so that to increase the complexity of a DPA attack on QDI asynchronous logic.