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Energy per logic operation in integrated circuits: definition and determination
- Source :
- IEEE Journal of Solid-State Circuits. 11:657-661
- Publication Year :
- 1976
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 1976.
-
Abstract
- A figure of merit for the comparison of different types of logic circuits on the basis of inverters is presented. This figure of merit-the minimum energy per logic operation-is equal to the product of the time period necessary for carrying out a logic operation times the power which is fed into the inverter during this time period. Methods for the determination of these terms by ring oscillator measurements and model calculations are considered. In contrast to the so-called `delay-power' product, these newly defined terms are independent of the kind of measurement, as for example the number of stages of the ring oscillator. Thus the minimum energy per logic operation is an intrinsic figure of merit which allows a qualitative comparison of different types of logic circuits on a physical basis.
- Subjects :
- Diode logic
Diode–transistor logic
Pass transistor logic
Computer science
Depletion-load NMOS logic
Integrated circuit
Ring oscillator
Topology
law.invention
law
Electronic engineering
Figure of merit
Electrical and Electronic Engineering
Pull-up resistor
NMOS logic
Logic optimization
Register-transfer level
Adiabatic circuit
Digital electronics
Sequential logic
business.industry
Logic family
Logic level
Emitter-coupled logic
Resistor–transistor logic
Integrated injection logic
Logic gate
Inverter
Three-state logic
business
Asynchronous circuit
Subjects
Details
- ISSN :
- 00189200
- Volume :
- 11
- Database :
- OpenAIRE
- Journal :
- IEEE Journal of Solid-State Circuits
- Accession number :
- edsair.doi...........571003e568c9cbc3273f1a29fced6b00
- Full Text :
- https://doi.org/10.1109/jssc.1976.1050795