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Improving the brightness of single-photon sources by means of optically resonant nanoantennas is a major stake for the development of efficient nanodevices for quantum communications. We demonstrate that nanoxerography by atomic force microscopy makes possible the fast, robust and repeatable positioning of model quantum nanoemitters (nitrogen-vacancy NV centers in nanodiamonds) on a large-scale in the gap of silicon nanoantennas with a dimer geometry. By tuning the parameters of the nanoxerography process, we can statistically control the number of deposited nanodiamonds, yielding configurations down to a unique single photon emitter coupled to these high index dielectric nanoantennas, with high selectivity and enhanced brightness induced by a near-field Purcell effect. Numerical simulations are in very good quantitative agreement with time-resolved photoluminescence experiments. A multipolar analysis reveals in particular all the aspects of the coupling between the dipolar single emitter and the Mie resonances hosted by these simple nanoantennas. This proof of principle opens a path to a genuine and large-scale spatial control of the coupling of punctual quantum nanoemitters to arrays of optimized optically resonant nanoantennas. It paves the way for future fundamental studies in quantum nano-optics and toward integrated photonics applications for quantum technologies.

International audience; The tremendous demand for low-cost, low-consumption and high-capacity optical transmitters in data centers challenges the current InP-photonics platform. The use of silicon (Si) photonics platform to fabricate photonic integrated circuits (PICs) is a promising approach for low-cost large-scale fabrication considering the CMOS-technology maturity and scalability. However, Si itself cannot provide an efficient emitting light source due to its indirect bandgap. Therefore, the integration of III-V semiconductors on Si wafers allows us to benefit from the III-V emitting properties combined with benefits offered by the Si photonics platform. Direct epitaxy of InP-based materials on 300 mm Si wafers is the most promising approach to reduce the costs. However, the differences between InP and Si in terms of lattice mismatch, thermal coefficients and polarity inducing defects are challenging issues to overcome. III-V/Si hetero-integration platform by wafer-bonding is the most mature integration scheme. However, no additional epitaxial regrowth steps are implemented after the bonding step. Considering the much larger epitaxial toolkit available in the conventional monolithic InP platform, where several epitaxial steps are often implemented, this represents a significant limitation. In this paper, we review an advanced integration scheme of AlGaInAs-based laser sources on Si wafers by bonding a thin InP seed on which further regrowth steps are implemented. A 3 µm-thick AlGaInAs-based MutiQuantum Wells (MQW) laser structure was grown onto on InP-SiO2/Si (InPoSi) wafer and compared to the same structure grown on InP wafer as a reference. The 400 ppm thermal strain on the structure grown on InPoSi, induced by the difference of coefficient of thermal expansion between InP and Si, was assessed at growth temperature. We also showed that this structure demonstrates laser performance similar to the ones obtained for the same structure grown on InP. Therefore, no material degradation was observed in spite of the thermal strain. Then, we developed the Selective Area Growth (SAG) technique to grow multi-wavelength laser sources from a single growth step on InPoSi. A 155 nm-wide spectral range from 1515 nm to 1670 nm was achieved. Furthermore, an AlGaInAs MQW-based laser source was successfully grown on InP-SOI wafers and efficiently coupled to Si-photonic DBR cavities. Altogether, the regrowth on InP-SOI wafers holds great promises to combine the best from the III-V monolithic platform combined with the possibilities offered by the Si photonics circuitry via efficient light-coupling.

International audience; A versatile industrial recipe of transferring nitride microelectronic components such as micro-electromechanical systems (MEMS) onto flexible and stretchable substrates is demonstrated. This method bypasses difficulties of temperature-related processing, and is applicable to large-scale and mass production. The technological process of fabrication is presented along with its underlying structural and radio-frequency characterizations. In particular, the Raman strain shifts of aluminum nitride (AlN) thin films are determined for uniaxial and biaxial mechanical deformations. The transferring process onto polymer is also demonstrated by an adhesive bonding of AlN-based MEMS onto a 200 mm silicon (Si) wafer. The devices microstructure is assessed using X-ray before and after transferring, as well as their electrical radio-frequency (RF) features when on Si and polymer substrates. Then, RF measurements are also performed on the transferred and flexible devices; some in their relaxed states, and others in an in situ manner under an increasing macroscopic strain. It is shown that bulk acoustic wave resonator MEMS are fully functional even under 12% uniaxial stretching of the substrate.

The LHCb VELO Upgrade I, currently being installed for the 2022 start of LHC Run 3, uses silicon microchannel coolers with internally circulating bi-phase \cotwo for thermal control of hybrid pixel modules operating in vacuum. This is the largest scale application of this technology to date. Production of the microchannel coolers was completed in July 2019 and the assembly into cooling structures was completed in September 2021. This paper describes the R\&D path supporting the microchannel production and assembly and the motivation for the design choices. The microchannel coolers have excellent thermal peformance, low and uniform mass, no thermal expansion mismatch with the ASICs and are radiation hard. The fluidic and thermal performance is presented., 31 pages, 27 figures

Si

Recent applications require vertical chip stacking to increase the performance of many devices without the need of advanced node components. Image sensors and vision systems will embed more and more smart functions, for instance, image processing, object recognition, and movement detection. In this perspective, the combination of Cu-to-Cu direct hybrid bonding technology with Through-Silicon-Via (TSV) will allow 3D interconnection between pixels and the associated computing and memory structures, each function fabricated on a separate wafer. Wafer-to-wafer hybrid bonding was achieved with multi-pitch design—1–4 µm—of single levels of Cu damascene patterned on 300 mm silicon substrates. Defect-free bonding, as far as the extreme edge of the wafer, was demonstrated on a stack with three wafers. Middle wafers thinning was done with grinding only and with a thickness uniformity (TTV)

International audience; Quantum nano-optics aims at transposing the concepts of quantum optics at the nanoscale. In this context, nitrogen-vacancy color centers in nanodiamonds are particularly interesting sources as they emit single photons one by one with a broad spectral distribution between 600 and 800 nm. We deposit such quantum emitters at the extremities of silicon nanowires and analyze the effects of this interaction via spectrally resolved confocal microscopy. We demonstrate that the single photon emission can be guided over several microns under conservation of their quantum statistics, and with efficiencies of up to 15 %.n We show that the silicon nanowires can be used as spectral filters for the quantum emission. Numerical simulations are in very good agreement with experiments, and indicate that the modal landscape of these nano-waveguides and the according coupling efficiencies with quantum emitters can be designed such that only light from emitters of specific orientations is efficiently guided through the nanowire, enabling a unique quantum state selectivity at a micrometer length scale. Our work opens the door to a genuine modal control of single photon transfer in subwavelength nanowaveguides, paving the way to future fundamental studies and towards integrated and multi-wavelength photonics applications in quantum nano-optics.

We report the resonantly enhanced radiative emission from a single SiGe quantum dot (QD), which is deterministically embedded into a bichromatic photonic crystal resonator (PhCR) at the position of its largest modal electric field by a scalable method. By optimizing our molecular beam epitaxy (MBE) growth technique, we were able to reduce the amount of Ge within the whole resonator to obtain an absolute minimum of exactly one QD, accurately positioned by lithographic methods relative to the PhCR, and an otherwise flat, a few monolayer thin, Ge wetting layer (WL). With this method, record quality (Q) factors for QD-loaded PhCRs up to Q similar to 105 are achieved. A comparison with control PhCRs on samples containing a WL but no QDs is presented, as well as a detailed analysis of the dependence of the resonator-coupled emission on temperature, excitation intensity, and emission decay after pulsed excitation. Our findings undoubtedly confirm a single QD in the center of the resonator as a potentially novel photon source in the telecom spectral range.Published by Optica Publishing Group under the terms of the Creative Commons Attribution 4.0 License. Further distribution of this work must maintain attribution to the author(s) and the published article's title, journal citation, and DOI.

Direct bonding energy relates to the well-known “strength” or “toughness” of direct bonding interfaces. It is the energy needed to separate two bonded surfaces. Its evolution with the post bonding annealing temperature is an important parameter closely linked to the fundamental direct bonding mechanism [1]. There are different ways of modifying the bonding energy and especially to increase it at low annealing temperatures. Plasma activation, chemical mechanical polishing (CMP) are for instance well known surface preparations that enhance the bonding energy at temperatures below 500°C [2]. Usually, for hydrophilic direct bonding, surfaces have to meet various specifications. A small high frequency roughness, a low nanotopology amplitude, a small wafer deformation, no particle contamination and a good hydrophilicity are mandatory to obtain spontaneous bonding at room temperature without any pressure [3, 4]. Moreover, the surface cleanliness in terms of hydrocarbon contamination is also very important to avoid bonding interface defectivity during the post bonding annealing. However, in this study, an intentional organic surface contamination will be shown to have a positive impact on direct bonding energy. An amino-alcohol molecule (N,N-diéthyléthanolamine also called DEAE) is sent vapor deposited on the surface of 200 mm silicon oxide or silicon. In an airtight reactor, 100 ml of water with different DEAE concentrations yield different DEAE saturated atmospheres in equilibrium with the liquid phase. As fast as possible, two wafers are loaded in the reactor and left there for different exposure times. Then, wafers covered with 145 nm of thermal silicon oxide surfaces are bonded just out of the reactor and annealed at different temperatures, for direct bonding energy measurements in an anhydrous atmosphere. As shown in figure 1a, different exposure times from 15 s up to 5 min to pure DEAE saturating vapor give almost the same bonding energy values. To have surfaces in good equilibrium with the reactor atmosphere, 5 min. of exposure time is selected to test various liquid DEAE concentrations. As shown on figure 1b, with the smallest tested concentration (2%) in the liquid phase, the direct bonding energy increases by more than 70% at 300°C compared to a reference bonding. Moreover, no bonding defect could be detected by acoustic microscopy. A positive impact of DEAE on silicon to silicon oxide bonding will also be shown. As silicon oxide direct bonding involves water oxide hydrolysis [1], a mechanism could be proposed to explain the beneficial impact of DEAE. Indeed, it is known that a high pH solution can enhance the silicon oxide hydrolysis [5]. As this molecule is very hydrophilic due to its alcoholic group, this molecule can be chemically adsorbed on a hydrophilic surface and can then be trapped at the bonding interface. After bonding, this molecule can increase the trapped water pH, enhancing the silica hydrolysis at the direct bonding interface and yielding higher bonding energies at low temperatures. As organic contamination is known to be detrimental for direct bonding, high concentration on the surface might be an issue. This should be the reason why a low concentration is more interesting. REFERENCES [1] F. Fournel, C. Martin-Cocher, D. Radisson, V. Larrey, E. Beche, C. Morales, P.A. Delean, F. Rieutord, and H. Moriceau, ECS J. Solid State Sci. Technol. 4, P124 (2015). [2] F. Fournel, H. Moriceau, C. Ventosa, L. Libralesso, Y.L. Tiec, T. Signamarcheix, and F. Rieutord, ECS Trans. 16, 475 (2008). [3] V. Larrey, G. Mauguen, F. Fournel, D. Radisson, F. Rieutord, C. Morales, C. Bridoux, and H. Moriceau, ECS Trans. 75, 145 (2016). [4] K.T. Turner, Wafer Bonding: Mechanics-Based Models and Experiments, Massachusetts Institute of Technology, 2004. [5] B.C. Bunker, Journal of Non-Crystalline Solids 179, 300 (1994). Figure 1

In this work, we present an advanced heterogeneous integration scheme which consists in integrating a thin InP layer by wafer-bonding onto a silicon wafer (InPoSi) on which a regrowth step of III-V materials is implemented. Vertical p-i-n AlGaInAs lasers obtained from a single Selective Area Growth (SAG) step on InPoSi were fabricated. Thanks to SAG, the AlGaInAs-MQW structures successfully cover a PL range of 160 nm in the C+L band. Based on these structures, a 5- channel laser array was fabricated. The latter successfully covers a 155 nm-wide spectral band from 1515 nm to 1670 nm with a maximum output power of 20 mW under continuous-wave regime at 20°C. High thermal stability up to 70°C is demonstrated with a characteristic temperature of 69°C for the lasers emitting from 1515 nm to 1600 nm.

The manufacturing of heterostructures is interesting in fields such as photonics(1), solar energy production(2) and quantum technologies(3). This paper, dedicated to germanium on silicon heterostructure manufacturing and stress engineering, builds up on Ref. (4) findings. We are using the differences in terms of coefficients of thermal expansion (CTE) between germanium and silicon, to induce a tensile stress in a thin germanium layer transferred by the Smart CutTM [1] technique onto a silicon substrate. In this approach, a bulk germanium wafer is directly bonded on a bulk silicon wafer, using surface activated bonding (SAB)(5,6). Process integration advantages are the low defect density of bulk germanium and the tensile stress that can be tuned using the bonding temperature. The adherence of SAB was high during bonding at relatively high temperatures (~250°C). Without any further heat treatment, the adherence was found to be 3500mJ/m2 by the double cantilever beam method (under prescribed displacement control and in an anhydrous atmosphere). This remarkable adherence prevented the Ge/Si heterostructure from sliding, debonding and cracking (7). The CTE difference could thus generate a large amount of tensile stress during the heterostructure cooling and splitting steps. First of all, using finite elements simulation, a model was designed to predict the bow and the in-plane internal stress after bonding and cooling of the heterostructure. Thanks to it, we could also evaluate those two values after layer transfer (splitting step). This numerical approach was more accurate than the former analytic method (Timoshenko), which did not include the non-linearity of CTE with temperature and for large displacements. Figure 1 shows the bow and the in-plane stress expected for a bonding at 250°C of, respectively, a Si/Si homostructure (Figure1.a) and a strained Ge/Si heterostructure (Figure1.b), when cooled down to room temperature. The former is flat while the bow of the latter is large indeed. Then, based on indications collected from simulations, we performed the bonding of a Si/Si homostructure in an EVG®ComBond® at 250°C. The same bonding conditions were used for an implanted germanium on silicon heterostructure. As shown in Figure 2, both bond pairs exhibited a bow close to that from FE simulations. After that, a splitting step was carried out, resulting in a thin germanium film on a silicon wafer (200mm), as shown in Figure 3. The film was transferred almost to the whole surface. The bow after splitting was of 10µm, a value not so far from the simulated value of 28.6 µm. As far as tensile stress was concerned, we used X-Ray Diffraction to gain access to the lattice parameter deformation and thus the tensile stress, 0.05% and 72 MPa, respectively (Figure 4). In comparison, FE simulation gives us 107 MPa of tensile stress after splitting. The main advantage of our approach is the lack of misfit dislocations in the Ge film, at variance with Ge epitaxy on Si (with a threading dislocations density typically around 107 cm-2, then). The presentation will focus, first, on the simulation tool and the manufacturing process used to fabricate such stressed germanium films. Then, stress calculus will be detailed. Finally, TEM imaging of cross-sections, XRD and bow measurements will help us better understand the specificities of such thin Ge films transferred on Si bulk wafers. Higurashi E. Heterogeneous integration based on low-temperature bonding for advanced optoelectronic devices. Jpn J Appl Phys. 1 avr 2018;57(4S):04FA02. King RR, Law DC, Edmondson KM, Fetzer CM, Kinsey GS, Yoon H, et al. 40% efficient metamorphic GaInP∕GaInAs∕Ge multijunction solar cells. Appl Phys Lett. 30 avr 2007;90(18):183516. Scappucci G, Kloeffel C, Zwanenburg FA, Loss D, Myronov M, Zhang JJ, et al. The germanium quantum information route. Nat Rev Mater. oct 2021;6(10):926-43. Abadie K, Fournel F, Morales C, Vignoud L, Colona JP, Widiez J. Manufacturing of Optimized Ge Substrates Using a Covalent Bonding Process. ECS Meet Abstr. 23 nov 2020;MA2020-02(22):1623. Takagi H, Kikuchi K, Maeda R, Chung TR, Suga T. Surface activated bonding of silicon wafers at room temperature. Appl Phys Lett. 15 avr 1996;68(16):2222-4. Rebhan B, Vanpaemel J, Dragoi V. 200 mm Ge Wafer Production for Oxide-Free Si-Ge Direct Wafer Bonding. ECS Trans. 8 sept 2020;98(4):87-100. Chao YL, Tong QY, Gösele UM. Thermomechanical stress in silicon on quartz wafer bonding and Smart Cut® process. MRS Proc. 2001;681:I5.10. [1] Trademark from S.O.I.T.E.C. .S.A. Figure 1

Abstract—Wafer direct bonding is now a widely spread technique in microelectronics. However in many interesting applications, wafer bonding is not adapted due to size, material or technological node differences. Die to wafer bonding could then lead to innovative devices. After explaining some specific fundamental mechanisms, III/V die to wafer bonding and copper hybrid bonding will be presented for photonic and 3D applications. Introduction SOI or backside image sensors’ fabrication in mass production, for instance, calls upon direct wafer bonding that has become a standard technology available in many industrial microelectronic factories. Direct bonding of 200 mm or 300 mm silicon wafers are nowadays well mastered. For many innovative applications, it could be interesting to introduce new materials like InP, AsGa, GaN on a silicon platform. Heterostructure bonding then needs to be developed. This could be done with wafer-to-wafer bonding. However, wafers made of these new materials usually have diameters much smaller than that of silicon wafers, especially if CMOS are required on the silicon wafers. Indeed, advanced CMOS devices are nowadays only available on 200/300 mm silicon wafers. Even if the bonding of a small wafer on a bigger one is easily feasible, the silicon surface lost will be detrimental to the cost of the device. Moreover, usually, a very small surface of the new material is needed on the silicon wafer. With a wafer-to-wafer bonding (W2W), the new material surface loss will be quite important. Die-to-wafer (D2W) bonding is thus the solution to both issues in order to put only a small amount of new material where it is needed and populate all the active area on silicon wafers. D2W is also interesting in hybrid bonding with silicon wafers. Indeed, D2W enlarges design rules to mix different technologies (material, dies size) on the same bottom wafer while enabling high density of copper interconnects.. Hybrid D2W is then foreseen as being the next step for hybrid bonding in order to widen its application field. Results Starting with the well know fundamental mechanisms of silicon dioxide bonding [1] as well as copper and hybrid surface bonding [2], D2W bonding behavior will be discussed. Some specific features indeed have to be taken into account for die bonding. For instance, all the edge effects, during and after the bonding or the annealing, have a great impact on the bonding energy as well as on the interface defectivity. Moreover, specific bonding techniques using for instance liquid water films can be used only in D2W bonding. If these specific features are under control, very innovative structures can be obtained. It is possible for instance to bond small 3mm*3mm InP dies onto 200mm silicon photonic wafers as shown in Fig.1a [3]. Moreover, hybrid bonding interfaces can also be obtained between 6mm*4mm dies and a 300mm wafer as shown in Fig.1b. Obviously, alignment in mandatory during hybrid bonding. This can be obtained thanks to a die to wafer bonder. However, innovative technologies such as capillary assisted self-assembly can also be really interesting [4 -7]. The electrical characterization of the D2W hybrid bonding connection will be also discussed, showing roughly the same good results as for W2W hybrid bonding. Acknowledgment This work was funded thanks to the French National program “Programme d’Investissement d’Avenir IRT Nanoelec” ANR-10-AIRT-05. References 1 F. Fournel, et al., ECS J. Solid State Sci. Technol. 4, P124 (2015). 2 L.D. Cioccio, et al., J. Electrochem. Soc. 158, P81 (2011). 3 B. Szelag et al., Hybrid III-V/Silicon technology for laser integration on a 200 mm fully CMOS-compatible silicon photonics platform, IEEE J. Sel. Top. Quantum Electron., In Press (2019). 4 A. Jouve, et al., ECTC (2019). 5 T. Fukushima, et al., in 2011 IEEE 61st Electron. Compon. Technol. Conf. ECTC (2011), pp. 2050–2055. 6 E. Bourjot, et al., ECTC(2021) Figure 1

The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors. The presentation will also give a synoptic view of all the key enabling process steps required to build high performance Si CMOS integrated by 3D-sequential with thermal budget preserving the integrity of active devices and interconnects and will sketch a status and prospect on current low temperature device performance.

International audience; A scalable manufacturing method is demonstrated for the transfer of crystalline AlN thin-films deposited on 200 mm Si wafer onto a flexible and stretchable polymer. The resulting AlN-On-Polymer (AOP) can be bent and stretched. This novel transfer process allows a straightforward strain-engineering method of semiconductor thin-films when transferred onto polymer. Straining controllably semiconductor thin-films may alter their properties, which may boost the performance of the corresponding devices; e.g. the piezoelectric properties of AlN are enhanced upon tensile strain. We present here the transfer process of AlN thin-films onto polymer substrates; we discuss the influence of uniaxial strain on microstructural properties of AOP after in situ Raman spectroscopy assessments and relative strain evaluations by X-ray diffractions of AlN thin-films embedded in different types of stack configurations.

Die-to-wafer direct hybrid bonding process is foreseen as a key enabler of heterogeneous 3D integration. Hybrid bonding technologies were first developed on W2W assembly reaching 3D interconnection pitch of $1\mu\mathrm{m}$ . Recently, CEA-Leti demonstrated the feasibility of DTW direct hybrid bonding at $10\mu\mathrm{m}$ with a specific die bonder (NEO HB) developed by SET Corporation. In this paper, the last improvements of DTW hybrid bonding process flow and die bonder alignment capability are presented. Main results showed an alignment capability improved to $ which enables bonding of die with $ interconnection pitch. Finally, multi-interconnection pitch bondings on a wafer were achieved with Cu pitches varying from $5\mu\mathrm{m}$ to $10\mu \mathrm{m}$ .

The study deals with the handling of thin wafers in 3D integration. It concerns the fabrication of 300 mm wafers in industrial tools. Usually, the manufacturing is based on a temporary bonding process performed at 200 °C using a thermoplastic adhesive. In that condition bonding, thinning and dismounting are satisfactory. Moreover, the adhesive flattening during bonding results in an excellent thickness uniformity of the bonded pairs, with a small total thickness variation (TTV) value suitable for 3D integration. If the temperature is 150 °C or lower, the adhesive thickness uniformity is not acceptable anymore. An innovative temporary bonding process at low temperature has thus been developed. It consists in a carrier fabrication with highly uniform adhesive thickness. The standard coated adhesive is flattened with a first reversible temporary bonding at 210 °C. After a first dismounting, this carrier is then bonded to the target device wafer with a low bonding temperature, from 110 °C to 150 °C. Due to the pre-flattening, 80 μm thick silicon films with an excellent TTV value can thus be obtained even with a low bonding temperature required by the device wafer. Moreover, after the device wafer thinning, the final dismounting can be performed without any antisticking layer.

International audience; This study reports the manufacturing of Silicon On Polymer (SOP). It describes the transfer of a 200 mm diameter silicon thin film from a silicon on insulator (SOI) substrate to a flexible polymer. The thickness of the single-crystal silicon film was less than 200 nm and the transfer was achieved by bonding the SOI wafer to a temporary silicon carrier with an adhesive polymer. Various parameters of the transfer were investigated: adherence of the stack, temperature of bonding, temporary carrier and Si film thickness. The substrate and the SOI buried oxide were removed by mechanical grinding and chemical etching. The Si thin film was held on a flexible tape and the temporary carrier was dismounted. SOPs consisting of 20 to 205 nm thin Si films on a flexible polymer (230 μm) were successfully obtained. 200 mm diameter full wafers or patterned wafers could be transferred.

Vertical p-i-n lasers integrated by wafer-bonding and regrowth on a heterogeneous InP-on-SOI wafer are presented. We demonstrate for the first time lasers based on regrown III-V active regions efficiently coupled to Si-photonic DBR cavities.

Vertical p-i-n AlGaInAs lasers obtained from a single Selective Area Growth (SAG) step on a thin InP layer bonded to silicon wafers are presented. A PL extension from 1490 nm to 1645 nm was demonstrated on InP-SOI wafer. Based on this result, a record of 155 nm wide spectral range was obtained for FP lasers on InP-SiO 2 /Si wafer.

Monolayers (MLs) of transition metal dichalcogenides (TMDs) such as WSe2 and MoSe2 can be placed by dry stamping directly on broadband dielectric resonators, which have the ability to enhance the spontaneous emission rate and brightness of solid-state emitters at room temperature. We show strongly enhanced emission and directivity modifications in room temperature photoluminescence mapping experiments. By varying TMD material (WSe2 versus MoSe2) transferred on silicon nanoresonators with various designs (planarized versus non-planarized), we experimentally separate the different physical mechanisms that govern the global light emission enhancement. For WSe2 and MoSe2 we address the effects of Mie Resonances and strain in the monolayer. For WSe2 an important additional contribution comes from out-of-plane exciton dipoles. This paves the way for more targeted designs of TMD-Si nanoresonator structures for room temperature applications., Comment: 10 pages, 5 figures

Strain engineering can be called upon to tune the band structures of semiconductors. It is widely used in different types of microelectronics devices and it is expected to enable unprecedented responses in optoelectronics [1]. In the case of single crystal Silicon (sc-Si), several approaches have been proposed, relying either on the lattice mismatch inherent to hetero-epitaxial growth (Si on relaxed SiGe) or on substrate expansion (porous Si) [2, 3]. However, these methods are limited to bi-axial strain and by the maximum strain achievable in sc-Si thin film. We recently evaluated a method enabling to transfer a 200nm thick sc-Si film on a stretchable polymer substrate. Tensile tests proved that applying an external mechanical load on the substrate injected significant amounts of strain into sc-Si [4]. This work is focused on studying different parameters to improve the maximum strain in a Silicon On Polymer (SOP) stack obtained from a 200mm Silicon On Insulator (SOI) wafer using temporary polymer bonding. The overall fabrication process is described in figure 1(a). 2 × 24mm2 rectangles are defined using photolithography in a SOI thin film. The wafer is temporary bonded to a handling silicon substrate with a 40µm thick glue layer. Then, the backside of the SOI is removed with mechanical grinding and selective chemical etching. Finally, the sc-Si thin film is transferred to a 230µm thick flexible substrate thanks to a release layer between the glue and the sc-Si layer. The substrate is cut into tensile test samples as described in figure 1(a). In a previous study we have shown that a 200nm thick sc-Si film could be uniaxialy strained up to 1.5% along the [110] direction [4]. In the present work, we quantify the impact of strain orientation, sc-Si film thickness and pattern edge roughness on maximum uniaxial strain. In order to change the sc-Si film thickness a dry etching step was used after removing the backside of the SOI ubstrate. A soft lithography mask and a standard chrome 1X lithography mask were compared for the fabrication of rectangles. To achieve even smoother pattern edges, TetraMethylAmmonium Hydroxide (TMAH) etching was also used (for 90 minutes in a 25 %wt solution at 80◦C) on a patterned SOI with a silicon oxide layer as a hard mask. Resulting samples were tested on a uniaxial tensile stage coupled to a Raman spectrometer, giving us access simultaneously to the sample macroscopic strain and the silicon local strain. Tensile test results are summarized in figure 1(b). Reducing the thickness of the sc-Si did not improve the strain limit while better edges definitions did. Indeed, using TMAH, uniaxial strains up to 3% along [100] were reached in a 200nm thick sc-Si film on a flexible polymer substrate. These results are highly encouraging for the development of films with a wide range of strain. Furthermore, this method is easily transferable to other materials such as AlN or Ge. References [1] J. Li, Z. Shan, and E. Ma, “Elastic strain engineering for unprecedented materials properties,” MRS Bulletin, vol. 39, no. 2, pp. 108–114, 2014. [2] A. Boucherif, N. P. Blanchard, P. Regreny, O. Marty, G. Guillot, G. Grenet, and V. Lysenko, “Tensile strain engineering of Si thin films using porous Si substrates,” Thin Solid Films, vol. 518, no. 9, pp. 2466–2469, 2010. [3] J. M. Hartmann, A. Abbadie, D. Rouchon, J. P. Barnes, M. Mermoux, and T. Billon, “Structural properties of tensile-strained Si layers grown on Si1-xGex virtual substrates (x = 0.2, 0.3, 0.4 and 0.5),” Thin Solid Films, vol. 516, pp. 4238–4246, 4 2008. [4] L. G. Michaud, C. Castan, M. Zussy, P. Montmeat, V. H. Mareau, L. Gonon, F. Fournel, F. Rieutord, and S. Tardif, “Elaboration and characterization of a 200 mm stretchable and flexible ultra-thin semi-conductor film,” Nanotechnology, vol. 31, p. 145302, 1 2020. Figure 1

High temperature (>1000°C) annealing is necessary to completely close a bonding interface. Using interface synchrotron high energy X-ray reflectivity, we have investigated the sealing behavior of silicon thermal oxide/ silicon thermal oxide interfaces, with different surface roughnesses. Interface X-ray reflection is able to measure accurately the width and the depth of the electron density gap across a bonding interface with a sub-nanometer accuracy, whose product is a good marker of the interface closure. The uncomplete closure of the interface is the result of a balance between attractive and repulsive force between the two bonded solids. These two forces depend on the statistics of asperity and on the mechanical behavior of individual asperity [1]. For attraction, at high temperatures, a key factor is the gain of contact surface area which reduces the surface energy due to uncontacted zones. Repulsion is due to compression of contacting asperities. At high temperature, both elastic and plastic behavior can be expected, with some yield of the asperities compressed above the elastic limit. In the elastic solid regime, we have shown that equilibrium distance of rough silicon oxide to rough siliconoxide bonding can be predicted using standard adhesive contact models such as Johnson-Kendall Roberts (JKR) or Deryagin-Müller-Toporov (DMT) with Gaussian roughness statistics[2]. The equilibrium distance is dependent and sensitive to the Fuller Tabor adhesion parameter, θ=E σ3/2 R1/2 / 2γR where E is the Young modulus, σ the mean roughness, R the radius of the asperity, while 2γ is the adhesion energy at contact points. When θ>>1 , the equilibrium distance is large and the contact area is small (unclosed interface) . When θ< In the plastic regime, both repulsive and attractive curves share the same dependence with distance so that the system is expected to be unstable, between a weakly evolving unsealed interface and a fully sealed interface when the asperity pressure stress is above the elastic limit. The kinetics of the sealing can also be modeled in this case, monitoring the interfacial gap as a function of time (Figure). It is found that the sealing characteristic time scales directly with the silicon oxide viscosity (Figure insert). This dependence can be understood using the plastic asperity contact model, assuming the fluid part flows according to the Stokes equation around asperities. References [1] Rieutord, F., L. Capello, R. Beneyton, C. Morales, A.-M. Charvet, and H. Moriceau. “Rough Surface Adhesion Mechanisms for Wafer Bonding.” In Semiconductor Wafer Bonding 9: Science, Technology, And Applications ECS Transactions, edited by H. Baumgart, S. Bengtsson, H. Moriceau, K.D. Hobart, T. Suga, and C. Colinge, 3:205–15. ECS Transactions, 2006. [2] Johnson, K. L., Contact Mechanics, Cambridge University Press (1985). Figure caption Time dependence of the interface closure for a SiO2//SiO2 bonding interface. Roughness of surfaces was 5.4Å rms as measured using AFM. The color scale gives the temperatures (1000-1200°C). Insert: dependence of the closure time with viscosity. Figure 1

To reach quantum supremacy, large scale integration of quantum bits through three dimensional (3D) architectures functional at sub-Kelvin temperatures is required. Electrical signals are transferred by 3D interconnects which need to be carefully designed in term of materials and dimensions to optimize the whole system performance. To that end, 20 μm pitch daisy chains with more than 20000 SnAg microbump-based interconnects and more than 1000 direct Cu bond ones have been fabricated with die-to-wafer processes developed on 300 mm Si wafers. Daisy chain resistances have been measured in a liquid nitrogen deware and in a He3 cryostat at the following thermal steps: 300 K, 77 K, 4 K and 400 mK, allowing to extract unitary link resistances to establish preliminary process design kits at these low temperatures. The mechanical and electrical robustness of these interconnects has been validated through the repeatability of the resistance measurements over several thermal cycles.

Current 3D integrated devices based on copper hybrid bonding are only integrating dual-damascene CMOS processes for interconnection.. In this study, we have developed a Titanium/Oxide (Ti/SiO 2 ) hybrid bonding technology suitable for 200 mm non-copper technology platforms featuring aluminum back-ends. A combination of material stack, CMP parameters and design rules enabled us to obtain defect-free bond interface across the wafer. Scanning acoustic microscopy, FIB-SEM and TEM cross-sections demonstrated a perfect SiO 2 /SiO 2 bonding as well as excellent Ti/Ti connections for Ti pads as small as 3×3 µm2. Moreover, we designed an electrical test vehicle including a Ti/SiO 2 hybrid-bonding interface, with W vias and AlCu metal interconnects. Despite the integration stack, the bonding interface remains defect-free with contact pads ranging from 10×10 µm2 down to 3×3 µm2. The 3D interconnect showed a contact resistance of 1 Ω and a parasitic capacitance of less than 2 fF. Finally, we report on the process reliability by means of thermal cycling and high-temperature storage, which confirmed the robustness of this innovative Ti/SiO 2 fine pitch interconnection.

In this work, we present the fabrication process of a $3~\mu \text{m}$ -thick AlGaInAs-based vertical p-i-n laser diode structure grown on a directly bonded InP-SiO2/Si (InPoSi) substrate. High-quality epitaxial growth on InPoSi is reported. Based on these structures, the fabrication process of Fabry-Perot broad lasers is presented. Device performance is compared to the ones obtained from the same growth run on an InP substrate as a reference. High electrical properties of the n and p contacts are demonstrated. Lasing operation in the pulse regime is shown up to 50°C. Threshold current densities as low as 0.4 kA/cm 2 at 20°C are obtained for the laser on InPoSi, comparable to the ones obtained for the reference on InP substrate.

Hybrid integration of III-V materials onto silicon by direct bonding technique is a mature and promising approaches to develop advanced photonic integrated devices into the silicon photonics platform. In this approach, the III-V material stack is grown on an InP wafer in a unique epitaxial step prior to the direct bonding process onto the silicon-on-insulator wafer. Currently, no additional epitaxial regrowth steps are implemented after bonding. This can be seen as a huge limitation as compared to the III-V on III-V wafer mature technology where multi-regrowth steps are most often implemented. In this work, we have studied the material behavior of an InP membrane on silicon (InPoSi) under epitaxial regrowth conditions by metal-organic vapor phase epitaxy (MOVPE). MOVPE requires high-temperature elevation, typically above 600 °C. We show for the first time the appearance of voids at 400 °C in an InP seed (100 nm) directly-bonded onto a thermally oxidized Si substrate despite the use of a thick SiO2 oxide (200 nm) at the bonding interface. This phenomenon is explained by a weakening of the bonding interface while high-pressurized hydrogen is present. A kinetic study of the hydrogen lateral diffusion is carried out, enabling the assessment of its lateral diffusion length. To overcome the void formation, highly efficient outgassing trenches after bonding are demonstrated. Finally, high-quality AlGaInAs-based multi-quantum well (MQW) heterostructure surrounded by two InP layers was grown by MOVPE on InPoSi template patterned with outgassing trenches. This process is not only compatible with MOVPE regrowth conditions (650 °C under PH3) but also with conventional fabrication processes used for photonic devices.

Fabry-Perot laser arrays based on vertical p-i-n laser diode structures grown on InP layer directly bonded to Si wafer is presented. Lasing emission covering the C+L bands is achieved by means of a single-epitaxy Selective Area Growth (SAG) technology.

International audience

Integrated transmitters incorporating lasers and modulators on silicon are of primary importance for all communication applications, and at the same time are the most challenging to manufacture due to the need of hybrid III-V integration. In order to introduce III-V materials in low cost silicon platform manufacturing, direct bonding approach could present a great interest due to the growth limitation of III-V hetero-epitaxial layers directly onto silicon. Furthermore, by using a 100 nm silicon dioxide layer between the silicon wave guide and the III-V active stack, direct bonding allows the optical coupling necessary to build active optical device. Nevertheless, the potential low cost model of silicon photonic is based only on the hypothesis that we are able to work on the full surface of the 200/300 mm SOI photonic wafer. III-V wafer direct bonding is not suitable to fulfill this requirement for two main reasons. First, the maximum diameter available for III-V wafers is limited to 150 mm up to now. Secondly, the III-V material is necessary only on the emitter and receiver areas which represent only a very little part of the device area. Therefore, the most part of the reported full III-V wafer is lost by the layer patterning on required areas. To overcome this limitation in term of wafer diameter and to limit the loss of a very expensive starting material we have developed at LETI a collective die direct bonding process. The idea is to bond collectively III-V chips only where there are necessary and on the full photonic SOI surface. The die size is selected to be slightly higher than the targeted area in order to be compatible with a wafer notch alignment and avoid any accurate alignment with alignment marks. The requirements for direct bonding are exactly the same than for wafer bonding, but die direct bonding is obviously more difficult due to the dicing step which generates a high level particle contamination. All the process steps have to be adapted to be compatible with die handling and the die cleaning before bonding have to be strongly optimized to remove this high particle contamination. We have then developed specific silicon die holder in order to clean the die surfaces collectively in classical microelectronics high performance cleaning tools. A test vehicle containing few hundred 3*3 mm² dice will be used to evaluate the collective die direct bonding process. Because III-V materials are not as mature as silicon, the bonding process will be firstly evaluated with silicon dies. After optimization, Indium phosphide dice will be used to validate the global process. Bonding interfaces of dice are finely characterized by Scanning Acoustic Microscopy and SAM images will be processed in order to quantify the bonding yield and the die positioning accuracy. Figure 1

Die-To-Wafer (D2W) direct hybrid bonding is foreseen as a major breakthrough for the future of 3D components; however, its industrialization rises some additional challenges compared to Wafer-To-Wafer processing. This paper presents a 300mm wafer complete solution developed at LETI to improve bonding yield of D2W hybrid bonding using copper interconnections until the assessment of the electrical performances thanks to a dedicated 300mm electrical test vehicle and robust stacking system. Stackings with +/-1.5μm accuracy and excellent bonding interface have been obtained (80% bonding yield). After stacking and annealing, the die can be thinned down to 10μm without damage. Electrical yield measured on daisy-chains with more than 20.000 connections present more than 75% yield and shown very limited drift after preliminary environmental reliability tests. All these results confirmed the high industrial potential of D2W hybrid bonding technology.

Die-to-wafer stacking is very promising for the next 3DIC generation since it offers the ability to assemble several dies with small interconnection pitches. This paper proposes an overall integration scheme D2W HB process to reinforce its robustness and its economical relevance for microelectronics industry. Firstly, a KGD strategy was developed to be compatible with hybrid bonding. A successful D2W bonding was demonstrated with tested pads. Secondly, the development of the planarization of stacked dies is presented.

International audience; The development of a silicon temporary carrier for thin wafer handling for 3D applications was investigated. Process selection and optimization ended up with a silicon carrier entirely covered with an antistick layer based on a fluorinated polymer. The carrier preparation was quite easy because only one coating was used and no sticking edge zone was needed onto the carrier. The fluorinated coating led to a very hydrophobic behavior. When bonded with a thermoplastic glue, it also exhibited very antiadhesive properties because the adherence was as low as 0.4 J/m(2) and lower than the adherence of a stack without any antiadhesive layer (above 4 J/m(2)). The carrier was nevertheless suitable for different back side processes in 300 mm grinding, chemical cleaning, chemical mechanical polishing and silicon oxide deposition. Compared with a commercial carrier, it exhibited the same level of performance for the integration. The proposed carrier was compatible with a mechanical debonding of a thinned bonded structure with a silicon device wafer of 80 pm. The carrier recycling was possible without any new preparation.

300 mm diameter thinned-down wafers are manufactured using temporary adhesive bonding. A thermoplastic adhesive and a silicon carrier are used to fabricate 100 μm thick silicon wafers. The impact of temperature on the thickness homogeneity of temporary bonded stacks is studied. From 150 °C up to 300 °C, the total thickness of the structure increases with the temperature. Moreover, its amplitude strongly increases with the thinned wafer stress and the adhesive thickness. On the contrary, it does not depend on the different interface adherence. The thinned wafer stress results in a significant peeling force which drives the deformation of the structure. This deformation is possible because of the high elasticity of the polymer at high temperature. To reduce this deformation, an alternative carrier is proposed yielding reduction of the adhesive thickness at the bonded edge only.

Epitaxial growth of high material quality $1.55\boldsymbol{\mu} \mathbf{m}$ AlGaInAs Multiquantum Wells Heterostructure on a directly-bonded InPoSi substrate has been developed for datacom applications.

The paper reviews the robustness/reliability achievements and include previously published data related to the hybrid bonding module for W2W and D2W bonding techniques.