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The increased demand for energy-efficient solutions compels system architects to explore the opportunities for minimizing area and power in the critical parts of a system. The register file is one such essential and critical component of any processor system that provides local storage for computing hardware such as arithmetic and logical unit. In this paper, we present an optimized design and implementation of a synthesizable register file that reduces the area and power consumption over an existing design. The proposed design is functionally equivalent to the existing design and uses latches in its core as main storage elements as opposed to the flip-flops; thus, reducing the area and power consumption. The proposed design has 10% less area and 23% less leakage power than the existing design when synthesized using a CMOS 45nm process libraries. Furthermore, the back-end implementation results show that the proposed design has 13% less core utilization and 2.3X less power., Part of proceedings: ISBN 978-1-6654-1992-5 QC 20220608

The way we develop software struggles to keep pace with changes in technology and business. Even with the rise of agile, people still flip-flop from one branded method to another, throwing away the good with the bad and behaving more like religious cultists than like scientists. The problem is that the professional practices that have been developed and refined over many years, and that together represent our shared industry knowledge and experience, are all too often imprisoned within proprietary method jails. The only option that development organizations and teams see themselves as having is to adopt this method or that method wholesale, and to reject all others-whereas, in fact, what is needed is for organizations and teams to be free to select the professional practices that they need, from wherever these may be defined, and use them in whatever permutations and combinations are appropriate to meet the exact set of circumstances and challenges they face. There is a simple way to break out of this cycle of unhealthy competition among methods-which are more similar than they are different-and that is to free the practices from their method prisons. Free the practices to rise and fall on their own merits. Free the practices so that teams can experiment, innovate, and plug and play with proven practices to create the way of working that they need today and to evolve seamlessly into the one they need tomorrow. This article explains why we need to break out of this repetitive dysfunctional behavior, and it introduces Essence, a new way of thinking that promises to free the practices from their method prisons and thus enable true learning organizations., QC 20220620

In this paper, we address the problem of low-overhead implementation of Feedback Shift Registers (FSRs). We present a dynamic pulse latch which is based on transistors with two different channel lengths. The channel lengths are selected to make the latch suitable for replacing flip-flops in FSRs. The presented latch is 1.92 times smaller and 3.94 times less power consuming compared to the smallest standard flip-flop in the same technology. By re-implementing FSRs of Grain-80 stream cipher with the presented latch, we achieve 32.24% reduction in area, 36.77% reduction in total power, and 10.81% increase in the maximum clock frequency compared to the original, flip-flop based version of Grain-80. If, in addition, the static time borrowing technique is applied, we achieve an additional 25.5% increase in the maximum clock frequency at the expense of 4.68% smaller gain in area and 2.67% smaller gain in total power., QC 20110314

We have developed a high-speed pipelined superconductor look-up table to generate programmable predistortion functions for direct linearization of radio frequency "RF" power amplifiers. The look-up table comprises an address decoder and a memory matrix with throughput above 10 GHz. The decoder performs code-matching of each input word and its conversion into a row address of the memory matrix. We discuss different possible implementations of the address decoder, including a preferred one for integrated circuit implementation. The memory matrix consists of RS flip-flops with nondestructive readout connected in series for slow-speed contents writing. Each row of the memory matrix contains a number, which can be read out by signal from the decoder. We present the design and the results of experimental evaluation of the look-up table and its components., Published in the Jnl. of IEEE Transactions on Applied Superconductivity v17, n2, p561-564, Jun 2007. Sponsored in part by CERDEC SBIR contracts.

A new method to obtain a high frequency clock (1 GHz) from a low frequency reference clock (10 MHz) is presented in this paper. High frequency is achieved using two level sensitive flip-flops. Variable delay lines are used to ensure that the multiplied clock is running in correct frequency. In the newly designed multiplier, the low frequency reference clock itself at every of its falling and rising edge keeps the generated high frequency clock in phase. The clock multiplication is achieved with 82ps peak-to-peak jitter when the generated clock is 1 GHz and consuming 0.822mW power from 2.5 volt power supply. The performance of the multiplication unit is tested on PSPICE using BSIM3v3 model parameters in.25μm CMOS technology., QC 20141201

This project has investigated novel circuit architectures for low-energy VLSI systems. Its primary focus has been on charge-recovering (a.k.a. adiabatic) circuits. By steering currents across devices with low voltage drops and by recycling undissipated energy, these circuits can operate more efficiently than their conventional digital counterparts. Early investigations into adiabatic circuits have yielded very complex designs that are impractical for high-speed design. This project has led to the discovery of extremely simple charge-recovering circuits that achieve very high energy efficiency at relatively high operating frequencies. The results of this research have been validated through experimental silicon prototypes. For three of the inventions that came out of this project, the University of Michigan has filed patent applications with the United States Patent and Trademark Office. In addition to charge-recovering circuits, this project also has explored tools and architectures for conventional low-energy CMOS design. The focus has been on design automation tools that can provide quick and accurate estimates of power dissipation from register-transfer level descriptions of programmable digital systems. Low-power signal processing architectures for communication applications also have been explored. A list of journal articles, conference papers, manuscripts, and inventions is included. (6 figures, 37 refs.)

Mixed signal circuits based on InP HBTs are being challenged for meeting DoD high bandwidth and dynamic range requirements by aggressively scaled SiGe bipolar technology. This paper presents the challenges that conventional mesa InP HBT technology must overcome (primarily scaling and integration complexity) to maintain its competitive advantage over the silicon alternative. Approaches to overcoming these challenges are identified., Pres. at International Conference on Indium Phosphide and Related Materials (15th) held in Santa Barbara, CA on 12-16 May 2003. See also IEEE catalog no. 03CH37413. ISBN no. 0-7803-7704-4. ISSN no. 1092-8669. This article is from ADA420200 2003 International Conference on Indium Phosphide and Related Materials

This program was based on leveraging software compiler optimization expertise to further improve upon hardware compiler optimization techniques for Field Programmable Gate Arrays (FPGAs).

This paper describes a polynomial time algorithm for min-area retiming for edge-triggered circuits to handle both setup and hold constraints. Given a circuit G and a target clock period c, our algorithm either outputs a retimed version of G satisfying setup and hold constraints or reports that such a solution is not possible, in O{absolute-value(V)(exp 3)log[absolute-value(V)]log[absolute-value(V)C]} steps, where absolute-value(V) corresponds to number of gates in the circuit and C is equal to the number of registers in the circuit. This is the first polynomial time algorithm ever reported for min-area retiming with constraints on both long and short-paths. An alternative problem formulation that takes practical issues in to consideration and lowers the problem complexity is also developed. Both the problem formulations have many parallels with the original formulation of long path only retiming by Leiserson and Saxe and all the speed improvements that have been obtained on that problem statement are also demonstrated in simulation for the approach presented here. Finally, a basis is provided for deriving efficient heuristics for addressing both long path and short-path requirements by combining the techniques of retiming and min-delay padding., Published in ACM Transactions on Design Automation of Electronic Systems, v9 n3 p273-289, July 2004.

This project addresses key component technologies for enabling the fusion of data between the transmission lines and the receivers in optical communication network systems. This year involved the optimization and testing of an integrated flip-flop device, fabrication of an integrated divide-by-8 optical clock counter/sequencer, and development of a serial to parallel converter.

The purpose of this research was to determine the expected yields and bit error rates of HTS digital circuits operated at tens of gigahertz at various temperatures. This was done by using device parameters from TRW, Conductus, and Northrup Grumman for state-of-the-art devices. The circuits studied included two rapid-single-flux-quantum (RSFQ) T flip-flop circuits. One (with 14 Josephson junctions) included estimated undesirable parasitic inductances and other was assumed free of parasitics. We also analyzed a three-stage counter made of a cascade of the T flip-flops with parasitics with 38 junctions. We conducted Monte Carlo simulations and evaluated the bit-error rates (BER) at various temperatures. Yield calculations were made for operation at a number of multi-gigahertz frequencies. For higher frequency operation, the results improved strongly with higher assumed products of critical current and normal-state resistance (lcRn). For 50 GHz operation with lcRn = 0.5 mV, we compared the yield for a T flip-flop with that of the three-stage counter (70% vs. 34%). Bit-error-rate calculations suggest that operating temperature must be <20-30 K for a BER <10^-6.

This project investigated novel design methodologies for low energy VLSI circuits and systems. It focused on energy recovering circuit architectures, a promising alternative to conventional digital CMOS circuits for low energy operation. It also explored technologies for designing low energy conventional CMOS circuits. The main contribution of our research was the discovery of TSEL, the first true single phase energy recovering circuit family. TSEL achieves very efficient operation in comparison with conventional CMOS and other energy recovering circuits. Due to its extremely simple clocking requirements. TSEL is ideal for high speed design. Moreover, TSEL gates are straightforward to cascade and are thus particularly suitable for the design of energy efficient data path components with regular structures. In the course of this project, we designed, developed, and evaluated layouts of several arithmetic units in TSEL, CMOS and several other energy recovering logic families. Our designs included 8-bit energy recovering multipliers, 8-bit carry look ahead adders, and an 8-point/4-bit Hadamard Transform module.

The majority of work today relating to quantum computing has provided results that are almost incomprehensible to even the most advanced computer architect. This paper uses the recent research results of quantum mechanical logic as building blocks to derive a computer architecture based on quantum devices that is consistent with existing system architectures. The new and admittedly exotic nature of quantum computing notwithstanding, this work presents a quantum mechanical analog of a finite state machine which may be realized from a present day architectural framework. Existing architectures are finite state sequential machines with binary data representations, asynchronous combinatorial Boolean logic and synchronous memory. Synchronous combinatorial logic with a binary data representation and implementations of D, T and JK flip-flops, which are the primary forms of synchronous memory, are presented using quantum and near quantum devices. Even the issue of reliable operation of quantum devices is addressed by suggesting that redundancy and quantum majority logic could perform single error correction at key points within the quantum system. Quantum devices can be a step in the evolution of advanced computer architectures.

The authors report an interceded oscillation in a wind- and thermally-driven ocean general circulation model (OGCM). The oscillation is tantalizing in that it occurs under a relatively strong thermal damping (26.3 W m(exp-2)K(exp-1). Examinations involving a two-dimensional OGCM, a simple thermal flip-flop model and a three-dimensional OGCM with and without the nonlinear effect of temperature in the state equation of sea water demonstrate that the oscillation is not driven by mechanisms such as the so-called convective oscillator, or the advective overshooting oscillator., Pub. in Q.J. R. /Meteorol Society, v124, p793-809, 1998.

Direct digital direction finding (DF) antennas will allow an incoming signal to be digitally encoded at the antenna with high dynamic range (14 bits approx. equal 86 dB) without the use of down conversion that is typically necessary. As a shipboard DF device, it also allows for the encoding of wide band, high power signals (e.g., +/- 43 volts) that can often appear on shipboard antennas due to the presence of in band transmitters that are located close by. This design utilizes three pulsed laser driven Mach-Zehnder optical interferometers to sample the RF signal. Each channel requires only 6 bit accuracy (64 comparators) to produce an Optimum Symmetrical Number System (OSNS) residue representation of the input signal. These residues are then sent to a locally programmed Field Programmable Gate Array (FPGA) for decoding into a 14 bit digital representation of the input RF voltage. Modern day FPGA devices are rapidly becoming the state of the art in programmable logic. The inclusion of on chip flip flops allows for a fast and efficient pipelined approach to OSNS decoding. This thesis documents the first 14 bit digital antenna which utilizes an FPGA algorithm as a method of OSNS decoding. This design uses FPGA processors for both OSNS decoding and Parity processing.

A signal converter for converting a bi-phase level data stream to non-return to zero level data. The hi-phase level data stream is input to a detector circuit. When the detector circuit detects a high level for more than half of a bit period the detector circuit provides a logic zero pulse at a state s7. If the high level is not at the logic one state for a sufficient time period the detector circuit will not reach state s7. If the time period is to short than the detector circuit is reset to state s0. This high level pulse occurs whenever the second half of a bit period is high followed by a high in the first half of the following bit period. A sample is taken on the first half of every bit period. A low at the detector circuit keeps the detector circuit at state s0. A clock signal generating circuit receives the logic zero pulse and then proceeds through its states s0-s10. When state S1 is reached a clock pulse is provided by the clock signal generating circuit. This clock pulse is supplied to a Flip Flop which also receives the bi-phase level data stream. The clock pulse then clocks the logic level of the bi-phase level data stream through the Flip Flop to its output thereby providing a non-return to zero level coded waveform or data stream., Supersedes PAT-APPL-591 179-95.

A digital conversion circuit for receiving a Non-Return to Zero Level Data stream and then converting the Non-Return to Zero Level Data stream to a Bi-Phase Data stream. Combinational logic including an EXCLUSIVE-NOR circuit, three D-type Flip-Flops, AND gates, a NAND gate and inverters are utilized to convert the Incoming Non-Return to Zero Level Data stream to the Bi-Phase Data stream while eliminating from the Bi-Phase Data stream any undesirable spikes or noise., Supersedes PAT-APPL-528 623-95.

The purpose of this program was to demonstrate the capabilities of NDR device for the design and fabrication of high-functionality for the design and fabrication of high-functionality digital circuits. Several basic circuit functions have been demonstrated using RTD-HBT devices and extensive software for CAD of various types of circuits including adders a correlators and multivalued logic circuits was developed and employed to estimate power/speed tradeoffs in various logic circuits. Several Resonant Tunneling devices were fabricated including RTD's, RHET's, Esaki diodes and others. These diodes were then employed to demonstrate various logic functions such as AND, XNOR, Flip Flops and others. A Monolithic RTBT circuit to demonstrate a minority gate was also fabricated and demonstrated.

A digital circuit comprising a pair of D Flip-Flops which synchronize an incoming NRZ L serial data stream to an external ten megahertz clock signal. The combination of a third D Flip-Flop and an EXCLUSIVE-NOR gate generates a clear pulse whenever a change of state occurs within the synchronized serial data stream. This clear pulse is supplied to a ten state machine resetting the state machine to state SO. When the state machine transition to state 54 the state machine generates an enable signal which is supplied to a toggle Flip-Flop enabling the Flip-Flop allowing the Flip-Flop to change state. The ten megahertz clock signal then clocks the toggle Flip-Flop causing the Flip-Flop to change state. At state S9 the state machine again provides an enable signal to the toggle Flip-Flop enabling the toggle Flip-Flop which allows the ten megahertz clock signal to change the state of the output of the toggle Flip-Flop. This results in one megahertz clock signal at the output of the toggle Flip-Flop which is synchronized to the incoming serial data stream., Supersedes PAT-APPL-521 385-95.

The goal of this program was to develop ultra-fast superconducting digital technology based on HTS Josephson junctions on silicon substrates. Working Josephson junctions and SQUID's were successfully fabricated on silicon, and an Yttrium-Barium-Copper-Oxide RSFQ rs flip-flop with 14 junctions and I/O test structures was successfully designed, fabricated, and tested. The kinetic inductance and London penetration depth of the films on silicon were determined from measurements of SQUIDs on silicon. Minimizing kinetic inductance through the use of thicker films will be required in future devices. An approach to alleviating film stress in these thicker films due to thermal expansion coefficient mismatch is outlined. This proposed solution involves fabricating a functionally graded buffer layer that can flow plastically to relieve stress while at the same time, allows nucleation and growth of heteroepitaxial films. A wafer bonding facility was constructed and utilized to demonstrate the successful bonding of silicon and BPSG coated wafers, a key step in the compliant substrate fabrication procedure., Original contains color plates: All DTIC/NTIS reproductions will be in black and white.

We have successfully fabricated and tested the first All-High-Tc circuit of the Rapid Single Flux Quantum (RSFQ) logic family using a single-layer YBa2Cu3O(7-x) thin-film structure with 14 in-plane Josephson junctions formed by direct electron beam writing. The circuit includes two DC/SFQ converters, two Josephson transmission lines, a complete RS SFQ flip-flop, and an SFQ/DC converter (readout SQUID). Low-frequency testing has shown that the dc-current biased circuit operates correctly and reliably at T-30 K, a few degrees below the effective critical temperature of the junctions. We have also made and studied the first SQUIDs on silicon substrates using the same method to demonstrate the feasibility of integrating HTS with silicon based technology.

A digital audio signal processing circuit eliminates the amplitude and phase components of logic induced modulation from a left right clock signal, a bit clock signal and digital data bits generated by a digital signal processor within a compact disk player. The digital audio signal processing circuit includes a trio of optical couplers for removing the amplitude component of logic induced modulation from the left right clock signal, the bit clock signal and the digital data bits; a clock circuit for generating a system clock signal and a trio of D Flip Flops for removing the phase component of logic induced modulation from the left right clock signal, the bit clock signal and the digital data bits and a digital to analog converter for separating the data bits into left channel data bits and right channel data bits and for converting the left channel data bits into a first analog signal and the right channel data bits into a second analog signal for use by speakers or the like to provide stereo sound. An isolated power supply provides both analog and digital voltages to the electronic elements of digital audio signal processing circuit., Supersedes PAT-APPL-897 647-92.

Summary of Progress . Task 2-RSFQ Modeling and design - We have identified parasitic inductance as a critical parameter governing the margins and performance of HTS RSFQ devices. Thermal expansion mismatch induced stress limits the overall thickness of HTS films on silicon substrates to under 70 nm. Because this thickness is less than the london penetration depth, typically 150 nm - 400 nm, we expect a substantial kinetic inductance to be associated with wiring and transmission lines. The kinetic inductance associated with the Josephson junctions themselves is still poorly understood. Because of the importance of inductance to overall circuit performance, we have fabricated and measured (Task 3) some dc SQUIDs and RSFQ flip flops incorporating SQUIDs. The estimated sheet parasitic kinetic inductance is given by the formula L sub sq =lambda sub L(2)/d, where lambda sub L is the London penetration depth, d is the film thickness (d much less than lambda sub L) and the current distribution is assumed to be uniform. The total loop inductance in a dc squid can be extracted from the magnitude of the magnetic field induced critical current modulation. We have performed measurements on a SQUID fabricated from a 25 nm thick film grown on an LaAlO3 substrate by the barium fluoride process. The inductance calculated over a wide temperature range are plotted in Figure 1. Similar results for a much smaller SQUID imbedded in an RSFQ flip flop are also shown in the figure. The temperature dependence to the sheet inductance is a signature of substantial kinetic inductance. Since kinetic inductance negatively impacts circuit performance, it is essential that careful quantitative account of all sources of inductance be included in circuit design efforts.

Three optical switching elements have been designed, fabricated and tested for use in an integrated, optical signal processor. The first, an optical NOR logic gate uses gain quenching as a means of allowing one (or more) light beam(s) to control the output light. This technique, along with the use of a two pad bistable output laser, is used in demonstrating the feasibility of the second device, an all optical RS flip flop. The third device consists of a broad area orthogonal model switching laser, whose corollary outputs correspond to the sign of the voltage difference between its two high impedance electrical inputs. This device also has possible memory applications if bistable mode switching within the broad area laser can be achieved.

A digital counting circuit, including a binary counter supplying output signals to an adjacent code encoder that processes the received signals and transmits its output to a binary decoder. The encoder has a plurality of D-type flip-flop devices to which selected outputs of the binary counter are connected. The circuit operates so that only one input change to the binary decoder is permitted for each change of count from the binary counter. This prevents any erroneous counts from momentarily appearing on the output lines of the binary decoder.

This research effort pursued the design, fabrication, and test of a robotic tactile sensor. The VLSI integrated circuit (IC) portion of the sensor included a 7 x 7 array of metal electrodes which were individually connected to identical MOSFET amplifiers. A 25 micrometers thick patch (6 mm x 6 mm) of piezoelectric polyvinylidene fluoride (PVDF) film was attached to the array with a non-conductive adhesive, thereby creating an array of taxels. Charge, generated by the PVDF film, was detected by the amplifiers. The outputs of these amplifiers were connected to onchip signal circuitry designed to produce a single stream of serial data. A problem with the signal processing circuit circumvented the proper operation of the entire IC. Therefore, an external multiplexer was used to analyze the performance of a 3 x 3 array of taxels located in the center of the 7 x 7 array. The key factor affecting the performance of the sensor was establishing a uniform initial charge state condition across the 3 x 3 array. Schemes for manifesting this condition were examined as well as characterization of taxel load response. A fundamental image recognition process successfully recognized an applied shape by comparing the pre-load, load, and post-load multiplexed output of the array.

Development of a hybrid simulation for the Stinger POST Missile System was completed during this task. A comprehensive users' manual is presented through this report. Descriptions of the analog models, electronics breadboard assembly, control logic, digital program, interfaces, diagnostic capabilities, and operation sequences are provided., SBI-ADE950403.

The technical contributions were as follows: (1) Optical parallel 2-D neighborhood processor and optical processor assessment technique; (2) High accuracy with moderately accurate components and optical fredkin gate architectures; (3) Integrated optical threshold computing, pipelined polynomial processor, and all otpical analog/digital converter; (4) Adaptive optical associative memory model with attention; (5) Effectiveness of parallelism and connectivity in optical computers; (6) Optical systolic array processing using an integrated acoustooptic module; (7) Optical threshold elements and networks, holographic threshold processors, adaptive matched spatial filtering, and coherence theory in optical computing; (8) Time-varying optical processing for sub-pixel targets, optical Kalman filtering, and adaptive matched filtering; (9) Optical degrees of freedom, ultra short optical pulses, number representations, content-addressable-memory processors, and integrated optical Givens rotation devices; (10) Optical J-K flip flop analysis and interfacing for optical computers; (11) Matrix multiplication algorithms and limits of incoherent optical computers; (12) Architecture for machine vision with sensor fusion, pattern recognition functions, and neural net implementations; (13) Optical computing algorithms, architectures, and components; and (14) Dynamic Optical interconnections, advantages and architectures.

A means for synthesizing echoes using a combination of analog and digital techniques for target classification training of shipboard ASW men was needed. A study indicated that the echoes could be generated by using the latest state-of-the-art methods and components. A system incorporating solid state components was designed and implemented to produce a synthetic sonar echo. The finalized research tool was then evaluated at the Key West Fleet Sonar Training School and at the Naval Training Equipment Center, Orlando. Installation of a prototype trainer in a Navy Sonar Training School is recommended. Training effectiveness studies should be conducted in order to determine the full extent of training transfer from the simulator to the real world situation. It is further recommended that this study be continued to include the effects on the echo signal due to multipath propagation and reverberation. Methods should be investigated to feed the echo signal to the sonar set receiver processor input on a non-programmed basis. This would include additional electronics or a mini-computer to solve target motion and position relative to own ship.

Active laser gyroscopes suffer from a lock-in phenomenon, a result of backscatter from the cavity optical elements, which limit their performance in the regime of near-zero rotation. The flip-flop gyro proposed and initially investigated under this effort shows potential for minimizing or avoiding this lock-in effect. The need for a high accuracy, inexpensive and reliable clock, suitable for avionics applications was the motivation for the laser clock proposed and studied during the course of this effort. Both devices require and deserve further investigation to properly demonstrate their utility. Keywords include: Laser gyroscoppe, Lock-in, Frequency stabilization, Laser clock, and Injection locking.

The invention pertains to the area of computer technology. Single-crystal registers with error detection are known. However, in them the error detection block is suitable only for the class of single-cycle registers. Also known are two-cycle shift registers in which the emergence of undetected errors is possible. In the proposed two-cycle register, to increase the reliability of error detection the first outputs of the primary and auxiliary flip-flop of each digit are connected with the inputs of one element, EXCLUSIVE-OR, the output of which is connected with input of the first element OR, the second outputs of the main flip-flop of each digit and the auxiliary flip-flop of the following digit are connected with the inputs of each element EXCLUSIVE-OR, the output of which is connected with the input of the second element OR, the outputs of elements OR, are connected with the input of the element AND which corresponds to it, the other input of which is connected with output of the additional flip-flop, the inputs of which are connected with the main and auxiliary clock bus, and the outputs of element AND are connected to the inputs of the third element OR. Additional keywords: Translations, USSR, Foreign technology., Edited trans. of Patent (USSR) 383 048 p1-4, 23 May 73, by Bernard L.Tauber.

Experimental radar measurements were taken on a target aircraft flying low over a smooth reflecting sea for the purpose of testing the three subaperture method, which is a non-linear technique for estimating the elevation angle of a a target in the presence of multipath. The experimental array employed three vertically mounted dishes and three receivers, and the system stability proved to be more than adequate to permit interchannel gain and phase calibrations to be made by an appropriate numerical processing of the data. The standard deviations of the angle estimates were found to conform to theoretical expectations, but the biases were often large and exhibited a certain peculiar degeneracy in the vicinity of multipath nulls; viz, a sharp and rapid increase as the target approached a null followed by an abrupt change in sign as the target emerged from the null. Computer simulations were used to determine whether this peculiar angle flip-flop phenomenon could have been caused by (1) refractive ray bending, (2) uncompensated array tilt, (3) diffuse scattering from the sea surface, or by (4) diffraction of the echo signal round obstacles located in the near vicinity of the radar. It was found that although the first two mechanisms can produce large biases, such biases are symmetric about the multipath nulls, whereas the latter two mechanisms can produce biases which are both large and skew-symmetric about the nulls. It is therefore concluded that one of the latter two mechanisms was responsible for for the observed large biases.

State-of-the-art bipolar logic technology has advanced with the recent introduction of 'Super Schottky' and 'Low Power Super Schottky' product lines by two semiconductor manufacturers. Texas Instruments (T.I.) and Fairchild Semiconductor have utilized advances in processing techniques such as oxide isolation and refinements in the resolution of photolithographic equipment to enhance the speed and reduce the power of present day Schottky (S) and Low Power Schottky (LS) technologies. This report provides results obtained from the electrical characterization over the military temperature range (-55 CTj to + 125 CTj) of gate and flip-flop samples of three new transistor Transistor Logic (TTL) technologies; Advanced Schottky (AS), Advanced Low Power Schottky (ALS), and Fairchild Advanced Schottky (TTL) (FAST). This report shows that each technology offers the system designer unique advantages in terms of improved performance, power reductions, and space savings derived from functional design complexity. The performance improvements obtained by these new logic technologies, however, present implicit new application and testing considerations that could previously be ignored by the military system designer.

A design and analysis study of potential high-speed GaAs-MESFET memory circuits was performed. The results show that a 1-kbit static RAM having a 1-nsec access time is feasible. The design of the flip-flop memory cell uses low-power enhancement-mode MESFETs; power dissipation would be 5 microwatts per cell. To achieve maximum memory speed, the peripheral control and drive circuitry uses depletion-mode devices; total power dissipation would be about 1 W. Experimental testing and characterization of the memory circuit designs will be performed during the second phase of the program. (Author)

The goal of this report is to develop test generation procedures for testing microprocessors in a user environment. Classical fault detection methods based on the gate and flip-flop level or on the state diagram level description of microprocessors are not suitable for test generation. The problem is further compounded by availability of a large variety of microprocessors. They differ widely in their organization, instruction repertoire, addressing modes, data storage and manipulation facilities, etc. In this report, a general graph-theoretic model for microprocessors is developed at the register transfer level. Any microprocessor can be easily modeled using information only about the instruction set and the functions performed by it. This information is easily available in the user's manual. A fault model is developed on a functional level quite independent of the implementation details. The effects of faults in the fault model are investigated at the level of the graph-theoretic model. Test generation procedures are proposed which take the microprocessor organization and the instruction set as parameters and generate tests to detect all the faults in the fault model. The complexity of the test sequences measured in terms of the number of instructions is given. Our effort in generating tests for a real microprocessor and evaluating their fault coverage is described. (Author), Sponsored in part by Contract DAAG29-78-C-0016.

The ion microprobe mass analyzer was used for a general chemical characterization of actual integrated circuits. The analysis technique was designed to determine impurities at the surface, in the deposited oxide, in the thermal oxide, in the metallization, and at the various interfaces between these layers. The identification of the intentional dopants in the silicon was performed where concentrations were above the detection limit. In-depth concentration profiles of intentional dopants such as phosphorus were obtained by monitoring the dopant ion signal as a function of sputter time. A quantitative estimate of some of the common dopants and/or impurities was accomplished using an emperical calibration. Depths were determined by emperically calibrating the sputter rates as a function of area, total primary ion current, and primary ion species. Interface regions were identified by sputter time analysis of layers where successive layers have an elemental matrix change. The interfaces between layers of similar matrix elements, such as deposited oxide - thermal oxide were assumed to have the same sputter time as dissimilar matrices, i.e., deposited oxide over metal has the same thickness and sputter characteristics as over thermal oxide. Negative or positive oxygen was used as the primary sputtering ion for data collection. Positive argon was used as the primary sputtering ion for data collection. Positive argon was used to rapidly sputter through layers for interfacial analysis.

A family of Processors has been developed to perform arithmetic on data in the Burst Format. The common building block of these circuits is a simple finite state machine called the Perverted Adder (PA) which performs BURST addition. The interconnection of PAs in a tree formation with some additional circuitry produces a Burst multiplier or divider. A PA CPU has been constructed to demonstrate these PA designs. (Author)

This thesis presents analysis of the application of alternating logic to the design of self-checking systems. In particular, results are presented in the areas of combinational logic, sequential logic, self-checking alternating logic modules, self-checking alternating logic checker design, and self-checking alternating logic system design. The necessary and sufficient conditions for a self-dual combinational network to be self-checking are developed. An analytic technique for evaluating if any self-dual network is self-checking is given. A memory efficient approach for the design of self-checking alternating logic sequential machines is presented. Various techniques of checker design for self-checking alternating logic are discussed. The requirements of the hardcore portion of general self-checking systems is given. Minority modules are shown to be sufficient to convert any NAND or NOR network to a self-checking alternating logic network.

Circuitry has been developed to permit a Computek GT-50 Graphic Tablet to be easily hooked up to any digital computer having an analog-to-digital converter. The Computek Tablet indicates the successive locations of a special pen traveling across the tablet surface as a series of digital coordinates. The circuity described represents each new set of digital coordinates. The circuitry described represents each new set of digital coordinates as a deviation from the previous set. Each deviation is represented as an analog voltage. The resulting analog signal is subsequently converted by an analog-to-digital converter into the binary representation required for use with a digital computer. This method of working with only the deviations of the successive pen positions allows the bandwidth needed to describe the movement of the pen across the table to be reduced. The accuracy of the signal describing the pen movement is assured by maintaining a large analog output signal-to-noise ratio. (Author)

This report describes the radiation test response of the five transistor-transistor-logic (TTL) technologies and the emitter-coupled-logic (ECL) technology. The five TTL technologies evaluated were Standard, High Speed, Low Power, Low Power Schottky, and Schottky. Quad dual input NAND (TTL) or NOR (ECL) gates and dual D flip-flops from each technology were tested. The devices were characterized for gamma dose-rate logic upset, total gamma dose survivability, and neutron fluence survivability. The data has been analyzed to provide a comparison of each logic technology's radiation response. (Author)