HTS Josephson Technology on Silicon with Application to High Speed Digital Microelectronics. Phase 1.

The goal of this program was to develop ultra-fast superconducting digital technology based on HTS Josephson junctions on silicon substrates. Working Josephson junctions and SQUID's were successfully fabricated on silicon, and an Yttrium-Barium-Copper-Oxide RSFQ rs flip-flop with 14 junctions and I/O test structures was successfully designed, fabricated, and tested. The kinetic inductance and London penetration depth of the films on silicon were determined from measurements of SQUIDs on silicon. Minimizing kinetic inductance through the use of thicker films will be required in future devices. An approach to alleviating film stress in these thicker films due to thermal expansion coefficient mismatch is outlined. This proposed solution involves fabricating a functionally graded buffer layer that can flow plastically to relieve stress while at the same time, allows nucleation and growth of heteroepitaxial films. A wafer bonding facility was constructed and utilized to demonstrate the successful bonding of silicon and BPSG coated wafers, a key step in the compliant substrate fabrication procedure.
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