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The effect of gate-tunneling leakage in the MOS capacitor on the circuit performance of the phase-locked loop (PLL) in the nanoscale CMOS technology is examined. The MOS capacitors with different oxide thicknesses are used for examining their affect on the PLL performance and the locked time, static phase error and jitter of the second-order PLL are degraded by the gate-tunneling of the MOS capacitor used in the loop filter.

Both LDNMOS and certain types of SCRLDMOS (SCRs embedded in LDNMOS) high-voltage clamps are examined for safe-operating-area collapse due to trigger voltage walk-in after transmission-line pulsing (TLP) corresponding to leakage-current increase below [I.sub.t2]. The physical mechanism for the leakage enhancement and trigger-voltage walk-in is ascertained through failure analysis that is consistent with melt filament growth perhaps helped by metal migration and the ESD-safe operating area (SOA) interaction is emphasized.

Millisecond Flash anneal (MFLA) is demonstrated on a matured DRAM product for gate-induced drain leakage (GIDL) improvement, while examining the device impact and junction defects. Bright field and weak-beam dark-field TEM images has showed perfect dislocation loops and fault dislocation loops staying in the {113} plane and these defects might be the one of the leakage sources for a defect-assisted trap charge, leading to trap-assisted tunneling.

The development of a new method for the analysis of dynamic random-access memory (DRAM) data-retention characteristics is reported. The method that is applicable to DRAM of any generation could be used as a powerful tool in the design of DRAM cells with adequate retention times.

The quantitative analysis of the variability of encroached growth (VEG) of nickel silicide is used to study the association between the nickel silicide encroachment and the gate-edge leakage current. The [Si.sup.+] ion-implantation (Si-I.I.) technique can be applied to achieve low leakage current n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) without any disturbance of the transistor performance.

This paper considers both flux and rotor position estimations for sensorless control of delta-connected cage induction machines (IMs) at low and zero frequency operation. The variation of leakage inductance due to either saturation or rotor slotting is tracked by measuring the derivative of the zero sequence current in response to the application of appropriate voltage test vectors. The method requires only a single extra sensor. It requires access to machine phase windings and is appropriate for integrated-type induction motor drives. Both a closed-slot and an open-slot machine is used to demonstrate rotor flux and rotor position tracking, respectively. Experimental results are presented showing sensorless torque control and sensorless speed and position control at low and zero frequencies. Index Terms--Induction machine, position estimation, rotor slotting saliency, saturation saliency, sensorless control, zero sequence current.