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We have developed a set of methodologies for thermal aware circuit-level reliability analysis with either Al or Cu metallization in a circuit layout and implemented it in a public domain reliability CAD tool, SysRel. SysRel utilizes a hierarchical reliability analysis flow, with interconnect trees treated as the fundamental reliability unit, that sufficiently captures the differences in electromigration failure between Al and Cu metallizations. Under similar test conditions, the electromigration reliability of Al and Cu interconnect trees demonstrates significant differences because of the differences in interconnect architectural schemes. Using the best estimates of material parameters and an analytical model, we present a detail comparison of electromigration reliability of a sample test-structure as well as of actual circuit layouts with Al and Cu dual-damascene interconnect systems. We also demonstrate fast thermal-analysis in SysRel for circuit performance driven chip-level reliability assessment.

Under similar test conditions, the electromigration reliability of Al and Cu interconnect trees demonstrate significant differences because of differences in interconnect architectural schemes. The low critical stress for void nucleation at the Cu and interlevel diffusion-barrier interface leads to varying failure characteristics depending on the via position and configuration in a line. Unlike Al technology, a (jL) product-filtering algorithm with a classification of separate via-above and via-below treatments is required for Cu interconnect trees. A methodology and tool for circuit-level interconnect-reliability analyses has been developed. Using data from the literature, the layout-specific circuit-level reliability for Al and dual-damascene Cu metallizations have been compared for various circuits and circuit elements. Significantly improved test-level reliability in Cu is required to achieve equivalent circuit-level reliability. Moreover, the required improvement will increase as low-k/low-modulus dielectrics are introduced, and as liner thicknesses are reduced.

A dithering algorithm is presented for application to local composition control (LCC) with three-dimensional printing (3D printing) to convert continuous-tone representation of objects with LCC into discrete (pointwise) version of machine instructions. The algorithm presented effectively reduces undesirable low frequency textures of composition for individual 3D layers and also for 3D volumes. Peculiarities of the 3D printing machine, including anisotropic geometry of its picture elements (PELs) and uncertainties in droplet placement, are addressed by adapting a standard digital halftoning algorithm. Without loss of generality, our algorithm also accounts for technical limitations in the printing device, only generating lattices that can be represented within the finite memory limits of the hardware.

In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit are fabricated on different wafers, and then, the wafers are bonded with a glue layer of Cu or polymer based adhesive. Using our layout methodology, designers can layout such 3D circuits with necessary information on inter-wafer via/contact and orientation of each wafer embedded in the layout. We have implemented the layout methodology in 3DMagic. Availability of 3DMagic has led to interesting research with a wide range of layout-specific circuit evaluation, from performance comparison of 2D and 3D circuits to layout-specific reliability analyses in 3D circuits. Using 3DMagic, researchers have designed and simulated an 8-bit encryption processor mapped into 2D and 3D FPGA layouts. Moreover, the layout methodology is an essential element of our ongoing research for the framework of a novel Reliability Computer Aided Design tool, ERNI-3D.

The computer-aided fabrication environment (CAFE) is a software system being developed at the Massachusetts Institute of Technology (MIT) for use in the manufacture of integrated circuits (ICs). CAFE is intended to be used in all phases of process design, development, planning, and manufacturing of IC wafers. While still under active development, CAFE presently provides day-to-day support to research and production facilities at MIT with both standard and flexible product lines. CAFE provides a platform for work in several active research areas at MIT, including technology (process and device) computer-aided design (TCAD), process modeling, manufacturing quality control, and TCAD tool integration. The overall architecture and characteristics of the CAFE system are described. The significant problems solved and the design decisions made are identified, and some of the most important components of the CAFE system as it currently exists are discussed. The CAFE architectural framework supports a wide variety of software modules, including both development tools and on-line applications. The key components of the CAFE architecture are the data model and data base schema, the process flow and wafer representations, the user interface, and the application programming and database interfaces. >

The interconnection architecture of FPGAs such as switches dominates performance of FPGAs. Three-dimensional integration of FPGAs overcomes interconnect limitations by allowing instances to be located and signals to be routed in 3-D space. Wire resource prediction is important for fast and accurate interconnection planning in 3-D FPGA. In this paper, we extend the existing analytic model shown in [13] with a new parameter for our 3-D FPGA which has cluster-based logic blocks. The proposed wire resource prediction model is applied to our 3-D FPGA using a Xilinx Virtex2 slice [18] and our 3-D routing architecture. We validate the effectiveness of the extended model by comparing the required number of channel wires predicted by the extended analytic equation with that of the placed and routed results using 3-D placement and routing algorithm designed for our 3-D FPGA for a number of benchmark circuits. The extended 3-D wire resource prediction model predicts the required channel capacity with an average of 11.1% error for 17 large circuits from LGSynth93 and ISPD2001 Verilog benchmarks.

Under similar test conditions, the electromigration reliability of Al and Cu metallization interconnect trees demonstrates significant differences because of the differences in interconnect architectural schemes. In Cu technology, the low critical stress for void nucleation at the interface of the Cu and the inter-level diffusion barrier, such as Si/sub 3/N/sub 4/, leads to asymmetric failure characteristics based on via position in a line. Unlike Al technology, a (jL) product filtering algorithm with a classification of separate via-above and via-below treatments is required for Cu interconnect trees. Using the best estimates of material parameters and an analytical model, we have compared electromigration lifetimes of Al and Cu dual-damascene interconnect lines. A reliability CAD tool, SysRel, has been used to simulate full-chip reliability of the same circuit layout with different interconnect technologies. In typical circuit operating conditions, Al bamboo lines have the best lifetime followed by Cu via-below, Cu via-above, and Al polygranular type lines.

Accurate circuit-level reliability analyses can be based in experimental results for simple interconnect segments if interconnect trees, linked interconnect segments within one level of metallization, are used as fundamental reliability units. The reliability behaviour of both segments and trees is different for Al and Cu. A revised method is proposed for tree-based circuit-level reliability analyses for Cu. The types of additional experimental data that would allow assessments with improves accuracy are outlined.

Copper (Cu) based interconnect technology is expected to meet some of the challenges of technology scaling in the pursuit of higher performance. However, Cu interconnects are still susceptible to electromigration-induced failure over time. We describe a new hierarchical approach for predicting the reliability of Cu-based interconnects in circuit layouts, and present an RCAD tool, SysRel, for such an analysis. We propose a (jL) product filtering algorithm with a classification of separate via-above and via-below treatments in Cu interconnect trees. After the filtering of immortal trees, a default model is applied to the remaining trees to compute reliability figures for individual units. SysRel utilizes joint stochastic reliability metrics based on the desired lifetime of a chip and combines reliability figures from individual fundamental reliability units. Simulation results with a 32-bit comparator circuit layout demonstrate the significance of our methodology in selectively identifying critical nets and their impacts on overall reliability.

In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit are fabricated on different wafers, and then, the wafers are bonded with a glue layer of Cu or polymer based adhesive. Using our layout methodology, designers can layout such 3D circuits with necessary information on inter-wafer via/contact and orientation of each wafer embedded in the layout. We have implemented the layout methodology in 3DMagic. Availability of 3DMagic has led to interesting research with a wide range of layout-specific circuit analyses, from performance comparison of 2D and 3D circuits to layout-specific reliability analyses in 3D circuits. Using 3DMagic, researchers have designed and simulated an 8-bit encryption processor mapped into 2D and 3D FPGA layouts. Moreover, the layout methodology is an essential element of our ongoing research for the framework of a novel reliability computer aided design tool, ERNI-3D.

The sections in this article are 1 Information Model 2 User and Program Interfaces 3 Process Libraries 4 Application Programs 5 Application: Factory Design 6 Application: Computer Integrated Manufacturing 7 Application: Simulation 8 Standardization

We describe a flexible, distributed system architecture capable of supporting collaborative design and fabrication of semi-conductor devices and integrated circuits. Such capabilities are of particular importance in the development of new technologies, where both equipment and expertise are limited. Distributed fabrication enables direct, remote, physical experimentation in the development of leading edge technology, where the necessary manufacturing resources are new, expensive, and scarce. Computational resources, software, processing equipment, and people may all be widely distributed; their effective integration is essential in order to achieve the realization of new technologies for specific product requirements. Our architecture leverages is essential in order to achieve the realization of new technologies for specific product requirements. Our architecture leverages current vendor and consortia developments to define software interfaces and infrastructure based on existing and merging networking, CIM, and CAD standards. Process engineers and product designers access processing and simulation results through a common interface and collaborate across the distributed manufacturing environment.© (1997) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

The MIT remote microscope is a telemicroscopy system that allows users to remotely control and view a microscope over the internet with a graphical interface that runs on an ordinary workstation computer. The microscope server consists of an automated Zeiss microscope that is controlled by a personal computer, while the client interface is implemented with custom software developed at MIT. The system was designed primarily to provide remote inspection capabilities for semiconductor researchers during the remote fabrication of integrated circuits, but can also be used as a general purpose instrument for remote inspections. The remote microscope also allows any number of clients to simultaneously view the microscope in a conference inspection mode, enabling collaboration opportunities among distant viewers. Because clients require no special hardware, the internet remote microscope is extremely accessible and easy to use, yet provides powerful remote inspection capabilities, collaboration opportunities, and easy access to hard to reach locations such as clean room environments for semiconductor processing.© (1996) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

The importance of enlarging and reducing two-level images such as graphical and documentary matter by digital means continues to grow as more such images are digitally represented. A nonlinear scaling scheme is devised which exploits the simplicity of this binary nature, treating images logically instead of arithmetically; a convolution-like effect is achieved without a single addition or multiplication! This method yields high-fidelity digital scaling and meets the objectives of being fast, conducive to hardware realization, and void of special pre-encoding requirements.

A system has been developed which represents an effective unified framework for interactive layout and page generation of pictures and linework for applications in the graphic arts. The functional structure and logical organization of this system are based upon the segment display processor (SDP) architecture which offers a generalized approach to the manipulation of multisegment multiformat data. Interactive layout is accomplished with the aid of a graphics digitizing tablet and proof TV display. Subsequent input scanning, sizing, enhancement, and merge operations are fully automatic. The system handles arbitrary shaped regions, type-on-tone, and optimally codes areas of continuous tone and line art copy individually. The PAGES system described in this paper is centered around a software emulation of the SDP supporting continuous tone imagery and scanned type. Most of the effort devoted to this development will be directly applicable to an SDP-based system implemented with the aid of special purpose high-speed hardware in the future.

A computer-based system for automated engraving of gravure cylinders has been developed and is now used in a normal production environment. Either fully composed pages or individual page components are scanned and stored on a large disk. In the case of fully composed pages, an operator uses a TV display to segment the page image into line and tone areas. The image is then coded by a software process and is ready for subsequent engraving. Prior to the scanning of page components, the operator uses a tablet in order to demark both cropping locations and to specify the location of the components on the final page image. The scanned components are then assembled and coded by a single software process. The encoding process reduces the data storage requirement by a factor of two without any apparent loss of quality. Data are retrieved from disk storage, buffered, decoded, transmitted to a special formatter, and used to drive a Helio Klischograph,® which engraves the cylinder in approximately one hour. Completely arbitrary imposition (the arrangement of pages on the gravure cylinder) is accomplished at the time of engraving. Provision is made for the arbitrary intermixture of computer-processed pages and conventional engraving by means of Cronapaquesgi mounted on the companion scanning machine. The motivation for this development was to reduce the cost and time required for the production of gravure cylinders.

A multiuser multiprocessing image processing system has been developed. It is an interactive picture manipulation and enhancement facility which is capable of executing a variety of image processing operations while simultaneously controlling real-time input and output of pictures. It was designed to provide a reliable picture processing system which would be cost-effective in the commercial production environment. Additional goals met by the system include flexibility and ease of operation and modification.

The transformation of image signals between the continuous domain of the real world and the discrete domain of modern data processing can have a significant effect on quality and efficiency. Analysis based on perceptual rather than mathematical considerations has been carried out. A series of experiments based on the analysis has shown that substantial improvement over usual techniques can be achieved by the use of a cascade of a presharpening filter combined with Gaussian presampling and interpolation filters. The resulting ``sharpened Gaussian'' filter, although not exactly circularly symmetrical, gives a high degree of isotropy. Each element in the cascade is separable, so that computational efficiency is high. A favorable tradeoff is achieved among sharpness, smoothness, and the effects of aliasing. Subjective testing, in comparison with other commonly used filters, has shown the clear superiority of this filter.

The two-channel system previously reported has been implemented in hardware using system parameters appropriate to consumer television. The basic system divides the spectrum into lowand high-frequency spatial components. The lows are coarsely sampled and finely quantized and the highs finely sampled and coarsely quantized using a companded, randomized quantizer. The purpose of this experiment was to demonstrate the potential of the system for low-cost practical application, to study the effect of the character of the randomizing noise, and to ascertain that there were no deleterious effects due to interlace, motion, or input noise. Theoretical noise calculations were qualitatively confirmed.

An explorable electrotactile display has been constructed and tested. A thus far neglected sensation was identified and has been shown to be more useful than the more common electrotactile sensations. Exploration of the surface of the electrotactile display elicits a sensation describable as texture. Experiments have indicated that the intensity of this texture sensation is due primarily to the peak applied voltage rather than to current density as is the case for the classical electrotactile sensation. For subjects employing the texture sensation, experimental results are given for approximate thresholds and for the effect of electrode area on these thresholds. A boundary-localization measurement is offered as a measure of the usefulness of the display for textured-area presentation, and form-separation measurements are given as a measure of usefulness for line-drawing presentations. A proposed model for the mechanism producing the texture sensation is offered as a guide for future experimentation and display-engineering development.

In the past two years a Digital Systems Project Laboratory has been developed within the Department of Electrical Engineering at Massachusetts Institute of Technology. The major objective is to allow the student to acquire a working knowledge of digital systems early in his undergraduate career. The emphasis is experimental, but about one-third of the semester is devoted to classroom activities. The classroom portion of the subject is used to present theoretical material normally unavailable to the student until the latter part of his junior year. However, the principal emphasis, even in the classroom, is on the design and implementation of moderately complex digital systems using integrated circuits at realistic speeds. A modular equipment system is described. An evaluation of the subject has been made by the students and most of them consider it to be as interesting and valuable as most classroom subjects.

When resampling an image to a new set of coordinates (for example, when rotating an image), there is often a noticeable loss in image quality. To preserve image quality, the interpolating function used for the resampling should be an ideal low-pass filter. To determine which limited extent convolving functions would provide the best interpolation, five functions were compared: A) nearest neighbor, B) linear, C) cubic B-spline, D) high-resolution cubic spline with edge enhancement (a = -1), and E) high-resolution cubic spline (a = -0.5). The functions which extend over four picture elements (C, D, E) were shown to have a better frequency response than those which extend over one (A) or two (B) pixels. The nearest neighbor function shifted the image up to one-half a pixel. Linear and cubic B-spline interpolation tended to smooth the image. The best response was obtained with the high-resolution cubic spline functions. The location of the resampled points with respect to the initial coordinate system has a dramatic effect on the response of the sampled interpolating function?the data are exactly reproduced when the points are aligned, and the response has the most smoothing when the resampled points are equidistant from the original coordinate points. Thus, at the expense of some increase in computing time, image quality can be improved by resampled using the high-resolution cubic spline function as compared to the nearest neighbor, linear, or cubic B-spline functions.

The tone scale or gradation of a continuous tone picture is the most important factor related to the quality of an image. We have developed special purpose analog and digital circuitry that enables the real-time (30 updates per second) computation of a tone scale transformation which is then applied to a digitized picture being displayed on a television monitor. In our system the tone scale transformations are controlled by knobs that are labeled in terms meaningful to photographic artisans, rather than requiring an operator to specify points on a transfer characteristic, as is common with other systems. These knobs directly specify minimum and maximum densities, brightness, and shadow, highlight, and overall contrast. These control parameters may be selectively enabled by the operator. After the appropriate aesthetic modifications have been achieved on the television display, the operator may initiate the transformation of the complete stored image prior to subsequent computer processing or hard copy output.

The tone scale or gradation of a continuous tone picture is the most important factor related to the quality of an image. We have developed special purpose analog and digital circuitry which enables the real-time (30 updates per second) computation of a tone scale transformation which is then applied to a digitized picture being displayed on a television monitor. In our system the tone scale transformations are controlled by knobs which are labelled in terms meaningful to photographic artisans, rather than requiring an operator to specify points on a transfer characteristic as is common with other systems. These knobs directly specify minimum and maximum densities, brightness, and shadow, highlight and overall contrast. These control parameters may be selectively enabled by the operator. After the appropriate aesthetic modifications have been achieved on the television display, the operator may initiate the transformation of the complete stored image prior to subsequent computer processing or hard copy output.© (1982) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.